| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /* Auto-generated config file hpl_gclk_config.h */ |
| 2 | #ifndef HPL_GCLK_CONFIG_H |
| 3 | #define HPL_GCLK_CONFIG_H |
| 4 | |
| 5 | // <<< Use Configuration Wizard in Context Menu >>> |
| 6 | |
| 7 | // <e> Generic clock generator 0 configuration |
| 8 | // <i> Indicates whether generic clock 0 configuration is enabled or not |
| 9 | // <id> enable_gclk_gen_0 |
| 10 | #ifndef CONF_GCLK_GENERATOR_0_CONFIG |
| 11 | #define CONF_GCLK_GENERATOR_0_CONFIG 1 |
| 12 | #endif |
| 13 | |
| 14 | // <h> Generic Clock Generator Control |
| 15 | // <y> Generic clock generator 0 source |
| 16 | // <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0) |
| 17 | // <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1) |
| 18 | // <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad |
| 19 | // <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1 |
| 20 | // <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) |
| 21 | // <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) |
| 22 | // <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M) |
| 23 | // <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0) |
| 24 | // <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1) |
| 25 | // <i> This defines the clock source for generic clock generator 0 |
| 26 | // <id> gclk_gen_0_oscillator |
| 27 | #ifndef CONF_GCLK_GEN_0_SOURCE |
| Kévin Redon | 4a2d8f4 | 2019-01-24 17:15:10 +0100 | [diff] [blame] | 28 | #define CONF_GCLK_GEN_0_SOURCE GCLK_GENCTRL_SRC_DPLL0 |
| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 29 | #endif |
| 30 | |
| 31 | // <q> Run in Standby |
| 32 | // <i> Indicates whether Run in Standby is enabled or not |
| 33 | // <id> gclk_arch_gen_0_runstdby |
| 34 | #ifndef CONF_GCLK_GEN_0_RUNSTDBY |
| 35 | #define CONF_GCLK_GEN_0_RUNSTDBY 0 |
| 36 | #endif |
| 37 | |
| 38 | // <q> Divide Selection |
| 39 | // <i> Indicates whether Divide Selection is enabled or not |
| 40 | //<id> gclk_gen_0_div_sel |
| 41 | #ifndef CONF_GCLK_GEN_0_DIVSEL |
| 42 | #define CONF_GCLK_GEN_0_DIVSEL 0 |
| 43 | #endif |
| 44 | |
| 45 | // <q> Output Enable |
| 46 | // <i> Indicates whether Output Enable is enabled or not |
| 47 | // <id> gclk_arch_gen_0_oe |
| 48 | #ifndef CONF_GCLK_GEN_0_OE |
| 49 | #define CONF_GCLK_GEN_0_OE 0 |
| 50 | #endif |
| 51 | |
| 52 | // <q> Output Off Value |
| 53 | // <i> Indicates whether Output Off Value is enabled or not |
| 54 | // <id> gclk_arch_gen_0_oov |
| 55 | #ifndef CONF_GCLK_GEN_0_OOV |
| 56 | #define CONF_GCLK_GEN_0_OOV 0 |
| 57 | #endif |
| 58 | |
| 59 | // <q> Improve Duty Cycle |
| 60 | // <i> Indicates whether Improve Duty Cycle is enabled or not |
| 61 | // <id> gclk_arch_gen_0_idc |
| 62 | #ifndef CONF_GCLK_GEN_0_IDC |
| 63 | #define CONF_GCLK_GEN_0_IDC 0 |
| 64 | #endif |
| 65 | |
| 66 | // <q> Generic Clock Generator Enable |
| 67 | // <i> Indicates whether Generic Clock Generator Enable is enabled or not |
| 68 | // <id> gclk_arch_gen_0_enable |
| 69 | #ifndef CONF_GCLK_GEN_0_GENEN |
| 70 | #define CONF_GCLK_GEN_0_GENEN 1 |
| 71 | #endif |
| 72 | // </h> |
| 73 | |
| 74 | //<h> Generic Clock Generator Division |
| 75 | //<o> Generic clock generator 0 division <0x0000-0xFFFF> |
| 76 | // <id> gclk_gen_0_div |
| 77 | #ifndef CONF_GCLK_GEN_0_DIV |
| 78 | #define CONF_GCLK_GEN_0_DIV 1 |
| 79 | #endif |
| 80 | // </h> |
| 81 | // </e> |
| 82 | |
| 83 | // <e> Generic clock generator 1 configuration |
| 84 | // <i> Indicates whether generic clock 1 configuration is enabled or not |
| 85 | // <id> enable_gclk_gen_1 |
| 86 | #ifndef CONF_GCLK_GENERATOR_1_CONFIG |
| 87 | #define CONF_GCLK_GENERATOR_1_CONFIG 1 |
| 88 | #endif |
| 89 | |
| 90 | // <h> Generic Clock Generator Control |
| 91 | // <y> Generic clock generator 1 source |
| 92 | // <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0) |
| 93 | // <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1) |
| 94 | // <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad |
| 95 | // <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) |
| 96 | // <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) |
| 97 | // <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M) |
| 98 | // <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0) |
| 99 | // <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1) |
| 100 | // <i> This defines the clock source for generic clock generator 1 |
| 101 | // <id> gclk_gen_1_oscillator |
| 102 | #ifndef CONF_GCLK_GEN_1_SOURCE |
| 103 | #define CONF_GCLK_GEN_1_SOURCE GCLK_GENCTRL_SRC_DFLL |
| 104 | #endif |
| 105 | |
| 106 | // <q> Run in Standby |
| 107 | // <i> Indicates whether Run in Standby is enabled or not |
| 108 | // <id> gclk_arch_gen_1_runstdby |
| 109 | #ifndef CONF_GCLK_GEN_1_RUNSTDBY |
| 110 | #define CONF_GCLK_GEN_1_RUNSTDBY 0 |
| 111 | #endif |
| 112 | |
| 113 | // <q> Divide Selection |
| 114 | // <i> Indicates whether Divide Selection is enabled or not |
| 115 | //<id> gclk_gen_1_div_sel |
| 116 | #ifndef CONF_GCLK_GEN_1_DIVSEL |
| 117 | #define CONF_GCLK_GEN_1_DIVSEL 0 |
| 118 | #endif |
| 119 | |
| 120 | // <q> Output Enable |
| 121 | // <i> Indicates whether Output Enable is enabled or not |
| 122 | // <id> gclk_arch_gen_1_oe |
| 123 | #ifndef CONF_GCLK_GEN_1_OE |
| 124 | #define CONF_GCLK_GEN_1_OE 0 |
| 125 | #endif |
| 126 | |
| 127 | // <q> Output Off Value |
| 128 | // <i> Indicates whether Output Off Value is enabled or not |
| 129 | // <id> gclk_arch_gen_1_oov |
| 130 | #ifndef CONF_GCLK_GEN_1_OOV |
| 131 | #define CONF_GCLK_GEN_1_OOV 0 |
| 132 | #endif |
| 133 | |
| 134 | // <q> Improve Duty Cycle |
| 135 | // <i> Indicates whether Improve Duty Cycle is enabled or not |
| 136 | // <id> gclk_arch_gen_1_idc |
| 137 | #ifndef CONF_GCLK_GEN_1_IDC |
| 138 | #define CONF_GCLK_GEN_1_IDC 0 |
| 139 | #endif |
| 140 | |
| 141 | // <q> Generic Clock Generator Enable |
| 142 | // <i> Indicates whether Generic Clock Generator Enable is enabled or not |
| 143 | // <id> gclk_arch_gen_1_enable |
| 144 | #ifndef CONF_GCLK_GEN_1_GENEN |
| 145 | #define CONF_GCLK_GEN_1_GENEN 1 |
| 146 | #endif |
| 147 | // </h> |
| 148 | |
| 149 | //<h> Generic Clock Generator Division |
| 150 | //<o> Generic clock generator 1 division <0x0000-0xFFFF> |
| 151 | // <id> gclk_gen_1_div |
| 152 | #ifndef CONF_GCLK_GEN_1_DIV |
| 153 | #define CONF_GCLK_GEN_1_DIV 1 |
| 154 | #endif |
| 155 | // </h> |
| 156 | // </e> |
| 157 | |
| 158 | // <e> Generic clock generator 2 configuration |
| 159 | // <i> Indicates whether generic clock 2 configuration is enabled or not |
| 160 | // <id> enable_gclk_gen_2 |
| 161 | #ifndef CONF_GCLK_GENERATOR_2_CONFIG |
| Kévin Redon | 20abc4f | 2019-01-24 17:32:17 +0100 | [diff] [blame] | 162 | #define CONF_GCLK_GENERATOR_2_CONFIG 1 |
| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 163 | #endif |
| 164 | |
| 165 | // <h> Generic Clock Generator Control |
| 166 | // <y> Generic clock generator 2 source |
| 167 | // <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0) |
| 168 | // <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1) |
| 169 | // <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad |
| 170 | // <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1 |
| 171 | // <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) |
| 172 | // <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) |
| 173 | // <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M) |
| 174 | // <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0) |
| 175 | // <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1) |
| 176 | // <i> This defines the clock source for generic clock generator 2 |
| 177 | // <id> gclk_gen_2_oscillator |
| 178 | #ifndef CONF_GCLK_GEN_2_SOURCE |
| Kévin Redon | 20abc4f | 2019-01-24 17:32:17 +0100 | [diff] [blame] | 179 | #define CONF_GCLK_GEN_2_SOURCE GCLK_GENCTRL_SRC_DPLL1 |
| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 180 | #endif |
| 181 | |
| 182 | // <q> Run in Standby |
| 183 | // <i> Indicates whether Run in Standby is enabled or not |
| 184 | // <id> gclk_arch_gen_2_runstdby |
| 185 | #ifndef CONF_GCLK_GEN_2_RUNSTDBY |
| 186 | #define CONF_GCLK_GEN_2_RUNSTDBY 0 |
| 187 | #endif |
| 188 | |
| 189 | // <q> Divide Selection |
| 190 | // <i> Indicates whether Divide Selection is enabled or not |
| 191 | //<id> gclk_gen_2_div_sel |
| 192 | #ifndef CONF_GCLK_GEN_2_DIVSEL |
| Kévin Redon | 20abc4f | 2019-01-24 17:32:17 +0100 | [diff] [blame] | 193 | #define CONF_GCLK_GEN_2_DIVSEL 0 |
| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 194 | #endif |
| 195 | |
| 196 | // <q> Output Enable |
| 197 | // <i> Indicates whether Output Enable is enabled or not |
| 198 | // <id> gclk_arch_gen_2_oe |
| 199 | #ifndef CONF_GCLK_GEN_2_OE |
| 200 | #define CONF_GCLK_GEN_2_OE 0 |
| 201 | #endif |
| 202 | |
| 203 | // <q> Output Off Value |
| 204 | // <i> Indicates whether Output Off Value is enabled or not |
| 205 | // <id> gclk_arch_gen_2_oov |
| 206 | #ifndef CONF_GCLK_GEN_2_OOV |
| 207 | #define CONF_GCLK_GEN_2_OOV 0 |
| 208 | #endif |
| 209 | |
| 210 | // <q> Improve Duty Cycle |
| 211 | // <i> Indicates whether Improve Duty Cycle is enabled or not |
| 212 | // <id> gclk_arch_gen_2_idc |
| 213 | #ifndef CONF_GCLK_GEN_2_IDC |
| 214 | #define CONF_GCLK_GEN_2_IDC 0 |
| 215 | #endif |
| 216 | |
| 217 | // <q> Generic Clock Generator Enable |
| 218 | // <i> Indicates whether Generic Clock Generator Enable is enabled or not |
| 219 | // <id> gclk_arch_gen_2_enable |
| 220 | #ifndef CONF_GCLK_GEN_2_GENEN |
| Kévin Redon | 4cd3f7d | 2019-01-24 17:57:13 +0100 | [diff] [blame] | 221 | #define CONF_GCLK_GEN_2_GENEN 1 |
| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 222 | #endif |
| 223 | // </h> |
| 224 | |
| 225 | //<h> Generic Clock Generator Division |
| 226 | //<o> Generic clock generator 2 division <0x0000-0xFFFF> |
| 227 | // <id> gclk_gen_2_div |
| 228 | #ifndef CONF_GCLK_GEN_2_DIV |
| Kévin Redon | 5e7cfae | 2019-04-25 15:50:30 +0200 | [diff] [blame] | 229 | #define CONF_GCLK_GEN_2_DIV 200 |
| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 230 | #endif |
| 231 | // </h> |
| 232 | // </e> |
| 233 | |
| 234 | // <e> Generic clock generator 3 configuration |
| 235 | // <i> Indicates whether generic clock 3 configuration is enabled or not |
| 236 | // <id> enable_gclk_gen_3 |
| 237 | #ifndef CONF_GCLK_GENERATOR_3_CONFIG |
| 238 | #define CONF_GCLK_GENERATOR_3_CONFIG 1 |
| 239 | #endif |
| 240 | |
| 241 | // <h> Generic Clock Generator Control |
| 242 | // <y> Generic clock generator 3 source |
| 243 | // <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0) |
| 244 | // <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1) |
| 245 | // <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad |
| 246 | // <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1 |
| 247 | // <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) |
| 248 | // <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) |
| 249 | // <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M) |
| 250 | // <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0) |
| 251 | // <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1) |
| 252 | // <i> This defines the clock source for generic clock generator 3 |
| 253 | // <id> gclk_gen_3_oscillator |
| 254 | #ifndef CONF_GCLK_GEN_3_SOURCE |
| 255 | #define CONF_GCLK_GEN_3_SOURCE GCLK_GENCTRL_SRC_XOSC32K |
| 256 | #endif |
| 257 | |
| 258 | // <q> Run in Standby |
| 259 | // <i> Indicates whether Run in Standby is enabled or not |
| 260 | // <id> gclk_arch_gen_3_runstdby |
| 261 | #ifndef CONF_GCLK_GEN_3_RUNSTDBY |
| 262 | #define CONF_GCLK_GEN_3_RUNSTDBY 0 |
| 263 | #endif |
| 264 | |
| 265 | // <q> Divide Selection |
| 266 | // <i> Indicates whether Divide Selection is enabled or not |
| 267 | //<id> gclk_gen_3_div_sel |
| 268 | #ifndef CONF_GCLK_GEN_3_DIVSEL |
| 269 | #define CONF_GCLK_GEN_3_DIVSEL 0 |
| 270 | #endif |
| 271 | |
| 272 | // <q> Output Enable |
| 273 | // <i> Indicates whether Output Enable is enabled or not |
| 274 | // <id> gclk_arch_gen_3_oe |
| 275 | #ifndef CONF_GCLK_GEN_3_OE |
| 276 | #define CONF_GCLK_GEN_3_OE 0 |
| 277 | #endif |
| 278 | |
| 279 | // <q> Output Off Value |
| 280 | // <i> Indicates whether Output Off Value is enabled or not |
| 281 | // <id> gclk_arch_gen_3_oov |
| 282 | #ifndef CONF_GCLK_GEN_3_OOV |
| 283 | #define CONF_GCLK_GEN_3_OOV 0 |
| 284 | #endif |
| 285 | |
| 286 | // <q> Improve Duty Cycle |
| 287 | // <i> Indicates whether Improve Duty Cycle is enabled or not |
| 288 | // <id> gclk_arch_gen_3_idc |
| 289 | #ifndef CONF_GCLK_GEN_3_IDC |
| 290 | #define CONF_GCLK_GEN_3_IDC 0 |
| 291 | #endif |
| 292 | |
| 293 | // <q> Generic Clock Generator Enable |
| 294 | // <i> Indicates whether Generic Clock Generator Enable is enabled or not |
| 295 | // <id> gclk_arch_gen_3_enable |
| 296 | #ifndef CONF_GCLK_GEN_3_GENEN |
| 297 | #define CONF_GCLK_GEN_3_GENEN 1 |
| 298 | #endif |
| 299 | // </h> |
| 300 | |
| 301 | //<h> Generic Clock Generator Division |
| 302 | //<o> Generic clock generator 3 division <0x0000-0xFFFF> |
| 303 | // <id> gclk_gen_3_div |
| 304 | #ifndef CONF_GCLK_GEN_3_DIV |
| 305 | #define CONF_GCLK_GEN_3_DIV 1 |
| 306 | #endif |
| 307 | // </h> |
| 308 | // </e> |
| 309 | |
| 310 | // <e> Generic clock generator 4 configuration |
| 311 | // <i> Indicates whether generic clock 4 configuration is enabled or not |
| 312 | // <id> enable_gclk_gen_4 |
| 313 | #ifndef CONF_GCLK_GENERATOR_4_CONFIG |
| Kévin Redon | 37e5fa9 | 2019-04-17 01:09:11 +0200 | [diff] [blame] | 314 | #define CONF_GCLK_GENERATOR_4_CONFIG 1 |
| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 315 | #endif |
| 316 | |
| 317 | // <h> Generic Clock Generator Control |
| 318 | // <y> Generic clock generator 4 source |
| 319 | // <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0) |
| 320 | // <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1) |
| 321 | // <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad |
| 322 | // <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1 |
| 323 | // <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) |
| 324 | // <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) |
| 325 | // <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M) |
| 326 | // <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0) |
| 327 | // <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1) |
| 328 | // <i> This defines the clock source for generic clock generator 4 |
| 329 | // <id> gclk_gen_4_oscillator |
| 330 | #ifndef CONF_GCLK_GEN_4_SOURCE |
| Kévin Redon | 37e5fa9 | 2019-04-17 01:09:11 +0200 | [diff] [blame] | 331 | #define CONF_GCLK_GEN_4_SOURCE GCLK_GENCTRL_SRC_DPLL1 |
| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 332 | #endif |
| 333 | |
| 334 | // <q> Run in Standby |
| 335 | // <i> Indicates whether Run in Standby is enabled or not |
| 336 | // <id> gclk_arch_gen_4_runstdby |
| 337 | #ifndef CONF_GCLK_GEN_4_RUNSTDBY |
| 338 | #define CONF_GCLK_GEN_4_RUNSTDBY 0 |
| 339 | #endif |
| 340 | |
| 341 | // <q> Divide Selection |
| 342 | // <i> Indicates whether Divide Selection is enabled or not |
| 343 | //<id> gclk_gen_4_div_sel |
| 344 | #ifndef CONF_GCLK_GEN_4_DIVSEL |
| 345 | #define CONF_GCLK_GEN_4_DIVSEL 0 |
| 346 | #endif |
| 347 | |
| 348 | // <q> Output Enable |
| 349 | // <i> Indicates whether Output Enable is enabled or not |
| 350 | // <id> gclk_arch_gen_4_oe |
| 351 | #ifndef CONF_GCLK_GEN_4_OE |
| Kévin Redon | f53d366 | 2019-04-25 13:55:06 +0200 | [diff] [blame] | 352 | #define CONF_GCLK_GEN_4_OE 1 |
| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 353 | #endif |
| 354 | |
| 355 | // <q> Output Off Value |
| 356 | // <i> Indicates whether Output Off Value is enabled or not |
| 357 | // <id> gclk_arch_gen_4_oov |
| 358 | #ifndef CONF_GCLK_GEN_4_OOV |
| 359 | #define CONF_GCLK_GEN_4_OOV 0 |
| 360 | #endif |
| 361 | |
| 362 | // <q> Improve Duty Cycle |
| 363 | // <i> Indicates whether Improve Duty Cycle is enabled or not |
| 364 | // <id> gclk_arch_gen_4_idc |
| 365 | #ifndef CONF_GCLK_GEN_4_IDC |
| 366 | #define CONF_GCLK_GEN_4_IDC 0 |
| 367 | #endif |
| 368 | |
| 369 | // <q> Generic Clock Generator Enable |
| 370 | // <i> Indicates whether Generic Clock Generator Enable is enabled or not |
| 371 | // <id> gclk_arch_gen_4_enable |
| 372 | #ifndef CONF_GCLK_GEN_4_GENEN |
| Kévin Redon | 37e5fa9 | 2019-04-17 01:09:11 +0200 | [diff] [blame] | 373 | #define CONF_GCLK_GEN_4_GENEN 1 |
| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 374 | #endif |
| 375 | // </h> |
| 376 | |
| 377 | //<h> Generic Clock Generator Division |
| 378 | //<o> Generic clock generator 4 division <0x0000-0xFFFF> |
| 379 | // <id> gclk_gen_4_div |
| 380 | #ifndef CONF_GCLK_GEN_4_DIV |
| Kévin Redon | f53d366 | 2019-04-25 13:55:06 +0200 | [diff] [blame] | 381 | #define CONF_GCLK_GEN_4_DIV 2 |
| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 382 | #endif |
| 383 | // </h> |
| 384 | // </e> |
| 385 | |
| 386 | // <e> Generic clock generator 5 configuration |
| 387 | // <i> Indicates whether generic clock 5 configuration is enabled or not |
| 388 | // <id> enable_gclk_gen_5 |
| 389 | #ifndef CONF_GCLK_GENERATOR_5_CONFIG |
| Kévin Redon | d4ed1ec | 2019-01-30 18:54:59 +0100 | [diff] [blame] | 390 | #define CONF_GCLK_GENERATOR_5_CONFIG 1 |
| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 391 | #endif |
| 392 | |
| 393 | // <h> Generic Clock Generator Control |
| 394 | // <y> Generic clock generator 5 source |
| 395 | // <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0) |
| 396 | // <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1) |
| 397 | // <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad |
| 398 | // <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1 |
| 399 | // <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) |
| 400 | // <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) |
| 401 | // <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M) |
| 402 | // <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0) |
| 403 | // <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1) |
| 404 | // <i> This defines the clock source for generic clock generator 5 |
| 405 | // <id> gclk_gen_5_oscillator |
| 406 | #ifndef CONF_GCLK_GEN_5_SOURCE |
| Kévin Redon | d4ed1ec | 2019-01-30 18:54:59 +0100 | [diff] [blame] | 407 | #define CONF_GCLK_GEN_5_SOURCE GCLK_GENCTRL_SRC_DPLL1 |
| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 408 | #endif |
| 409 | |
| 410 | // <q> Run in Standby |
| 411 | // <i> Indicates whether Run in Standby is enabled or not |
| 412 | // <id> gclk_arch_gen_5_runstdby |
| 413 | #ifndef CONF_GCLK_GEN_5_RUNSTDBY |
| 414 | #define CONF_GCLK_GEN_5_RUNSTDBY 0 |
| 415 | #endif |
| 416 | |
| 417 | // <q> Divide Selection |
| 418 | // <i> Indicates whether Divide Selection is enabled or not |
| 419 | //<id> gclk_gen_5_div_sel |
| 420 | #ifndef CONF_GCLK_GEN_5_DIVSEL |
| 421 | #define CONF_GCLK_GEN_5_DIVSEL 0 |
| 422 | #endif |
| 423 | |
| 424 | // <q> Output Enable |
| 425 | // <i> Indicates whether Output Enable is enabled or not |
| 426 | // <id> gclk_arch_gen_5_oe |
| 427 | #ifndef CONF_GCLK_GEN_5_OE |
| Kévin Redon | d4ed1ec | 2019-01-30 18:54:59 +0100 | [diff] [blame] | 428 | #define CONF_GCLK_GEN_5_OE 1 |
| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 429 | #endif |
| 430 | |
| 431 | // <q> Output Off Value |
| 432 | // <i> Indicates whether Output Off Value is enabled or not |
| 433 | // <id> gclk_arch_gen_5_oov |
| 434 | #ifndef CONF_GCLK_GEN_5_OOV |
| 435 | #define CONF_GCLK_GEN_5_OOV 0 |
| 436 | #endif |
| 437 | |
| 438 | // <q> Improve Duty Cycle |
| 439 | // <i> Indicates whether Improve Duty Cycle is enabled or not |
| 440 | // <id> gclk_arch_gen_5_idc |
| 441 | #ifndef CONF_GCLK_GEN_5_IDC |
| 442 | #define CONF_GCLK_GEN_5_IDC 0 |
| 443 | #endif |
| 444 | |
| 445 | // <q> Generic Clock Generator Enable |
| 446 | // <i> Indicates whether Generic Clock Generator Enable is enabled or not |
| 447 | // <id> gclk_arch_gen_5_enable |
| 448 | #ifndef CONF_GCLK_GEN_5_GENEN |
| Kévin Redon | d4ed1ec | 2019-01-30 18:54:59 +0100 | [diff] [blame] | 449 | #define CONF_GCLK_GEN_5_GENEN 1 |
| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 450 | #endif |
| 451 | // </h> |
| 452 | |
| 453 | //<h> Generic Clock Generator Division |
| 454 | //<o> Generic clock generator 5 division <0x0000-0xFFFF> |
| 455 | // <id> gclk_gen_5_div |
| 456 | #ifndef CONF_GCLK_GEN_5_DIV |
| Eric Wild | 8456e67 | 2019-10-25 16:41:56 +0200 | [diff] [blame] | 457 | #define CONF_GCLK_GEN_5_DIV 5 |
| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 458 | #endif |
| 459 | // </h> |
| 460 | // </e> |
| 461 | |
| 462 | // <e> Generic clock generator 6 configuration |
| 463 | // <i> Indicates whether generic clock 6 configuration is enabled or not |
| 464 | // <id> enable_gclk_gen_6 |
| 465 | #ifndef CONF_GCLK_GENERATOR_6_CONFIG |
| Kévin Redon | 5e7cfae | 2019-04-25 15:50:30 +0200 | [diff] [blame] | 466 | #define CONF_GCLK_GENERATOR_6_CONFIG 1 |
| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 467 | #endif |
| 468 | |
| 469 | // <h> Generic Clock Generator Control |
| 470 | // <y> Generic clock generator 6 source |
| 471 | // <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0) |
| 472 | // <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1) |
| 473 | // <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad |
| 474 | // <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1 |
| 475 | // <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) |
| 476 | // <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) |
| 477 | // <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M) |
| 478 | // <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0) |
| 479 | // <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1) |
| 480 | // <i> This defines the clock source for generic clock generator 6 |
| 481 | // <id> gclk_gen_6_oscillator |
| 482 | #ifndef CONF_GCLK_GEN_6_SOURCE |
| Kévin Redon | 5e7cfae | 2019-04-25 15:50:30 +0200 | [diff] [blame] | 483 | #define CONF_GCLK_GEN_6_SOURCE GCLK_GENCTRL_SRC_DPLL0 |
| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 484 | #endif |
| 485 | |
| 486 | // <q> Run in Standby |
| 487 | // <i> Indicates whether Run in Standby is enabled or not |
| 488 | // <id> gclk_arch_gen_6_runstdby |
| 489 | #ifndef CONF_GCLK_GEN_6_RUNSTDBY |
| 490 | #define CONF_GCLK_GEN_6_RUNSTDBY 0 |
| 491 | #endif |
| 492 | |
| 493 | // <q> Divide Selection |
| 494 | // <i> Indicates whether Divide Selection is enabled or not |
| 495 | //<id> gclk_gen_6_div_sel |
| 496 | #ifndef CONF_GCLK_GEN_6_DIVSEL |
| 497 | #define CONF_GCLK_GEN_6_DIVSEL 0 |
| 498 | #endif |
| 499 | |
| 500 | // <q> Output Enable |
| 501 | // <i> Indicates whether Output Enable is enabled or not |
| 502 | // <id> gclk_arch_gen_6_oe |
| 503 | #ifndef CONF_GCLK_GEN_6_OE |
| 504 | #define CONF_GCLK_GEN_6_OE 0 |
| 505 | #endif |
| 506 | |
| 507 | // <q> Output Off Value |
| 508 | // <i> Indicates whether Output Off Value is enabled or not |
| 509 | // <id> gclk_arch_gen_6_oov |
| 510 | #ifndef CONF_GCLK_GEN_6_OOV |
| 511 | #define CONF_GCLK_GEN_6_OOV 0 |
| 512 | #endif |
| 513 | |
| 514 | // <q> Improve Duty Cycle |
| 515 | // <i> Indicates whether Improve Duty Cycle is enabled or not |
| 516 | // <id> gclk_arch_gen_6_idc |
| 517 | #ifndef CONF_GCLK_GEN_6_IDC |
| 518 | #define CONF_GCLK_GEN_6_IDC 0 |
| 519 | #endif |
| 520 | |
| 521 | // <q> Generic Clock Generator Enable |
| 522 | // <i> Indicates whether Generic Clock Generator Enable is enabled or not |
| 523 | // <id> gclk_arch_gen_6_enable |
| 524 | #ifndef CONF_GCLK_GEN_6_GENEN |
| Kévin Redon | 5e7cfae | 2019-04-25 15:50:30 +0200 | [diff] [blame] | 525 | #define CONF_GCLK_GEN_6_GENEN 1 |
| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 526 | #endif |
| 527 | // </h> |
| 528 | |
| 529 | //<h> Generic Clock Generator Division |
| 530 | //<o> Generic clock generator 6 division <0x0000-0xFFFF> |
| 531 | // <id> gclk_gen_6_div |
| 532 | #ifndef CONF_GCLK_GEN_6_DIV |
| Kévin Redon | 5e7cfae | 2019-04-25 15:50:30 +0200 | [diff] [blame] | 533 | #define CONF_GCLK_GEN_6_DIV 17 |
| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 534 | #endif |
| 535 | // </h> |
| 536 | // </e> |
| 537 | |
| 538 | // <e> Generic clock generator 7 configuration |
| 539 | // <i> Indicates whether generic clock 7 configuration is enabled or not |
| 540 | // <id> enable_gclk_gen_7 |
| 541 | #ifndef CONF_GCLK_GENERATOR_7_CONFIG |
| 542 | #define CONF_GCLK_GENERATOR_7_CONFIG 0 |
| 543 | #endif |
| 544 | |
| 545 | // <h> Generic Clock Generator Control |
| 546 | // <y> Generic clock generator 7 source |
| 547 | // <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0) |
| 548 | // <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1) |
| 549 | // <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad |
| 550 | // <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1 |
| 551 | // <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) |
| 552 | // <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) |
| 553 | // <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M) |
| 554 | // <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0) |
| 555 | // <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1) |
| 556 | // <i> This defines the clock source for generic clock generator 7 |
| 557 | // <id> gclk_gen_7_oscillator |
| 558 | #ifndef CONF_GCLK_GEN_7_SOURCE |
| Kévin Redon | 4e39b01 | 2019-01-30 15:55:58 +0100 | [diff] [blame] | 559 | #define CONF_GCLK_GEN_7_SOURCE GCLK_GENCTRL_SRC_XOSC1 |
| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 560 | #endif |
| 561 | |
| 562 | // <q> Run in Standby |
| 563 | // <i> Indicates whether Run in Standby is enabled or not |
| 564 | // <id> gclk_arch_gen_7_runstdby |
| 565 | #ifndef CONF_GCLK_GEN_7_RUNSTDBY |
| 566 | #define CONF_GCLK_GEN_7_RUNSTDBY 0 |
| 567 | #endif |
| 568 | |
| 569 | // <q> Divide Selection |
| 570 | // <i> Indicates whether Divide Selection is enabled or not |
| 571 | //<id> gclk_gen_7_div_sel |
| 572 | #ifndef CONF_GCLK_GEN_7_DIVSEL |
| 573 | #define CONF_GCLK_GEN_7_DIVSEL 0 |
| 574 | #endif |
| 575 | |
| 576 | // <q> Output Enable |
| 577 | // <i> Indicates whether Output Enable is enabled or not |
| 578 | // <id> gclk_arch_gen_7_oe |
| 579 | #ifndef CONF_GCLK_GEN_7_OE |
| 580 | #define CONF_GCLK_GEN_7_OE 0 |
| 581 | #endif |
| 582 | |
| 583 | // <q> Output Off Value |
| 584 | // <i> Indicates whether Output Off Value is enabled or not |
| 585 | // <id> gclk_arch_gen_7_oov |
| 586 | #ifndef CONF_GCLK_GEN_7_OOV |
| 587 | #define CONF_GCLK_GEN_7_OOV 0 |
| 588 | #endif |
| 589 | |
| 590 | // <q> Improve Duty Cycle |
| 591 | // <i> Indicates whether Improve Duty Cycle is enabled or not |
| 592 | // <id> gclk_arch_gen_7_idc |
| 593 | #ifndef CONF_GCLK_GEN_7_IDC |
| 594 | #define CONF_GCLK_GEN_7_IDC 0 |
| 595 | #endif |
| 596 | |
| 597 | // <q> Generic Clock Generator Enable |
| 598 | // <i> Indicates whether Generic Clock Generator Enable is enabled or not |
| 599 | // <id> gclk_arch_gen_7_enable |
| 600 | #ifndef CONF_GCLK_GEN_7_GENEN |
| 601 | #define CONF_GCLK_GEN_7_GENEN 0 |
| 602 | #endif |
| 603 | // </h> |
| 604 | |
| 605 | //<h> Generic Clock Generator Division |
| 606 | //<o> Generic clock generator 7 division <0x0000-0xFFFF> |
| 607 | // <id> gclk_gen_7_div |
| 608 | #ifndef CONF_GCLK_GEN_7_DIV |
| 609 | #define CONF_GCLK_GEN_7_DIV 1 |
| 610 | #endif |
| 611 | // </h> |
| 612 | // </e> |
| 613 | |
| 614 | // <e> Generic clock generator 8 configuration |
| 615 | // <i> Indicates whether generic clock 8 configuration is enabled or not |
| 616 | // <id> enable_gclk_gen_8 |
| 617 | #ifndef CONF_GCLK_GENERATOR_8_CONFIG |
| 618 | #define CONF_GCLK_GENERATOR_8_CONFIG 0 |
| 619 | #endif |
| 620 | |
| 621 | // <h> Generic Clock Generator Control |
| 622 | // <y> Generic clock generator 8 source |
| 623 | // <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0) |
| 624 | // <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1) |
| 625 | // <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad |
| 626 | // <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1 |
| 627 | // <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) |
| 628 | // <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) |
| 629 | // <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M) |
| 630 | // <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0) |
| 631 | // <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1) |
| 632 | // <i> This defines the clock source for generic clock generator 8 |
| 633 | // <id> gclk_gen_8_oscillator |
| 634 | #ifndef CONF_GCLK_GEN_8_SOURCE |
| Kévin Redon | 4e39b01 | 2019-01-30 15:55:58 +0100 | [diff] [blame] | 635 | #define CONF_GCLK_GEN_8_SOURCE GCLK_GENCTRL_SRC_XOSC1 |
| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 636 | #endif |
| 637 | |
| 638 | // <q> Run in Standby |
| 639 | // <i> Indicates whether Run in Standby is enabled or not |
| 640 | // <id> gclk_arch_gen_8_runstdby |
| 641 | #ifndef CONF_GCLK_GEN_8_RUNSTDBY |
| 642 | #define CONF_GCLK_GEN_8_RUNSTDBY 0 |
| 643 | #endif |
| 644 | |
| 645 | // <q> Divide Selection |
| 646 | // <i> Indicates whether Divide Selection is enabled or not |
| 647 | //<id> gclk_gen_8_div_sel |
| 648 | #ifndef CONF_GCLK_GEN_8_DIVSEL |
| 649 | #define CONF_GCLK_GEN_8_DIVSEL 0 |
| 650 | #endif |
| 651 | |
| 652 | // <q> Output Enable |
| 653 | // <i> Indicates whether Output Enable is enabled or not |
| 654 | // <id> gclk_arch_gen_8_oe |
| 655 | #ifndef CONF_GCLK_GEN_8_OE |
| 656 | #define CONF_GCLK_GEN_8_OE 0 |
| 657 | #endif |
| 658 | |
| 659 | // <q> Output Off Value |
| 660 | // <i> Indicates whether Output Off Value is enabled or not |
| 661 | // <id> gclk_arch_gen_8_oov |
| 662 | #ifndef CONF_GCLK_GEN_8_OOV |
| 663 | #define CONF_GCLK_GEN_8_OOV 0 |
| 664 | #endif |
| 665 | |
| 666 | // <q> Improve Duty Cycle |
| 667 | // <i> Indicates whether Improve Duty Cycle is enabled or not |
| 668 | // <id> gclk_arch_gen_8_idc |
| 669 | #ifndef CONF_GCLK_GEN_8_IDC |
| 670 | #define CONF_GCLK_GEN_8_IDC 0 |
| 671 | #endif |
| 672 | |
| 673 | // <q> Generic Clock Generator Enable |
| 674 | // <i> Indicates whether Generic Clock Generator Enable is enabled or not |
| 675 | // <id> gclk_arch_gen_8_enable |
| 676 | #ifndef CONF_GCLK_GEN_8_GENEN |
| 677 | #define CONF_GCLK_GEN_8_GENEN 0 |
| 678 | #endif |
| 679 | // </h> |
| 680 | |
| 681 | //<h> Generic Clock Generator Division |
| 682 | //<o> Generic clock generator 8 division <0x0000-0xFFFF> |
| 683 | // <id> gclk_gen_8_div |
| 684 | #ifndef CONF_GCLK_GEN_8_DIV |
| 685 | #define CONF_GCLK_GEN_8_DIV 1 |
| 686 | #endif |
| 687 | // </h> |
| 688 | // </e> |
| 689 | |
| 690 | // <e> Generic clock generator 9 configuration |
| 691 | // <i> Indicates whether generic clock 9 configuration is enabled or not |
| 692 | // <id> enable_gclk_gen_9 |
| 693 | #ifndef CONF_GCLK_GENERATOR_9_CONFIG |
| 694 | #define CONF_GCLK_GENERATOR_9_CONFIG 0 |
| 695 | #endif |
| 696 | |
| 697 | // <h> Generic Clock Generator Control |
| 698 | // <y> Generic clock generator 9 source |
| 699 | // <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0) |
| 700 | // <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1) |
| 701 | // <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad |
| 702 | // <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1 |
| 703 | // <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) |
| 704 | // <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) |
| 705 | // <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M) |
| 706 | // <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0) |
| 707 | // <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1) |
| 708 | // <i> This defines the clock source for generic clock generator 9 |
| 709 | // <id> gclk_gen_9_oscillator |
| 710 | #ifndef CONF_GCLK_GEN_9_SOURCE |
| Kévin Redon | 4e39b01 | 2019-01-30 15:55:58 +0100 | [diff] [blame] | 711 | #define CONF_GCLK_GEN_9_SOURCE GCLK_GENCTRL_SRC_XOSC1 |
| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 712 | #endif |
| 713 | |
| 714 | // <q> Run in Standby |
| 715 | // <i> Indicates whether Run in Standby is enabled or not |
| 716 | // <id> gclk_arch_gen_9_runstdby |
| 717 | #ifndef CONF_GCLK_GEN_9_RUNSTDBY |
| 718 | #define CONF_GCLK_GEN_9_RUNSTDBY 0 |
| 719 | #endif |
| 720 | |
| 721 | // <q> Divide Selection |
| 722 | // <i> Indicates whether Divide Selection is enabled or not |
| 723 | //<id> gclk_gen_9_div_sel |
| 724 | #ifndef CONF_GCLK_GEN_9_DIVSEL |
| 725 | #define CONF_GCLK_GEN_9_DIVSEL 0 |
| 726 | #endif |
| 727 | |
| 728 | // <q> Output Enable |
| 729 | // <i> Indicates whether Output Enable is enabled or not |
| 730 | // <id> gclk_arch_gen_9_oe |
| 731 | #ifndef CONF_GCLK_GEN_9_OE |
| 732 | #define CONF_GCLK_GEN_9_OE 0 |
| 733 | #endif |
| 734 | |
| 735 | // <q> Output Off Value |
| 736 | // <i> Indicates whether Output Off Value is enabled or not |
| 737 | // <id> gclk_arch_gen_9_oov |
| 738 | #ifndef CONF_GCLK_GEN_9_OOV |
| 739 | #define CONF_GCLK_GEN_9_OOV 0 |
| 740 | #endif |
| 741 | |
| 742 | // <q> Improve Duty Cycle |
| 743 | // <i> Indicates whether Improve Duty Cycle is enabled or not |
| 744 | // <id> gclk_arch_gen_9_idc |
| 745 | #ifndef CONF_GCLK_GEN_9_IDC |
| 746 | #define CONF_GCLK_GEN_9_IDC 0 |
| 747 | #endif |
| 748 | |
| 749 | // <q> Generic Clock Generator Enable |
| 750 | // <i> Indicates whether Generic Clock Generator Enable is enabled or not |
| 751 | // <id> gclk_arch_gen_9_enable |
| 752 | #ifndef CONF_GCLK_GEN_9_GENEN |
| 753 | #define CONF_GCLK_GEN_9_GENEN 0 |
| 754 | #endif |
| 755 | // </h> |
| 756 | |
| 757 | //<h> Generic Clock Generator Division |
| 758 | //<o> Generic clock generator 9 division <0x0000-0xFFFF> |
| 759 | // <id> gclk_gen_9_div |
| 760 | #ifndef CONF_GCLK_GEN_9_DIV |
| 761 | #define CONF_GCLK_GEN_9_DIV 1 |
| 762 | #endif |
| 763 | // </h> |
| 764 | // </e> |
| 765 | |
| 766 | // <e> Generic clock generator 10 configuration |
| 767 | // <i> Indicates whether generic clock 10 configuration is enabled or not |
| 768 | // <id> enable_gclk_gen_10 |
| 769 | #ifndef CONF_GCLK_GENERATOR_10_CONFIG |
| 770 | #define CONF_GCLK_GENERATOR_10_CONFIG 0 |
| 771 | #endif |
| 772 | |
| 773 | // <h> Generic Clock Generator Control |
| 774 | // <y> Generic clock generator 10 source |
| 775 | // <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0) |
| 776 | // <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1) |
| 777 | // <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad |
| 778 | // <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1 |
| 779 | // <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) |
| 780 | // <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) |
| 781 | // <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M) |
| 782 | // <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0) |
| 783 | // <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1) |
| 784 | // <i> This defines the clock source for generic clock generator 10 |
| 785 | // <id> gclk_gen_10_oscillator |
| 786 | #ifndef CONF_GCLK_GEN_10_SOURCE |
| Kévin Redon | 4e39b01 | 2019-01-30 15:55:58 +0100 | [diff] [blame] | 787 | #define CONF_GCLK_GEN_10_SOURCE GCLK_GENCTRL_SRC_XOSC1 |
| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 788 | #endif |
| 789 | |
| 790 | // <q> Run in Standby |
| 791 | // <i> Indicates whether Run in Standby is enabled or not |
| 792 | // <id> gclk_arch_gen_10_runstdby |
| 793 | #ifndef CONF_GCLK_GEN_10_RUNSTDBY |
| 794 | #define CONF_GCLK_GEN_10_RUNSTDBY 0 |
| 795 | #endif |
| 796 | |
| 797 | // <q> Divide Selection |
| 798 | // <i> Indicates whether Divide Selection is enabled or not |
| 799 | //<id> gclk_gen_10_div_sel |
| 800 | #ifndef CONF_GCLK_GEN_10_DIVSEL |
| 801 | #define CONF_GCLK_GEN_10_DIVSEL 0 |
| 802 | #endif |
| 803 | |
| 804 | // <q> Output Enable |
| 805 | // <i> Indicates whether Output Enable is enabled or not |
| 806 | // <id> gclk_arch_gen_10_oe |
| 807 | #ifndef CONF_GCLK_GEN_10_OE |
| 808 | #define CONF_GCLK_GEN_10_OE 0 |
| 809 | #endif |
| 810 | |
| 811 | // <q> Output Off Value |
| 812 | // <i> Indicates whether Output Off Value is enabled or not |
| 813 | // <id> gclk_arch_gen_10_oov |
| 814 | #ifndef CONF_GCLK_GEN_10_OOV |
| 815 | #define CONF_GCLK_GEN_10_OOV 0 |
| 816 | #endif |
| 817 | |
| 818 | // <q> Improve Duty Cycle |
| 819 | // <i> Indicates whether Improve Duty Cycle is enabled or not |
| 820 | // <id> gclk_arch_gen_10_idc |
| 821 | #ifndef CONF_GCLK_GEN_10_IDC |
| 822 | #define CONF_GCLK_GEN_10_IDC 0 |
| 823 | #endif |
| 824 | |
| 825 | // <q> Generic Clock Generator Enable |
| 826 | // <i> Indicates whether Generic Clock Generator Enable is enabled or not |
| 827 | // <id> gclk_arch_gen_10_enable |
| 828 | #ifndef CONF_GCLK_GEN_10_GENEN |
| 829 | #define CONF_GCLK_GEN_10_GENEN 0 |
| 830 | #endif |
| 831 | // </h> |
| 832 | |
| 833 | //<h> Generic Clock Generator Division |
| 834 | //<o> Generic clock generator 10 division <0x0000-0xFFFF> |
| 835 | // <id> gclk_gen_10_div |
| 836 | #ifndef CONF_GCLK_GEN_10_DIV |
| 837 | #define CONF_GCLK_GEN_10_DIV 1 |
| 838 | #endif |
| 839 | // </h> |
| 840 | // </e> |
| 841 | |
| 842 | // <e> Generic clock generator 11 configuration |
| 843 | // <i> Indicates whether generic clock 11 configuration is enabled or not |
| 844 | // <id> enable_gclk_gen_11 |
| 845 | #ifndef CONF_GCLK_GENERATOR_11_CONFIG |
| Kévin Redon | 4cb8e32 | 2019-01-24 17:41:44 +0100 | [diff] [blame] | 846 | #define CONF_GCLK_GENERATOR_11_CONFIG 0 |
| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 847 | #endif |
| 848 | |
| 849 | // <h> Generic Clock Generator Control |
| 850 | // <y> Generic clock generator 11 source |
| 851 | // <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0) |
| 852 | // <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1) |
| 853 | // <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad |
| 854 | // <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1 |
| 855 | // <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) |
| 856 | // <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) |
| 857 | // <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M) |
| 858 | // <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0) |
| 859 | // <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1) |
| 860 | // <i> This defines the clock source for generic clock generator 11 |
| 861 | // <id> gclk_gen_11_oscillator |
| 862 | #ifndef CONF_GCLK_GEN_11_SOURCE |
| Kévin Redon | 4a2d8f4 | 2019-01-24 17:15:10 +0100 | [diff] [blame] | 863 | #define CONF_GCLK_GEN_11_SOURCE GCLK_GENCTRL_SRC_XOSC1 |
| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 864 | #endif |
| 865 | |
| 866 | // <q> Run in Standby |
| 867 | // <i> Indicates whether Run in Standby is enabled or not |
| 868 | // <id> gclk_arch_gen_11_runstdby |
| 869 | #ifndef CONF_GCLK_GEN_11_RUNSTDBY |
| 870 | #define CONF_GCLK_GEN_11_RUNSTDBY 0 |
| 871 | #endif |
| 872 | |
| 873 | // <q> Divide Selection |
| 874 | // <i> Indicates whether Divide Selection is enabled or not |
| 875 | //<id> gclk_gen_11_div_sel |
| 876 | #ifndef CONF_GCLK_GEN_11_DIVSEL |
| 877 | #define CONF_GCLK_GEN_11_DIVSEL 0 |
| 878 | #endif |
| 879 | |
| 880 | // <q> Output Enable |
| 881 | // <i> Indicates whether Output Enable is enabled or not |
| 882 | // <id> gclk_arch_gen_11_oe |
| 883 | #ifndef CONF_GCLK_GEN_11_OE |
| 884 | #define CONF_GCLK_GEN_11_OE 0 |
| 885 | #endif |
| 886 | |
| 887 | // <q> Output Off Value |
| 888 | // <i> Indicates whether Output Off Value is enabled or not |
| 889 | // <id> gclk_arch_gen_11_oov |
| 890 | #ifndef CONF_GCLK_GEN_11_OOV |
| 891 | #define CONF_GCLK_GEN_11_OOV 0 |
| 892 | #endif |
| 893 | |
| 894 | // <q> Improve Duty Cycle |
| 895 | // <i> Indicates whether Improve Duty Cycle is enabled or not |
| 896 | // <id> gclk_arch_gen_11_idc |
| 897 | #ifndef CONF_GCLK_GEN_11_IDC |
| 898 | #define CONF_GCLK_GEN_11_IDC 0 |
| 899 | #endif |
| 900 | |
| 901 | // <q> Generic Clock Generator Enable |
| 902 | // <i> Indicates whether Generic Clock Generator Enable is enabled or not |
| 903 | // <id> gclk_arch_gen_11_enable |
| 904 | #ifndef CONF_GCLK_GEN_11_GENEN |
| Kévin Redon | 6b9363c | 2019-01-24 17:21:33 +0100 | [diff] [blame] | 905 | #define CONF_GCLK_GEN_11_GENEN 0 |
| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 906 | #endif |
| 907 | // </h> |
| 908 | |
| 909 | //<h> Generic Clock Generator Division |
| 910 | //<o> Generic clock generator 11 division <0x0000-0xFFFF> |
| 911 | // <id> gclk_gen_11_div |
| 912 | #ifndef CONF_GCLK_GEN_11_DIV |
| Kévin Redon | 4a2d8f4 | 2019-01-24 17:15:10 +0100 | [diff] [blame] | 913 | #define CONF_GCLK_GEN_11_DIV 6 |
| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 914 | #endif |
| 915 | // </h> |
| 916 | // </e> |
| 917 | |
| 918 | // <<< end of configuration section >>> |
| 919 | |
| 920 | #endif // HPL_GCLK_CONFIG_H |