output 50 MHz for RMII
in hardware revision 2 the Ethernet PHY RMII_CLOCK input clock is
connected to the MCU pin PA10.
GCLK4 of the MCU now outputs the required 50 MHz clock on this pin.
the same clock is re-used for UART debug to generate the 921600
bps baud rate.
Change-Id: Id3a3dee15c3986536b0623d0f39ca62e94acd1fd
diff --git a/sysmoOCTSIM/config/hpl_gclk_config.h b/sysmoOCTSIM/config/hpl_gclk_config.h
index 71c26e1..81a1f03 100644
--- a/sysmoOCTSIM/config/hpl_gclk_config.h
+++ b/sysmoOCTSIM/config/hpl_gclk_config.h
@@ -349,7 +349,7 @@
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_4_oe
#ifndef CONF_GCLK_GEN_4_OE
-#define CONF_GCLK_GEN_4_OE 0
+#define CONF_GCLK_GEN_4_OE 1
#endif
// <q> Output Off Value
@@ -378,7 +378,7 @@
//<o> Generic clock generator 4 division <0x0000-0xFFFF>
// <id> gclk_gen_4_div
#ifndef CONF_GCLK_GEN_4_DIV
-#define CONF_GCLK_GEN_4_DIV 1
+#define CONF_GCLK_GEN_4_DIV 2
#endif
// </h>
// </e>