use XOSC1 directly for DPLL1
DPLL1 can take directly XOSC1 as input and divide it to 2 MHz.
thus the intermediate GCLK11 is not needed.
we now also completely de-configure GCLK11
this configuration is not supported by Atmel START since it does
not know about the division and thinks the input frequency
exceeds the maximum
GCLK2 is also disabled for now because it is not used
Change-Id: Icee7f5a13019c47cebc23376cabb18cb31178ece
diff --git a/sysmoOCTSIM/config/hpl_gclk_config.h b/sysmoOCTSIM/config/hpl_gclk_config.h
index 398a617..0ad8ead 100644
--- a/sysmoOCTSIM/config/hpl_gclk_config.h
+++ b/sysmoOCTSIM/config/hpl_gclk_config.h
@@ -218,7 +218,7 @@
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_2_enable
#ifndef CONF_GCLK_GEN_2_GENEN
-#define CONF_GCLK_GEN_2_GENEN 1
+#define CONF_GCLK_GEN_2_GENEN 0
#endif
// </h>
@@ -843,7 +843,7 @@
// <i> Indicates whether generic clock 11 configuration is enabled or not
// <id> enable_gclk_gen_11
#ifndef CONF_GCLK_GENERATOR_11_CONFIG
-#define CONF_GCLK_GENERATOR_11_CONFIG 1
+#define CONF_GCLK_GENERATOR_11_CONFIG 0
#endif
// <h> Generic Clock Generator Control