| commit | f53d366c1d3daa0f5ac88af7b8a1ce53a5018a2c | [log] [tgz] |
|---|---|---|
| author | Kévin Redon <kredon@sysmocom.de> | Thu Apr 25 13:55:06 2019 +0200 |
| committer | Kévin Redon <kredon@sysmocom.de> | Thu May 09 15:46:38 2019 +0200 |
| tree | 3035dfb4e4aca90d649eb3d83fc40e6c50ae9c24 | |
| parent | 0c3533fc0915d0d4e43f740f4ea739e51781dd88 [diff] |
output 50 MHz for RMII in hardware revision 2 the Ethernet PHY RMII_CLOCK input clock is connected to the MCU pin PA10. GCLK4 of the MCU now outputs the required 50 MHz clock on this pin. the same clock is re-used for UART debug to generate the 921600 bps baud rate. Change-Id: Id3a3dee15c3986536b0623d0f39ca62e94acd1fd