switch CPU clock to 120 MHz
use GCLK11 to bring external crystal oscillator XOSC1 from 12 MHz
to 2MHz
use DPLL0 to multiply 2 MHz to 120 MHz.
the division is first needed because the DPLL0 maximum input
frequency is 3.2 MHz
Change-Id: I642e724ec56a376addf21cc58ecd2ef1b40bd116
diff --git a/sysmoOCTSIM/config/hpl_gclk_config.h b/sysmoOCTSIM/config/hpl_gclk_config.h
index 306d90e..8d10f38 100644
--- a/sysmoOCTSIM/config/hpl_gclk_config.h
+++ b/sysmoOCTSIM/config/hpl_gclk_config.h
@@ -25,7 +25,7 @@
// <i> This defines the clock source for generic clock generator 0
// <id> gclk_gen_0_oscillator
#ifndef CONF_GCLK_GEN_0_SOURCE
-#define CONF_GCLK_GEN_0_SOURCE GCLK_GENCTRL_SRC_XOSC1
+#define CONF_GCLK_GEN_0_SOURCE GCLK_GENCTRL_SRC_DPLL0
#endif
// <q> Run in Standby
@@ -843,7 +843,7 @@
// <i> Indicates whether generic clock 11 configuration is enabled or not
// <id> enable_gclk_gen_11
#ifndef CONF_GCLK_GENERATOR_11_CONFIG
-#define CONF_GCLK_GENERATOR_11_CONFIG 0
+#define CONF_GCLK_GENERATOR_11_CONFIG 1
#endif
// <h> Generic Clock Generator Control
@@ -860,7 +860,7 @@
// <i> This defines the clock source for generic clock generator 11
// <id> gclk_gen_11_oscillator
#ifndef CONF_GCLK_GEN_11_SOURCE
-#define CONF_GCLK_GEN_11_SOURCE GCLK_GENCTRL_SRC_XOSC0
+#define CONF_GCLK_GEN_11_SOURCE GCLK_GENCTRL_SRC_XOSC1
#endif
// <q> Run in Standby
@@ -902,7 +902,7 @@
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_11_enable
#ifndef CONF_GCLK_GEN_11_GENEN
-#define CONF_GCLK_GEN_11_GENEN 0
+#define CONF_GCLK_GEN_11_GENEN 1
#endif
// </h>
@@ -910,7 +910,7 @@
//<o> Generic clock generator 11 division <0x0000-0xFFFF>
// <id> gclk_gen_11_div
#ifndef CONF_GCLK_GEN_11_DIV
-#define CONF_GCLK_GEN_11_DIV 1
+#define CONF_GCLK_GEN_11_DIV 6
#endif
// </h>
// </e>