| commit | 6b9363ca8e161dbd2922058340df576465eb7439 | [log] [tgz] |
|---|---|---|
| author | Kévin Redon <kredon@sysmocom.de> | Thu Jan 24 17:21:33 2019 +0100 |
| committer | Kévin Redon <kredon@sysmocom.de> | Thu Feb 07 15:56:04 2019 +0100 |
| tree | c7bd27b7ecc2d5e9621bbd2e8c72006c6d119b06 | |
| parent | 4a2d8f4773a18d35080c10a63607095dd34901be [diff] |
remove usage of GCLK11 DPLL0 can take directly XOSC1 as input and divide it to 2 MHz. thus the intermediate GCLK11 is not needed. this configuration is not supported by Atmel START since it does not know about the division and thinks the input frequency exceeds the maximum Change-Id: I121ad850cf118b641fe522b513ffd7e00b30b710