blob: ac98215eb023354dd58476ed1838753d712f7119 [file] [log] [blame]
Neels Hofmeyr3cf797d2018-04-05 16:56:38 +02001<?xml version="1.0"?>
Neels Hofmeyrcb8d9892021-07-02 18:03:52 +02002<testsuite name='Titan' tests='199' failures='6' errors='0' skipped='0' inconc='0' time='MASKED'>
Neels Hofmeyrfc0384a2018-04-11 15:56:41 +02003 <testcase classname='MSC_Tests' name='TC_cr_before_reset' time='MASKED'/>
4 <testcase classname='MSC_Tests' name='TC_lu_imsi_noauth_tmsi' time='MASKED'/>
5 <testcase classname='MSC_Tests' name='TC_lu_imsi_noauth_notmsi' time='MASKED'/>
Neels Hofmeyr873ae202018-09-06 14:13:34 +02006 <testcase classname='MSC_Tests' name='TC_lu_imsi_reject' time='MASKED'/>
7 <testcase classname='MSC_Tests' name='TC_lu_imsi_timeout_gsup' time='MASKED'/>
Neels Hofmeyrfc0384a2018-04-11 15:56:41 +02008 <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi' time='MASKED'/>
Oliver Smithbe4c5312019-07-23 15:00:04 +02009 <testcase classname='MSC_Tests' name='TC_lu_imsi_auth3g_tmsi' time='MASKED'/>
Pau Espin Pedrold3d54a92019-12-17 17:02:54 +010010 <testcase classname='MSC_Tests' name='TC_lu_imsi_timeout_tmsi_realloc' time='MASKED'>
11 <failure type='fail-verdict'>Timeout waiting for ClearCommand/Release
Neels Hofmeyra4d21002020-05-14 21:10:28 +020012 MSC_Tests.ttcn:MASKED MSC_Tests control part
Pau Espin Pedrold3d54a92019-12-17 17:02:54 +010013 MSC_Tests.ttcn:MASKED TC_lu_imsi_timeout_tmsi_realloc testcase
14 </failure>
15 </testcase>
Neels Hofmeyrfc0384a2018-04-11 15:56:41 +020016 <testcase classname='MSC_Tests' name='TC_cmserv_imsi_unknown' time='MASKED'/>
Neels Hofmeyr929b4062020-09-11 18:24:23 +000017 <testcase classname='MSC_Tests' name='TC_cmserv_tmsi_unknown' time='MASKED'/>
Neels Hofmeyrfc0384a2018-04-11 15:56:41 +020018 <testcase classname='MSC_Tests' name='TC_lu_and_mo_call' time='MASKED'/>
Neels Hofmeyr929b4062020-09-11 18:24:23 +000019 <testcase classname='MSC_Tests' name='TC_lu_and_mo_call_ipv6' time='MASKED'/>
Pau Espin Pedrola42745c2020-01-10 18:03:28 +010020 <testcase classname='MSC_Tests' name='TC_lu_and_mo_call_sccp_tiar_timeout' time='MASKED'/>
Neels Hofmeyrfc0384a2018-04-11 15:56:41 +020021 <testcase classname='MSC_Tests' name='TC_lu_auth_sai_timeout' time='MASKED'/>
22 <testcase classname='MSC_Tests' name='TC_lu_auth_sai_err' time='MASKED'/>
Neels Hofmeyrde172222018-05-02 11:59:18 +020023 <testcase classname='MSC_Tests' name='TC_lu_clear_request' time='MASKED'/>
Neels Hofmeyrcb8d9892021-07-02 18:03:52 +020024 <testcase classname='MSC_Tests' name='TC_mo_call_clear_request' time='MASKED'/>
25 <testcase classname='MSC_Tests' name='TC_mt_call_clear_request' time='MASKED'/>
Neels Hofmeyrfc0384a2018-04-11 15:56:41 +020026 <testcase classname='MSC_Tests' name='TC_lu_disconnect' time='MASKED'/>
27 <testcase classname='MSC_Tests' name='TC_lu_by_imei' time='MASKED'/>
28 <testcase classname='MSC_Tests' name='TC_lu_by_tmsi_noauth_unknown' time='MASKED'/>
Neels Hofmeyr929b4062020-09-11 18:24:23 +000029 <testcase classname='MSC_Tests' name='TC_attached_imsi_lu_unknown_tmsi' time='MASKED'>
30 <failure type='fail-verdict'>Expected LU ACK, but received REJ
31 MSC_Tests.ttcn:MASKED MSC_Tests control part
32 MSC_Tests.ttcn:MASKED TC_attached_imsi_lu_unknown_tmsi testcase
33 </failure>
34 </testcase>
Neels Hofmeyrfc0384a2018-04-11 15:56:41 +020035 <testcase classname='MSC_Tests' name='TC_imsi_detach_by_imsi' time='MASKED'/>
36 <testcase classname='MSC_Tests' name='TC_imsi_detach_by_tmsi' time='MASKED'/>
37 <testcase classname='MSC_Tests' name='TC_imsi_detach_by_imei' time='MASKED'/>
Neels Hofmeyrde172222018-05-02 11:59:18 +020038 <testcase classname='MSC_Tests' name='TC_emerg_call_imei_reject' time='MASKED'/>
Neels Hofmeyrfc0384a2018-04-11 15:56:41 +020039 <testcase classname='MSC_Tests' name='TC_emerg_call_imsi' time='MASKED'/>
Neels Hofmeyrde172222018-05-02 11:59:18 +020040 <testcase classname='MSC_Tests' name='TC_cm_serv_req_vgcs_reject' time='MASKED'/>
41 <testcase classname='MSC_Tests' name='TC_cm_serv_req_vbs_reject' time='MASKED'/>
42 <testcase classname='MSC_Tests' name='TC_cm_serv_req_lcs_reject' time='MASKED'/>
43 <testcase classname='MSC_Tests' name='TC_cm_reest_req_reject' time='MASKED'/>
Neels Hofmeyrfc0384a2018-04-11 15:56:41 +020044 <testcase classname='MSC_Tests' name='TC_lu_auth_2G_fail' time='MASKED'/>
45 <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_encr_13_13' time='MASKED'/>
46 <testcase classname='MSC_Tests' name='TC_cl3_no_payload' time='MASKED'/>
Neels Hofmeyrde172222018-05-02 11:59:18 +020047 <testcase classname='MSC_Tests' name='TC_cl3_rnd_payload' time='MASKED'/>
Stefan Sperlingf46eb262018-06-01 17:30:45 +020048 <testcase classname='MSC_Tests' name='TC_establish_and_nothing' time='MASKED'/>
Neels Hofmeyr2caf3492019-01-23 12:44:09 +010049 <testcase classname='MSC_Tests' name='TC_mo_setup_and_nothing' time='MASKED'/>
Neels Hofmeyrfc0384a2018-04-11 15:56:41 +020050 <testcase classname='MSC_Tests' name='TC_mo_crcx_ran_timeout' time='MASKED'/>
51 <testcase classname='MSC_Tests' name='TC_mo_crcx_ran_reject' time='MASKED'/>
Oliver Smithbe4c5312019-07-23 15:00:04 +020052 <testcase classname='MSC_Tests' name='TC_mt_crcx_ran_reject' time='MASKED'/>
Neels Hofmeyrfc0384a2018-04-11 15:56:41 +020053 <testcase classname='MSC_Tests' name='TC_mo_setup_and_dtmf_dup' time='MASKED'/>
Neels Hofmeyrcb8d9892021-07-02 18:03:52 +020054 <testcase classname='MSC_Tests' name='TC_mt_t310' time='MASKED'/>
Neels Hofmeyr2caf3492019-01-23 12:44:09 +010055 <testcase classname='MSC_Tests' name='TC_gsup_cancel' time='MASKED'/>
Neels Hofmeyrfc0384a2018-04-11 15:56:41 +020056 <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_encr_1_13' time='MASKED'/>
57 <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_encr_3_13' time='MASKED'/>
58 <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_encr_3_1' time='MASKED'/>
59 <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_encr_3_1_no_cm' time='MASKED'/>
60 <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_encr_13_2' time='MASKED'/>
61 <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_encr_013_2' time='MASKED'/>
Eric Wild26f4a622021-05-17 15:27:05 +020062 <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_encr_0134_1' time='MASKED'/>
63 <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_encr_0134_34' time='MASKED'/>
64 <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_encr_0134_34_no_cm3' time='MASKED'/>
Neels Hofmeyrfc0384a2018-04-11 15:56:41 +020065 <testcase classname='MSC_Tests' name='TC_mo_release_timeout' time='MASKED'/>
66 <testcase classname='MSC_Tests' name='TC_lu_and_mt_call_no_dlcx_resp' time='MASKED'/>
67 <testcase classname='MSC_Tests' name='TC_reset_two' time='MASKED'/>
68 <testcase classname='MSC_Tests' name='TC_lu_and_mt_call' time='MASKED'/>
Neels Hofmeyr929b4062020-09-11 18:24:23 +000069 <testcase classname='MSC_Tests' name='TC_lu_and_mt_call_ipv6' time='MASKED'/>
Neels Hofmeyra4d21002020-05-14 21:10:28 +020070 <testcase classname='MSC_Tests' name='TC_lu_and_mt_call_already_paging' time='MASKED'/>
Neels Hofmeyrcb8d9892021-07-02 18:03:52 +020071 <testcase classname='MSC_Tests' name='TC_lu_and_mt_call_osmux' time='MASKED'/>
Neels Hofmeyr98d428d2018-04-11 15:54:07 +020072 <testcase classname='MSC_Tests' name='TC_lu_and_mo_sms' time='MASKED'/>
Neels Hofmeyrde172222018-05-02 11:59:18 +020073 <testcase classname='MSC_Tests' name='TC_lu_and_mt_sms' time='MASKED'/>
Neels Hofmeyra4d21002020-05-14 21:10:28 +020074 <testcase classname='MSC_Tests' name='TC_lu_and_mt_sms_already_paging' time='MASKED'/>
Philipp Maier3983e702018-11-22 19:01:33 +010075 <testcase classname='MSC_Tests' name='TC_lu_and_mt_sms_paging_and_nothing' time='MASKED'/>
Neels Hofmeyra4d21002020-05-14 21:10:28 +020076 <testcase classname='MSC_Tests' name='TC_lu_and_mt_sms_paging_repeated' time='MASKED'/>
Neels Hofmeyrde172222018-05-02 11:59:18 +020077 <testcase classname='MSC_Tests' name='TC_smpp_mo_sms' time='MASKED'/>
Vadim Yanitskiy33820762020-01-15 11:26:07 +070078 <testcase classname='MSC_Tests' name='TC_smpp_mo_sms_rp_error' time='MASKED'/>
Neels Hofmeyrde172222018-05-02 11:59:18 +020079 <testcase classname='MSC_Tests' name='TC_smpp_mt_sms' time='MASKED'/>
Vadim Yanitskiy103d09f2018-11-12 02:50:23 +070080 <testcase classname='MSC_Tests' name='TC_gsup_mo_sms' time='MASKED'/>
Vadim Yanitskiy9cc019a2018-11-15 02:06:07 +070081 <testcase classname='MSC_Tests' name='TC_gsup_mo_smma' time='MASKED'/>
Vadim Yanitskiyd7b37ab2018-11-24 03:40:20 +070082 <testcase classname='MSC_Tests' name='TC_gsup_mt_sms_ack' time='MASKED'/>
83 <testcase classname='MSC_Tests' name='TC_gsup_mt_sms_err' time='MASKED'/>
Vadim Yanitskiybe1ff4b2019-01-18 15:04:13 +070084 <testcase classname='MSC_Tests' name='TC_gsup_mt_sms_rp_mr' time='MASKED'/>
Vadim Yanitskiy5ac49cc2019-01-24 16:57:31 +070085 <testcase classname='MSC_Tests' name='TC_gsup_mo_mt_sms_rp_mr' time='MASKED'/>
Oliver Smithbe4c5312019-07-23 15:00:04 +020086 <testcase classname='MSC_Tests' name='TC_gsup_mt_multi_part_sms' time='MASKED'/>
Vadim Yanitskiy2a978b92018-06-19 17:51:20 +070087 <testcase classname='MSC_Tests' name='TC_lu_and_mo_ussd_single_request' time='MASKED'/>
Vadim Yanitskiy13e4a272018-06-19 18:24:31 +070088 <testcase classname='MSC_Tests' name='TC_lu_and_mt_ussd_notification' time='MASKED'/>
Vadim Yanitskiy2a978b92018-06-19 17:51:20 +070089 <testcase classname='MSC_Tests' name='TC_lu_and_mo_ussd_during_mt_call' time='MASKED'/>
Vadim Yanitskiy13e4a272018-06-19 18:24:31 +070090 <testcase classname='MSC_Tests' name='TC_lu_and_mt_ussd_during_mt_call' time='MASKED'/>
Vadim Yanitskiy2daf52d2018-06-21 04:19:58 +070091 <testcase classname='MSC_Tests' name='TC_lu_and_mo_ussd_mo_release' time='MASKED'/>
Vadim Yanitskiy78329c72019-06-17 23:20:00 +070092 <testcase classname='MSC_Tests' name='TC_lu_and_ss_session_timeout' time='MASKED'/>
93 <testcase classname='MSC_Tests' name='TC_mt_ussd_for_unknown_subscr' time='MASKED'/>
94 <testcase classname='MSC_Tests' name='TC_mo_ussd_for_unknown_trans' time='MASKED'/>
95 <testcase classname='MSC_Tests' name='TC_proc_ss_for_unknown_session' time='MASKED'/>
96 <testcase classname='MSC_Tests' name='TC_proc_ss_paging_fail' time='MASKED'/>
97 <testcase classname='MSC_Tests' name='TC_proc_ss_abort' time='MASKED'/>
Vadim Yanitskiy1c9754d2020-01-07 21:56:55 +010098 <testcase classname='MSC_Tests' name='TC_multi_lu_and_mo_ussd' time='MASKED'/>
99 <testcase classname='MSC_Tests' name='TC_multi_lu_and_mt_ussd' time='MASKED'/>
Stefan Sperling89eb1f32018-12-17 15:06:20 +0100100 <testcase classname='MSC_Tests' name='TC_cipher_complete_with_invalid_cipher' time='MASKED'/>
Oliver Smithbe4c5312019-07-23 15:00:04 +0200101 <testcase classname='MSC_Tests' name='TC_cipher_complete_1_without_cipher' time='MASKED'/>
102 <testcase classname='MSC_Tests' name='TC_cipher_complete_3_without_cipher' time='MASKED'/>
103 <testcase classname='MSC_Tests' name='TC_cipher_complete_13_without_cipher' time='MASKED'/>
104 <testcase classname='MSC_Tests' name='TC_lu_with_invalid_mcc_mnc' time='MASKED'/>
Harald Welte43d36b92019-02-17 21:40:59 +0100105 <testcase classname='MSC_Tests' name='TC_sgsap_reset' time='MASKED'/>
106 <testcase classname='MSC_Tests' name='TC_sgsap_lu' time='MASKED'/>
107 <testcase classname='MSC_Tests' name='TC_sgsap_lu_imsi_reject' time='MASKED'/>
108 <testcase classname='MSC_Tests' name='TC_sgsap_lu_and_nothing' time='MASKED'/>
109 <testcase classname='MSC_Tests' name='TC_sgsap_expl_imsi_det_eps' time='MASKED'/>
Philipp Maierfc19f172019-03-21 11:17:54 +0100110 <testcase classname='MSC_Tests' name='TC_sgsap_impl_imsi_det_eps' time='MASKED'/>
Harald Welte43d36b92019-02-17 21:40:59 +0100111 <testcase classname='MSC_Tests' name='TC_sgsap_expl_imsi_det_noneps' time='MASKED'/>
Philipp Maier5d812702019-03-21 10:51:26 +0100112 <testcase classname='MSC_Tests' name='TC_sgsap_impl_imsi_det_noneps' time='MASKED'/>
Harald Welte43d36b92019-02-17 21:40:59 +0100113 <testcase classname='MSC_Tests' name='TC_sgsap_paging_rej' time='MASKED'/>
114 <testcase classname='MSC_Tests' name='TC_sgsap_paging_subscr_rej' time='MASKED'/>
115 <testcase classname='MSC_Tests' name='TC_sgsap_paging_ue_unr' time='MASKED'/>
116 <testcase classname='MSC_Tests' name='TC_sgsap_paging_and_nothing' time='MASKED'/>
117 <testcase classname='MSC_Tests' name='TC_sgsap_paging_and_lu' time='MASKED'/>
118 <testcase classname='MSC_Tests' name='TC_sgsap_mt_sms' time='MASKED'/>
119 <testcase classname='MSC_Tests' name='TC_sgsap_mo_sms' time='MASKED'/>
120 <testcase classname='MSC_Tests' name='TC_sgsap_mt_sms_and_nothing' time='MASKED'/>
121 <testcase classname='MSC_Tests' name='TC_sgsap_mt_sms_and_reject' time='MASKED'/>
122 <testcase classname='MSC_Tests' name='TC_sgsap_unexp_ud' time='MASKED'/>
123 <testcase classname='MSC_Tests' name='TC_sgsap_unsol_ud' time='MASKED'/>
124 <testcase classname='MSC_Tests' name='TC_bssap_lu_sgsap_lu_and_mt_call' time='MASKED'/>
125 <testcase classname='MSC_Tests' name='TC_sgsap_lu_and_mt_call' time='MASKED'/>
Philipp Maier628c0052019-04-09 17:36:57 +0200126 <testcase classname='MSC_Tests' name='TC_sgsap_vlr_failure' time='MASKED'/>
Oliver Smithbe4c5312019-07-23 15:00:04 +0200127 <testcase classname='MSC_Tests' name='TC_ho_inter_bsc_unknown_cell' time='MASKED'/>
128 <testcase classname='MSC_Tests' name='TC_ho_inter_bsc' time='MASKED'/>
Neels Hofmeyrcb8d9892021-07-02 18:03:52 +0200129 <testcase classname='MSC_Tests' name='TC_ho_inter_bsc_a5_1' time='MASKED'/>
130 <testcase classname='MSC_Tests' name='TC_ho_inter_bsc_a5_3' time='MASKED'/>
131 <testcase classname='MSC_Tests' name='TC_ho_inter_bsc_a5_4' time='MASKED'/>
Neels Hofmeyr929b4062020-09-11 18:24:23 +0000132 <testcase classname='MSC_Tests' name='TC_ho_inter_bsc_ipv6' time='MASKED'/>
Oliver Smithbe4c5312019-07-23 15:00:04 +0200133 <testcase classname='MSC_Tests' name='TC_ho_inter_msc_out' time='MASKED'/>
Neels Hofmeyrcb8d9892021-07-02 18:03:52 +0200134 <testcase classname='MSC_Tests' name='TC_ho_inter_msc_out_a5_1' time='MASKED'/>
135 <testcase classname='MSC_Tests' name='TC_ho_inter_msc_out_a5_3' time='MASKED'/>
136 <testcase classname='MSC_Tests' name='TC_ho_inter_msc_out_a5_4' time='MASKED'/>
Neels Hofmeyr929b4062020-09-11 18:24:23 +0000137 <testcase classname='MSC_Tests' name='TC_ho_inter_msc_out_ipv6' time='MASKED'/>
Oliver Smith1d118ff2019-07-03 10:57:35 +0200138 <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_check_imei' time='MASKED'/>
139 <testcase classname='MSC_Tests' name='TC_lu_imsi_auth3g_tmsi_check_imei' time='MASKED'/>
140 <testcase classname='MSC_Tests' name='TC_lu_imsi_noauth_tmsi_check_imei' time='MASKED'/>
141 <testcase classname='MSC_Tests' name='TC_lu_imsi_noauth_notmsi_check_imei' time='MASKED'/>
Oliver Smith690d60f2019-07-23 13:09:08 +0200142 <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_check_imei_nack' time='MASKED'/>
143 <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_check_imei_err' time='MASKED'/>
Oliver Smith1d118ff2019-07-03 10:57:35 +0200144 <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_check_imei_early' time='MASKED'/>
145 <testcase classname='MSC_Tests' name='TC_lu_imsi_auth3g_tmsi_check_imei_early' time='MASKED'/>
146 <testcase classname='MSC_Tests' name='TC_lu_imsi_noauth_tmsi_check_imei_early' time='MASKED'/>
147 <testcase classname='MSC_Tests' name='TC_lu_imsi_noauth_notmsi_check_imei_early' time='MASKED'/>
148 <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_check_imei_early_nack' time='MASKED'/>
149 <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_check_imei_early_err' time='MASKED'/>
Oliver Smithbe4c5312019-07-23 15:00:04 +0200150 <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_encr_3_1_log_msc_debug' time='MASKED'/>
151 <testcase classname='MSC_Tests' name='TC_mo_cc_bssmap_clear' time='MASKED'/>
Neels Hofmeyra4d21002020-05-14 21:10:28 +0200152 <testcase classname='MSC_Tests' name='TC_invalid_mgcp_crash' time='MASKED'/>
153 <testcase classname='MSC_Tests' name='TC_mm_id_resp_no_identity' time='MASKED'/>
Vadim Yanitskiy25219062020-01-21 01:41:33 +0700154 <testcase classname='MSC_Tests' name='TC_lu_and_expire_while_paging' time='MASKED'/>
Neels Hofmeyr929b4062020-09-11 18:24:23 +0000155 <testcase classname='MSC_Tests' name='TC_paging_response_imsi_unknown' time='MASKED'/>
156 <testcase classname='MSC_Tests' name='TC_paging_response_tmsi_unknown' time='MASKED'/>
Neels Hofmeyra4d21002020-05-14 21:10:28 +0200157 <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_imsi_reject' time='MASKED'/>
158 <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_imsi_timeout_gsup' time='MASKED'/>
Oliver Smithbe4c5312019-07-23 15:00:04 +0200159 <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_imsi_auth3g_tmsi' time='MASKED'/>
Pau Espin Pedrold3d54a92019-12-17 17:02:54 +0100160 <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_imsi_timeout_tmsi_realloc' time='MASKED'>
161 <failure type='fail-verdict'>Timeout waiting for ClearCommand/Release
Neels Hofmeyra4d21002020-05-14 21:10:28 +0200162 MSC_Tests_Iu.ttcn:MASKED MSC_Tests_Iu control part
Pau Espin Pedrold3d54a92019-12-17 17:02:54 +0100163 MSC_Tests_Iu.ttcn:MASKED TC_iu_lu_imsi_timeout_tmsi_realloc testcase
164 </failure>
165 </testcase>
Oliver Smithbe4c5312019-07-23 15:00:04 +0200166 <testcase classname='MSC_Tests_Iu' name='TC_iu_cmserv_imsi_unknown' time='MASKED'>
167 <failure type='fail-verdict'>Tguard timeout
168 MSC_Tests_Iu.ttcn:MASKED MSC_Tests_Iu control part
169 MSC_Tests_Iu.ttcn:MASKED TC_iu_cmserv_imsi_unknown testcase
170 </failure>
171 </testcase>
Neels Hofmeyra4d21002020-05-14 21:10:28 +0200172 <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_and_mo_call' time='MASKED'/>
173 <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_and_mo_call_sccp_tiar_timeout' time='MASKED'/>
Oliver Smithbe4c5312019-07-23 15:00:04 +0200174 <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_auth_sai_timeout' time='MASKED'/>
175 <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_auth_sai_err' time='MASKED'/>
176 <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_release_request' time='MASKED'/>
177 <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_disconnect' time='MASKED'/>
178 <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_by_imei' time='MASKED'/>
179 <testcase classname='MSC_Tests_Iu' name='TC_iu_imsi_detach_by_imsi' time='MASKED'/>
180 <testcase classname='MSC_Tests_Iu' name='TC_iu_imsi_detach_by_tmsi' time='MASKED'/>
181 <testcase classname='MSC_Tests_Iu' name='TC_iu_imsi_detach_by_imei' time='MASKED'/>
182 <testcase classname='MSC_Tests_Iu' name='TC_iu_emerg_call_imei_reject' time='MASKED'/>
Neels Hofmeyra4d21002020-05-14 21:10:28 +0200183 <testcase classname='MSC_Tests_Iu' name='TC_iu_emerg_call_imsi' time='MASKED'/>
Oliver Smithbe4c5312019-07-23 15:00:04 +0200184 <testcase classname='MSC_Tests_Iu' name='TC_iu_establish_and_nothing' time='MASKED'/>
185 <testcase classname='MSC_Tests_Iu' name='TC_iu_mo_setup_and_nothing' time='MASKED'/>
186 <testcase classname='MSC_Tests_Iu' name='TC_iu_mo_crcx_ran_timeout' time='MASKED'/>
Neels Hofmeyra4d21002020-05-14 21:10:28 +0200187 <testcase classname='MSC_Tests_Iu' name='TC_iu_mo_crcx_ran_reject' time='MASKED'/>
Oliver Smithbe4c5312019-07-23 15:00:04 +0200188 <testcase classname='MSC_Tests_Iu' name='TC_iu_mt_crcx_ran_reject' time='MASKED'/>
Neels Hofmeyra4d21002020-05-14 21:10:28 +0200189 <testcase classname='MSC_Tests_Iu' name='TC_iu_gsup_cancel' time='MASKED'/>
Oliver Smithbe4c5312019-07-23 15:00:04 +0200190 <testcase classname='MSC_Tests_Iu' name='TC_iu_mo_release_timeout' time='MASKED'/>
191 <testcase classname='MSC_Tests' name='TC_reset_two_1iu' time='MASKED'/>
Neels Hofmeyra4d21002020-05-14 21:10:28 +0200192 <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_and_mt_call' time='MASKED'/>
193 <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_and_mt_call_already_paging' time='MASKED'/>
Oliver Smithbe4c5312019-07-23 15:00:04 +0200194 <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_and_mo_sms' time='MASKED'/>
195 <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_and_mt_sms' time='MASKED'/>
Neels Hofmeyra4d21002020-05-14 21:10:28 +0200196 <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_and_mt_sms_already_paging' time='MASKED'/>
Oliver Smithbe4c5312019-07-23 15:00:04 +0200197 <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_and_mt_sms_paging_and_nothing' time='MASKED'/>
Neels Hofmeyra4d21002020-05-14 21:10:28 +0200198 <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_and_mt_sms_paging_repeated' time='MASKED'>
199 <failure type='fail-verdict'>UTRAN: Expected a second Paging
200 MSC_Tests_Iu.ttcn:MASKED MSC_Tests_Iu control part
201 MSC_Tests_Iu.ttcn:MASKED TC_iu_lu_and_mt_sms_paging_repeated testcase
202 </failure>
203 </testcase>
Oliver Smithbe4c5312019-07-23 15:00:04 +0200204 <testcase classname='MSC_Tests_Iu' name='TC_iu_smpp_mo_sms' time='MASKED'/>
205 <testcase classname='MSC_Tests_Iu' name='TC_iu_gsup_mo_sms' time='MASKED'/>
206 <testcase classname='MSC_Tests_Iu' name='TC_iu_gsup_mo_smma' time='MASKED'/>
207 <testcase classname='MSC_Tests_Iu' name='TC_iu_gsup_mt_sms_ack' time='MASKED'/>
208 <testcase classname='MSC_Tests_Iu' name='TC_iu_gsup_mt_sms_err' time='MASKED'/>
209 <testcase classname='MSC_Tests_Iu' name='TC_iu_gsup_mt_sms_rp_mr' time='MASKED'/>
210 <testcase classname='MSC_Tests_Iu' name='TC_iu_gsup_mo_mt_sms_rp_mr' time='MASKED'/>
211 <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_and_mo_ussd_single_request' time='MASKED'/>
212 <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_and_mt_ussd_notification' time='MASKED'/>
Neels Hofmeyra4d21002020-05-14 21:10:28 +0200213 <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_and_mo_ussd_during_mt_call' time='MASKED'/>
214 <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_and_mt_ussd_during_mt_call' time='MASKED'/>
Oliver Smithbe4c5312019-07-23 15:00:04 +0200215 <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_and_mo_ussd_mo_release' time='MASKED'/>
216 <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_and_ss_session_timeout' time='MASKED'/>
Vadim Yanitskiy373b0542020-01-07 22:57:46 +0100217 <testcase classname='MSC_Tests_Iu' name='TC_iu_mt_ussd_for_unknown_subscr' time='MASKED'/>
218 <testcase classname='MSC_Tests_Iu' name='TC_iu_mo_ussd_for_unknown_trans' time='MASKED'/>
219 <testcase classname='MSC_Tests_Iu' name='TC_iu_proc_ss_for_unknown_session' time='MASKED'/>
220 <testcase classname='MSC_Tests_Iu' name='TC_iu_proc_ss_paging_fail' time='MASKED'/>
221 <testcase classname='MSC_Tests_Iu' name='TC_iu_proc_ss_abort' time='MASKED'/>
Vadim Yanitskiy1c9754d2020-01-07 21:56:55 +0100222 <testcase classname='MSC_Tests_Iu' name='TC_iu_multi_lu_and_mo_ussd' time='MASKED'/>
223 <testcase classname='MSC_Tests_Iu' name='TC_iu_multi_lu_and_mt_ussd' time='MASKED'/>
Neels Hofmeyrcb8d9892021-07-02 18:03:52 +0200224 <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_with_invalid_mcc_mnc' time='MASKED'>
225 <failure type='fail-verdict'>Tguard timeout
226 MSC_Tests_Iu.ttcn:MASKED MSC_Tests_Iu control part
227 MSC_Tests_Iu.ttcn:MASKED TC_iu_lu_with_invalid_mcc_mnc testcase
228 </failure>
229 </testcase>
Vadim Yanitskiy25219062020-01-21 01:41:33 +0700230 <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_and_expire_while_paging' time='MASKED'/>
Oliver Smithbe4c5312019-07-23 15:00:04 +0200231 <testcase classname='MSC_Tests_Iu' name='TC_mo_cc_iu_release' time='MASKED'/>
Neels Hofmeyr3cf797d2018-04-05 16:56:38 +0200232</testsuite>