commit 373b054d458180f81382e5a18ae33a446079174b
author Vadim Yanitskiy <axilirator@gmail.com> Tue Jan 07 22:57:46 2020 +0100
committer Vadim Yanitskiy <axilirator@gmail.com> Tue Jan 07 23:30:39 2020 +0100
tree 1c0d75c3f3fad151273212f1477e700d55b8c1c6
parent 2dd9661220de9d37855dece3042ca2cd5e9ec925

MSC/Iu: add missing SS/USSD test cases from MSC_Tests.ttcn

Change-Id: I99e888708ed1efeab12a4c88c734a78619a39888

msc/expected-results.xml

diff --git a/msc/expected-results.xml b/msc/expected-results.xml
index f94c781..a7b7142 100644
--- a/msc/expected-results.xml
+++ b/msc/expected-results.xml
@@ -207,6 +207,11 @@
   </testcase>
   <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_and_mo_ussd_mo_release' time='MASKED'/>
   <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_and_ss_session_timeout' time='MASKED'/>
+  <testcase classname='MSC_Tests_Iu' name='TC_iu_mt_ussd_for_unknown_subscr' time='MASKED'/>
+  <testcase classname='MSC_Tests_Iu' name='TC_iu_mo_ussd_for_unknown_trans' time='MASKED'/>
+  <testcase classname='MSC_Tests_Iu' name='TC_iu_proc_ss_for_unknown_session' time='MASKED'/>
+  <testcase classname='MSC_Tests_Iu' name='TC_iu_proc_ss_paging_fail' time='MASKED'/>
+  <testcase classname='MSC_Tests_Iu' name='TC_iu_proc_ss_abort' time='MASKED'/>
   <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_with_invalid_mcc_mnc' time='MASKED'/>
   <testcase classname='MSC_Tests_Iu' name='TC_mo_cc_iu_release' time='MASKED'/>
 </testsuite>