| Neels Hofmeyr | 3cf797d | 2018-04-05 16:56:38 +0200 | [diff] [blame] | 1 | <?xml version="1.0"?> |
| Oliver Smith | 690d60f | 2019-07-23 13:09:08 +0200 | [diff] [blame] | 2 | <testsuite name='Titan' tests='154' failures='9' errors='0' skipped='0' inconc='0' time='MASKED'> |
| Neels Hofmeyr | fc0384a | 2018-04-11 15:56:41 +0200 | [diff] [blame] | 3 | <testcase classname='MSC_Tests' name='TC_cr_before_reset' time='MASKED'/> |
| 4 | <testcase classname='MSC_Tests' name='TC_lu_imsi_noauth_tmsi' time='MASKED'/> |
| 5 | <testcase classname='MSC_Tests' name='TC_lu_imsi_noauth_notmsi' time='MASKED'/> |
| Neels Hofmeyr | 873ae20 | 2018-09-06 14:13:34 +0200 | [diff] [blame] | 6 | <testcase classname='MSC_Tests' name='TC_lu_imsi_reject' time='MASKED'/> |
| 7 | <testcase classname='MSC_Tests' name='TC_lu_imsi_timeout_gsup' time='MASKED'/> |
| Neels Hofmeyr | fc0384a | 2018-04-11 15:56:41 +0200 | [diff] [blame] | 8 | <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi' time='MASKED'/> |
| Oliver Smith | be4c531 | 2019-07-23 15:00:04 +0200 | [diff] [blame] | 9 | <testcase classname='MSC_Tests' name='TC_lu_imsi_auth3g_tmsi' time='MASKED'/> |
| Pau Espin Pedrol | d3d54a9 | 2019-12-17 17:02:54 +0100 | [diff] [blame] | 10 | <testcase classname='MSC_Tests' name='TC_lu_imsi_timeout_tmsi_realloc' time='MASKED'> |
| 11 | <failure type='fail-verdict'>Timeout waiting for ClearCommand/Release |
| 12 | MSC_Tests.ttcn:MASKED TC_lu_imsi_timeout_tmsi_realloc testcase |
| 13 | </failure> |
| 14 | </testcase> |
| Neels Hofmeyr | fc0384a | 2018-04-11 15:56:41 +0200 | [diff] [blame] | 15 | <testcase classname='MSC_Tests' name='TC_cmserv_imsi_unknown' time='MASKED'/> |
| 16 | <testcase classname='MSC_Tests' name='TC_lu_and_mo_call' time='MASKED'/> |
| Pau Espin Pedrol | a42745c | 2020-01-10 18:03:28 +0100 | [diff] [blame^] | 17 | <testcase classname='MSC_Tests' name='TC_lu_and_mo_call_sccp_tiar_timeout' time='MASKED'/> |
| Neels Hofmeyr | fc0384a | 2018-04-11 15:56:41 +0200 | [diff] [blame] | 18 | <testcase classname='MSC_Tests' name='TC_lu_auth_sai_timeout' time='MASKED'/> |
| 19 | <testcase classname='MSC_Tests' name='TC_lu_auth_sai_err' time='MASKED'/> |
| Neels Hofmeyr | de17222 | 2018-05-02 11:59:18 +0200 | [diff] [blame] | 20 | <testcase classname='MSC_Tests' name='TC_lu_clear_request' time='MASKED'/> |
| Neels Hofmeyr | fc0384a | 2018-04-11 15:56:41 +0200 | [diff] [blame] | 21 | <testcase classname='MSC_Tests' name='TC_lu_disconnect' time='MASKED'/> |
| 22 | <testcase classname='MSC_Tests' name='TC_lu_by_imei' time='MASKED'/> |
| 23 | <testcase classname='MSC_Tests' name='TC_lu_by_tmsi_noauth_unknown' time='MASKED'/> |
| 24 | <testcase classname='MSC_Tests' name='TC_imsi_detach_by_imsi' time='MASKED'/> |
| 25 | <testcase classname='MSC_Tests' name='TC_imsi_detach_by_tmsi' time='MASKED'/> |
| 26 | <testcase classname='MSC_Tests' name='TC_imsi_detach_by_imei' time='MASKED'/> |
| Neels Hofmeyr | de17222 | 2018-05-02 11:59:18 +0200 | [diff] [blame] | 27 | <testcase classname='MSC_Tests' name='TC_emerg_call_imei_reject' time='MASKED'/> |
| Neels Hofmeyr | fc0384a | 2018-04-11 15:56:41 +0200 | [diff] [blame] | 28 | <testcase classname='MSC_Tests' name='TC_emerg_call_imsi' time='MASKED'/> |
| Neels Hofmeyr | de17222 | 2018-05-02 11:59:18 +0200 | [diff] [blame] | 29 | <testcase classname='MSC_Tests' name='TC_cm_serv_req_vgcs_reject' time='MASKED'/> |
| 30 | <testcase classname='MSC_Tests' name='TC_cm_serv_req_vbs_reject' time='MASKED'/> |
| 31 | <testcase classname='MSC_Tests' name='TC_cm_serv_req_lcs_reject' time='MASKED'/> |
| 32 | <testcase classname='MSC_Tests' name='TC_cm_reest_req_reject' time='MASKED'/> |
| Neels Hofmeyr | fc0384a | 2018-04-11 15:56:41 +0200 | [diff] [blame] | 33 | <testcase classname='MSC_Tests' name='TC_lu_auth_2G_fail' time='MASKED'/> |
| 34 | <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_encr_13_13' time='MASKED'/> |
| 35 | <testcase classname='MSC_Tests' name='TC_cl3_no_payload' time='MASKED'/> |
| Neels Hofmeyr | de17222 | 2018-05-02 11:59:18 +0200 | [diff] [blame] | 36 | <testcase classname='MSC_Tests' name='TC_cl3_rnd_payload' time='MASKED'/> |
| Stefan Sperling | f46eb26 | 2018-06-01 17:30:45 +0200 | [diff] [blame] | 37 | <testcase classname='MSC_Tests' name='TC_establish_and_nothing' time='MASKED'/> |
| Neels Hofmeyr | 2caf349 | 2019-01-23 12:44:09 +0100 | [diff] [blame] | 38 | <testcase classname='MSC_Tests' name='TC_mo_setup_and_nothing' time='MASKED'/> |
| Neels Hofmeyr | fc0384a | 2018-04-11 15:56:41 +0200 | [diff] [blame] | 39 | <testcase classname='MSC_Tests' name='TC_mo_crcx_ran_timeout' time='MASKED'/> |
| 40 | <testcase classname='MSC_Tests' name='TC_mo_crcx_ran_reject' time='MASKED'/> |
| Oliver Smith | be4c531 | 2019-07-23 15:00:04 +0200 | [diff] [blame] | 41 | <testcase classname='MSC_Tests' name='TC_mt_crcx_ran_reject' time='MASKED'/> |
| Neels Hofmeyr | fc0384a | 2018-04-11 15:56:41 +0200 | [diff] [blame] | 42 | <testcase classname='MSC_Tests' name='TC_mo_setup_and_dtmf_dup' time='MASKED'/> |
| Neels Hofmeyr | 2caf349 | 2019-01-23 12:44:09 +0100 | [diff] [blame] | 43 | <testcase classname='MSC_Tests' name='TC_gsup_cancel' time='MASKED'/> |
| Neels Hofmeyr | fc0384a | 2018-04-11 15:56:41 +0200 | [diff] [blame] | 44 | <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_encr_1_13' time='MASKED'/> |
| 45 | <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_encr_3_13' time='MASKED'/> |
| 46 | <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_encr_3_1' time='MASKED'/> |
| 47 | <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_encr_3_1_no_cm' time='MASKED'/> |
| 48 | <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_encr_13_2' time='MASKED'/> |
| 49 | <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_encr_013_2' time='MASKED'/> |
| 50 | <testcase classname='MSC_Tests' name='TC_mo_release_timeout' time='MASKED'/> |
| 51 | <testcase classname='MSC_Tests' name='TC_lu_and_mt_call_no_dlcx_resp' time='MASKED'/> |
| 52 | <testcase classname='MSC_Tests' name='TC_reset_two' time='MASKED'/> |
| 53 | <testcase classname='MSC_Tests' name='TC_lu_and_mt_call' time='MASKED'/> |
| Neels Hofmeyr | 98d428d | 2018-04-11 15:54:07 +0200 | [diff] [blame] | 54 | <testcase classname='MSC_Tests' name='TC_lu_and_mo_sms' time='MASKED'/> |
| Neels Hofmeyr | de17222 | 2018-05-02 11:59:18 +0200 | [diff] [blame] | 55 | <testcase classname='MSC_Tests' name='TC_lu_and_mt_sms' time='MASKED'/> |
| Philipp Maier | 3983e70 | 2018-11-22 19:01:33 +0100 | [diff] [blame] | 56 | <testcase classname='MSC_Tests' name='TC_lu_and_mt_sms_paging_and_nothing' time='MASKED'/> |
| Neels Hofmeyr | de17222 | 2018-05-02 11:59:18 +0200 | [diff] [blame] | 57 | <testcase classname='MSC_Tests' name='TC_smpp_mo_sms' time='MASKED'/> |
| 58 | <testcase classname='MSC_Tests' name='TC_smpp_mt_sms' time='MASKED'/> |
| Vadim Yanitskiy | 103d09f | 2018-11-12 02:50:23 +0700 | [diff] [blame] | 59 | <testcase classname='MSC_Tests' name='TC_gsup_mo_sms' time='MASKED'/> |
| Vadim Yanitskiy | 9cc019a | 2018-11-15 02:06:07 +0700 | [diff] [blame] | 60 | <testcase classname='MSC_Tests' name='TC_gsup_mo_smma' time='MASKED'/> |
| Vadim Yanitskiy | d7b37ab | 2018-11-24 03:40:20 +0700 | [diff] [blame] | 61 | <testcase classname='MSC_Tests' name='TC_gsup_mt_sms_ack' time='MASKED'/> |
| 62 | <testcase classname='MSC_Tests' name='TC_gsup_mt_sms_err' time='MASKED'/> |
| Vadim Yanitskiy | be1ff4b | 2019-01-18 15:04:13 +0700 | [diff] [blame] | 63 | <testcase classname='MSC_Tests' name='TC_gsup_mt_sms_rp_mr' time='MASKED'/> |
| Vadim Yanitskiy | 5ac49cc | 2019-01-24 16:57:31 +0700 | [diff] [blame] | 64 | <testcase classname='MSC_Tests' name='TC_gsup_mo_mt_sms_rp_mr' time='MASKED'/> |
| Oliver Smith | be4c531 | 2019-07-23 15:00:04 +0200 | [diff] [blame] | 65 | <testcase classname='MSC_Tests' name='TC_gsup_mt_multi_part_sms' time='MASKED'/> |
| Vadim Yanitskiy | 2a978b9 | 2018-06-19 17:51:20 +0700 | [diff] [blame] | 66 | <testcase classname='MSC_Tests' name='TC_lu_and_mo_ussd_single_request' time='MASKED'/> |
| Vadim Yanitskiy | 13e4a27 | 2018-06-19 18:24:31 +0700 | [diff] [blame] | 67 | <testcase classname='MSC_Tests' name='TC_lu_and_mt_ussd_notification' time='MASKED'/> |
| Vadim Yanitskiy | 2a978b9 | 2018-06-19 17:51:20 +0700 | [diff] [blame] | 68 | <testcase classname='MSC_Tests' name='TC_lu_and_mo_ussd_during_mt_call' time='MASKED'/> |
| Vadim Yanitskiy | 13e4a27 | 2018-06-19 18:24:31 +0700 | [diff] [blame] | 69 | <testcase classname='MSC_Tests' name='TC_lu_and_mt_ussd_during_mt_call' time='MASKED'/> |
| Vadim Yanitskiy | 2daf52d | 2018-06-21 04:19:58 +0700 | [diff] [blame] | 70 | <testcase classname='MSC_Tests' name='TC_lu_and_mo_ussd_mo_release' time='MASKED'/> |
| Vadim Yanitskiy | 78329c7 | 2019-06-17 23:20:00 +0700 | [diff] [blame] | 71 | <testcase classname='MSC_Tests' name='TC_lu_and_ss_session_timeout' time='MASKED'/> |
| 72 | <testcase classname='MSC_Tests' name='TC_mt_ussd_for_unknown_subscr' time='MASKED'/> |
| 73 | <testcase classname='MSC_Tests' name='TC_mo_ussd_for_unknown_trans' time='MASKED'/> |
| 74 | <testcase classname='MSC_Tests' name='TC_proc_ss_for_unknown_session' time='MASKED'/> |
| 75 | <testcase classname='MSC_Tests' name='TC_proc_ss_paging_fail' time='MASKED'/> |
| 76 | <testcase classname='MSC_Tests' name='TC_proc_ss_abort' time='MASKED'/> |
| Vadim Yanitskiy | 1c9754d | 2020-01-07 21:56:55 +0100 | [diff] [blame] | 77 | <testcase classname='MSC_Tests' name='TC_multi_lu_and_mo_ussd' time='MASKED'/> |
| 78 | <testcase classname='MSC_Tests' name='TC_multi_lu_and_mt_ussd' time='MASKED'/> |
| Stefan Sperling | 89eb1f3 | 2018-12-17 15:06:20 +0100 | [diff] [blame] | 79 | <testcase classname='MSC_Tests' name='TC_cipher_complete_with_invalid_cipher' time='MASKED'/> |
| Oliver Smith | be4c531 | 2019-07-23 15:00:04 +0200 | [diff] [blame] | 80 | <testcase classname='MSC_Tests' name='TC_cipher_complete_1_without_cipher' time='MASKED'/> |
| 81 | <testcase classname='MSC_Tests' name='TC_cipher_complete_3_without_cipher' time='MASKED'/> |
| 82 | <testcase classname='MSC_Tests' name='TC_cipher_complete_13_without_cipher' time='MASKED'/> |
| 83 | <testcase classname='MSC_Tests' name='TC_lu_with_invalid_mcc_mnc' time='MASKED'/> |
| Harald Welte | 43d36b9 | 2019-02-17 21:40:59 +0100 | [diff] [blame] | 84 | <testcase classname='MSC_Tests' name='TC_sgsap_reset' time='MASKED'/> |
| 85 | <testcase classname='MSC_Tests' name='TC_sgsap_lu' time='MASKED'/> |
| 86 | <testcase classname='MSC_Tests' name='TC_sgsap_lu_imsi_reject' time='MASKED'/> |
| 87 | <testcase classname='MSC_Tests' name='TC_sgsap_lu_and_nothing' time='MASKED'/> |
| 88 | <testcase classname='MSC_Tests' name='TC_sgsap_expl_imsi_det_eps' time='MASKED'/> |
| Philipp Maier | fc19f17 | 2019-03-21 11:17:54 +0100 | [diff] [blame] | 89 | <testcase classname='MSC_Tests' name='TC_sgsap_impl_imsi_det_eps' time='MASKED'/> |
| Harald Welte | 43d36b9 | 2019-02-17 21:40:59 +0100 | [diff] [blame] | 90 | <testcase classname='MSC_Tests' name='TC_sgsap_expl_imsi_det_noneps' time='MASKED'/> |
| Philipp Maier | 5d81270 | 2019-03-21 10:51:26 +0100 | [diff] [blame] | 91 | <testcase classname='MSC_Tests' name='TC_sgsap_impl_imsi_det_noneps' time='MASKED'/> |
| Harald Welte | 43d36b9 | 2019-02-17 21:40:59 +0100 | [diff] [blame] | 92 | <testcase classname='MSC_Tests' name='TC_sgsap_paging_rej' time='MASKED'/> |
| 93 | <testcase classname='MSC_Tests' name='TC_sgsap_paging_subscr_rej' time='MASKED'/> |
| 94 | <testcase classname='MSC_Tests' name='TC_sgsap_paging_ue_unr' time='MASKED'/> |
| 95 | <testcase classname='MSC_Tests' name='TC_sgsap_paging_and_nothing' time='MASKED'/> |
| 96 | <testcase classname='MSC_Tests' name='TC_sgsap_paging_and_lu' time='MASKED'/> |
| 97 | <testcase classname='MSC_Tests' name='TC_sgsap_mt_sms' time='MASKED'/> |
| 98 | <testcase classname='MSC_Tests' name='TC_sgsap_mo_sms' time='MASKED'/> |
| 99 | <testcase classname='MSC_Tests' name='TC_sgsap_mt_sms_and_nothing' time='MASKED'/> |
| 100 | <testcase classname='MSC_Tests' name='TC_sgsap_mt_sms_and_reject' time='MASKED'/> |
| 101 | <testcase classname='MSC_Tests' name='TC_sgsap_unexp_ud' time='MASKED'/> |
| 102 | <testcase classname='MSC_Tests' name='TC_sgsap_unsol_ud' time='MASKED'/> |
| 103 | <testcase classname='MSC_Tests' name='TC_bssap_lu_sgsap_lu_and_mt_call' time='MASKED'/> |
| 104 | <testcase classname='MSC_Tests' name='TC_sgsap_lu_and_mt_call' time='MASKED'/> |
| Philipp Maier | 628c005 | 2019-04-09 17:36:57 +0200 | [diff] [blame] | 105 | <testcase classname='MSC_Tests' name='TC_sgsap_vlr_failure' time='MASKED'/> |
| Oliver Smith | be4c531 | 2019-07-23 15:00:04 +0200 | [diff] [blame] | 106 | <testcase classname='MSC_Tests' name='TC_ho_inter_bsc_unknown_cell' time='MASKED'/> |
| 107 | <testcase classname='MSC_Tests' name='TC_ho_inter_bsc' time='MASKED'/> |
| 108 | <testcase classname='MSC_Tests' name='TC_ho_inter_msc_out' time='MASKED'/> |
| Oliver Smith | 1d118ff | 2019-07-03 10:57:35 +0200 | [diff] [blame] | 109 | <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_check_imei' time='MASKED'/> |
| 110 | <testcase classname='MSC_Tests' name='TC_lu_imsi_auth3g_tmsi_check_imei' time='MASKED'/> |
| 111 | <testcase classname='MSC_Tests' name='TC_lu_imsi_noauth_tmsi_check_imei' time='MASKED'/> |
| 112 | <testcase classname='MSC_Tests' name='TC_lu_imsi_noauth_notmsi_check_imei' time='MASKED'/> |
| Oliver Smith | 690d60f | 2019-07-23 13:09:08 +0200 | [diff] [blame] | 113 | <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_check_imei_nack' time='MASKED'/> |
| 114 | <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_check_imei_err' time='MASKED'/> |
| Oliver Smith | 1d118ff | 2019-07-03 10:57:35 +0200 | [diff] [blame] | 115 | <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_check_imei_early' time='MASKED'/> |
| 116 | <testcase classname='MSC_Tests' name='TC_lu_imsi_auth3g_tmsi_check_imei_early' time='MASKED'/> |
| 117 | <testcase classname='MSC_Tests' name='TC_lu_imsi_noauth_tmsi_check_imei_early' time='MASKED'/> |
| 118 | <testcase classname='MSC_Tests' name='TC_lu_imsi_noauth_notmsi_check_imei_early' time='MASKED'/> |
| 119 | <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_check_imei_early_nack' time='MASKED'/> |
| 120 | <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_check_imei_early_err' time='MASKED'/> |
| Oliver Smith | be4c531 | 2019-07-23 15:00:04 +0200 | [diff] [blame] | 121 | <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_encr_3_1_log_msc_debug' time='MASKED'/> |
| 122 | <testcase classname='MSC_Tests' name='TC_mo_cc_bssmap_clear' time='MASKED'/> |
| 123 | <testcase classname='MSC_Tests' name='TC_lu_and_mt_call_osmux' time='MASKED'/> |
| 124 | <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_imsi_reject' time='MASKED'> |
| 125 | <failure type='fail-verdict'>Tguard timeout |
| 126 | MSC_Tests_Iu.ttcn:MASKED MSC_Tests_Iu control part |
| 127 | MSC_Tests_Iu.ttcn:MASKED TC_iu_lu_imsi_reject testcase |
| 128 | </failure> |
| 129 | </testcase> |
| 130 | <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_imsi_timeout_gsup' time='MASKED'> |
| 131 | <failure type='fail-verdict'>Tguard timeout |
| 132 | MSC_Tests_Iu.ttcn:MASKED MSC_Tests_Iu control part |
| 133 | MSC_Tests_Iu.ttcn:MASKED TC_iu_lu_imsi_timeout_gsup testcase |
| 134 | </failure> |
| 135 | </testcase> |
| 136 | <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_imsi_auth3g_tmsi' time='MASKED'/> |
| Pau Espin Pedrol | d3d54a9 | 2019-12-17 17:02:54 +0100 | [diff] [blame] | 137 | <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_imsi_timeout_tmsi_realloc' time='MASKED'> |
| 138 | <failure type='fail-verdict'>Timeout waiting for ClearCommand/Release |
| 139 | MSC_Tests_Iu.ttcn:MASKED TC_iu_lu_imsi_timeout_tmsi_realloc testcase |
| 140 | </failure> |
| 141 | </testcase> |
| Oliver Smith | be4c531 | 2019-07-23 15:00:04 +0200 | [diff] [blame] | 142 | <testcase classname='MSC_Tests_Iu' name='TC_iu_cmserv_imsi_unknown' time='MASKED'> |
| 143 | <failure type='fail-verdict'>Tguard timeout |
| 144 | MSC_Tests_Iu.ttcn:MASKED MSC_Tests_Iu control part |
| 145 | MSC_Tests_Iu.ttcn:MASKED TC_iu_cmserv_imsi_unknown testcase |
| 146 | </failure> |
| 147 | </testcase> |
| 148 | <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_and_mo_call' time='MASKED'> |
| 149 | <failure type='fail-verdict'>Tguard timeout |
| 150 | MSC_Tests_Iu.ttcn:MASKED MSC_Tests_Iu control part |
| 151 | MSC_Tests_Iu.ttcn:MASKED TC_iu_lu_and_mo_call testcase |
| 152 | </failure> |
| 153 | </testcase> |
| 154 | <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_auth_sai_timeout' time='MASKED'/> |
| 155 | <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_auth_sai_err' time='MASKED'/> |
| 156 | <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_release_request' time='MASKED'/> |
| 157 | <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_disconnect' time='MASKED'/> |
| 158 | <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_by_imei' time='MASKED'/> |
| 159 | <testcase classname='MSC_Tests_Iu' name='TC_iu_imsi_detach_by_imsi' time='MASKED'/> |
| 160 | <testcase classname='MSC_Tests_Iu' name='TC_iu_imsi_detach_by_tmsi' time='MASKED'/> |
| 161 | <testcase classname='MSC_Tests_Iu' name='TC_iu_imsi_detach_by_imei' time='MASKED'/> |
| 162 | <testcase classname='MSC_Tests_Iu' name='TC_iu_emerg_call_imei_reject' time='MASKED'/> |
| 163 | <testcase classname='MSC_Tests_Iu' name='TC_iu_emerg_call_imsi' time='MASKED'> |
| 164 | <failure type='fail-verdict'>Tguard timeout |
| 165 | MSC_Tests_Iu.ttcn:MASKED MSC_Tests_Iu control part |
| 166 | MSC_Tests_Iu.ttcn:MASKED TC_iu_emerg_call_imsi testcase |
| 167 | </failure> |
| 168 | </testcase> |
| 169 | <testcase classname='MSC_Tests_Iu' name='TC_iu_establish_and_nothing' time='MASKED'/> |
| 170 | <testcase classname='MSC_Tests_Iu' name='TC_iu_mo_setup_and_nothing' time='MASKED'/> |
| 171 | <testcase classname='MSC_Tests_Iu' name='TC_iu_mo_crcx_ran_timeout' time='MASKED'/> |
| 172 | <testcase classname='MSC_Tests_Iu' name='TC_iu_mo_crcx_ran_reject' time='MASKED'> |
| 173 | <failure type='fail-verdict'>Timeout waiting for channel release |
| 174 | MSC_Tests_Iu.ttcn:MASKED MSC_Tests_Iu control part |
| 175 | MSC_Tests_Iu.ttcn:MASKED TC_iu_mo_crcx_ran_reject testcase |
| 176 | </failure> |
| 177 | </testcase> |
| 178 | <testcase classname='MSC_Tests_Iu' name='TC_iu_mt_crcx_ran_reject' time='MASKED'/> |
| 179 | <testcase classname='MSC_Tests_Iu' name='TC_iu_gsup_cancel' time='MASKED'> |
| 180 | <failure type='fail-verdict'>Tguard timeout |
| 181 | MSC_Tests_Iu.ttcn:MASKED MSC_Tests_Iu control part |
| 182 | MSC_Tests_Iu.ttcn:MASKED TC_iu_gsup_cancel testcase |
| 183 | </failure> |
| 184 | </testcase> |
| 185 | <testcase classname='MSC_Tests_Iu' name='TC_iu_mo_release_timeout' time='MASKED'/> |
| 186 | <testcase classname='MSC_Tests' name='TC_reset_two_1iu' time='MASKED'/> |
| 187 | <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_and_mo_sms' time='MASKED'/> |
| 188 | <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_and_mt_sms' time='MASKED'/> |
| 189 | <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_and_mt_sms_paging_and_nothing' time='MASKED'/> |
| 190 | <testcase classname='MSC_Tests_Iu' name='TC_iu_smpp_mo_sms' time='MASKED'/> |
| 191 | <testcase classname='MSC_Tests_Iu' name='TC_iu_gsup_mo_sms' time='MASKED'/> |
| 192 | <testcase classname='MSC_Tests_Iu' name='TC_iu_gsup_mo_smma' time='MASKED'/> |
| 193 | <testcase classname='MSC_Tests_Iu' name='TC_iu_gsup_mt_sms_ack' time='MASKED'/> |
| 194 | <testcase classname='MSC_Tests_Iu' name='TC_iu_gsup_mt_sms_err' time='MASKED'/> |
| 195 | <testcase classname='MSC_Tests_Iu' name='TC_iu_gsup_mt_sms_rp_mr' time='MASKED'/> |
| 196 | <testcase classname='MSC_Tests_Iu' name='TC_iu_gsup_mo_mt_sms_rp_mr' time='MASKED'/> |
| 197 | <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_and_mo_ussd_single_request' time='MASKED'/> |
| 198 | <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_and_mt_ussd_notification' time='MASKED'/> |
| 199 | <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_and_mo_ussd_during_mt_call' time='MASKED'> |
| 200 | <failure type='fail-verdict'>Tguard timeout |
| 201 | MSC_Tests_Iu.ttcn:MASKED MSC_Tests_Iu control part |
| 202 | MSC_Tests_Iu.ttcn:MASKED TC_iu_lu_and_mo_ussd_during_mt_call testcase |
| 203 | </failure> |
| 204 | </testcase> |
| 205 | <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_and_mt_ussd_during_mt_call' time='MASKED'> |
| 206 | <failure type='fail-verdict'>Tguard timeout |
| 207 | MSC_Tests_Iu.ttcn:MASKED MSC_Tests_Iu control part |
| 208 | MSC_Tests_Iu.ttcn:MASKED TC_iu_lu_and_mt_ussd_during_mt_call testcase |
| 209 | </failure> |
| 210 | </testcase> |
| 211 | <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_and_mo_ussd_mo_release' time='MASKED'/> |
| 212 | <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_and_ss_session_timeout' time='MASKED'/> |
| Vadim Yanitskiy | 373b054 | 2020-01-07 22:57:46 +0100 | [diff] [blame] | 213 | <testcase classname='MSC_Tests_Iu' name='TC_iu_mt_ussd_for_unknown_subscr' time='MASKED'/> |
| 214 | <testcase classname='MSC_Tests_Iu' name='TC_iu_mo_ussd_for_unknown_trans' time='MASKED'/> |
| 215 | <testcase classname='MSC_Tests_Iu' name='TC_iu_proc_ss_for_unknown_session' time='MASKED'/> |
| 216 | <testcase classname='MSC_Tests_Iu' name='TC_iu_proc_ss_paging_fail' time='MASKED'/> |
| 217 | <testcase classname='MSC_Tests_Iu' name='TC_iu_proc_ss_abort' time='MASKED'/> |
| Vadim Yanitskiy | 1c9754d | 2020-01-07 21:56:55 +0100 | [diff] [blame] | 218 | <testcase classname='MSC_Tests_Iu' name='TC_iu_multi_lu_and_mo_ussd' time='MASKED'/> |
| 219 | <testcase classname='MSC_Tests_Iu' name='TC_iu_multi_lu_and_mt_ussd' time='MASKED'/> |
| Oliver Smith | be4c531 | 2019-07-23 15:00:04 +0200 | [diff] [blame] | 220 | <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_with_invalid_mcc_mnc' time='MASKED'/> |
| 221 | <testcase classname='MSC_Tests_Iu' name='TC_mo_cc_iu_release' time='MASKED'/> |
| Neels Hofmeyr | 3cf797d | 2018-04-05 16:56:38 +0200 | [diff] [blame] | 222 | </testsuite> |