commit d3d54a91fab60b2299087a092a3935ed7de73616
author Pau Espin Pedrol <pespin@sysmocom.de> Tue Dec 17 17:02:54 2019 +0100
committer laforge <laforge@osmocom.org> Wed Jan 01 16:12:20 2020 +0000
tree d9b248ea3d21691e66b2ea0cbc6223bfed822d00
parent 461ed61e4d8c3b1b9e21c62d27b7050307d9555d

msc: Introduce test TC_lu_imsi_timeout_tmsi_realloc

Related: OS#4336, OS#4337
Change-Id: I603b2b2b1ae7edd6360ea38c6bbbfedc46e9fa5d

msc/expected-results.xml

diff --git a/msc/expected-results.xml b/msc/expected-results.xml
index 96af4a4..f94c781 100644
--- a/msc/expected-results.xml
+++ b/msc/expected-results.xml
@@ -7,6 +7,11 @@
   <testcase classname='MSC_Tests' name='TC_lu_imsi_timeout_gsup' time='MASKED'/>
   <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi' time='MASKED'/>
   <testcase classname='MSC_Tests' name='TC_lu_imsi_auth3g_tmsi' time='MASKED'/>
+  <testcase classname='MSC_Tests' name='TC_lu_imsi_timeout_tmsi_realloc' time='MASKED'>
+    <failure type='fail-verdict'>Timeout waiting for ClearCommand/Release
+      MSC_Tests.ttcn:MASKED TC_lu_imsi_timeout_tmsi_realloc testcase
+    </failure>
+  </testcase>
   <testcase classname='MSC_Tests' name='TC_cmserv_imsi_unknown' time='MASKED'/>
   <testcase classname='MSC_Tests' name='TC_lu_and_mo_call' time='MASKED'/>
   <testcase classname='MSC_Tests' name='TC_lu_auth_sai_timeout' time='MASKED'/>
@@ -126,6 +131,11 @@
     </failure>
   </testcase>
   <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_imsi_auth3g_tmsi' time='MASKED'/>
+  <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_imsi_timeout_tmsi_realloc' time='MASKED'>
+    <failure type='fail-verdict'>Timeout waiting for ClearCommand/Release
+      MSC_Tests_Iu.ttcn:MASKED TC_iu_lu_imsi_timeout_tmsi_realloc testcase
+    </failure>
+  </testcase>
   <testcase classname='MSC_Tests_Iu' name='TC_iu_cmserv_imsi_unknown' time='MASKED'>
     <failure type='fail-verdict'>Tguard timeout
       MSC_Tests_Iu.ttcn:MASKED MSC_Tests_Iu control part