diff --git a/msc/expected-results.xml b/msc/expected-results.xml
index 96af4a4..f94c781 100644
--- a/msc/expected-results.xml
+++ b/msc/expected-results.xml
@@ -7,6 +7,11 @@
   <testcase classname='MSC_Tests' name='TC_lu_imsi_timeout_gsup' time='MASKED'/>
   <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi' time='MASKED'/>
   <testcase classname='MSC_Tests' name='TC_lu_imsi_auth3g_tmsi' time='MASKED'/>
+  <testcase classname='MSC_Tests' name='TC_lu_imsi_timeout_tmsi_realloc' time='MASKED'>
+    <failure type='fail-verdict'>Timeout waiting for ClearCommand/Release
+      MSC_Tests.ttcn:MASKED TC_lu_imsi_timeout_tmsi_realloc testcase
+    </failure>
+  </testcase>
   <testcase classname='MSC_Tests' name='TC_cmserv_imsi_unknown' time='MASKED'/>
   <testcase classname='MSC_Tests' name='TC_lu_and_mo_call' time='MASKED'/>
   <testcase classname='MSC_Tests' name='TC_lu_auth_sai_timeout' time='MASKED'/>
@@ -126,6 +131,11 @@
     </failure>
   </testcase>
   <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_imsi_auth3g_tmsi' time='MASKED'/>
+  <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_imsi_timeout_tmsi_realloc' time='MASKED'>
+    <failure type='fail-verdict'>Timeout waiting for ClearCommand/Release
+      MSC_Tests_Iu.ttcn:MASKED TC_iu_lu_imsi_timeout_tmsi_realloc testcase
+    </failure>
+  </testcase>
   <testcase classname='MSC_Tests_Iu' name='TC_iu_cmserv_imsi_unknown' time='MASKED'>
     <failure type='fail-verdict'>Tguard timeout
       MSC_Tests_Iu.ttcn:MASKED MSC_Tests_Iu control part