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gerrit.osmocom.org / osmo-ttcn3-hacks / 98d428da11ee271b47d9178c8ca45e82dac0c0d9 / . / msc / expected-results.xml
blob: 48ab12d94a279b93b278f0e7102e8506b7cb27d3 [file] [log] [blame]
Neels Hofmeyr3cf797d2018-04-05 16:56:38 +0200[diff] [blame]1<?xml version="1.0"?>
Neels Hofmeyr98d428d2018-04-11 15:54:07 +0200[diff] [blame^]2<testsuite name='Titan' tests='47' failures='13' errors='1' skipped='0' inconc='0' time='MASKED'>
Neels Hofmeyrfc0384a2018-04-11 15:56:41 +0200[diff] [blame]3 <testcase classname='MSC_Tests' name='TC_cr_before_reset' time='MASKED'/>
4 <testcase classname='MSC_Tests' name='TC_lu_imsi_noauth_tmsi' time='MASKED'/>
5 <testcase classname='MSC_Tests' name='TC_lu_imsi_noauth_notmsi' time='MASKED'/>
6 <testcase classname='MSC_Tests' name='TC_lu_imsi_reject' time='MASKED'>
Neels Hofmeyr3cf797d2018-04-05 16:56:38 +0200[diff] [blame]7 <failure type='fail-verdict'>Timeout waiting for ClearCommand/Release
Neels Hofmeyrfc0384a2018-04-11 15:56:41 +0200[diff] [blame]8 MSC_Tests.ttcn:MASKED MSC_Tests control part
9 MSC_Tests.ttcn:MASKED TC_lu_imsi_reject testcase
Neels Hofmeyr3cf797d2018-04-05 16:56:38 +0200[diff] [blame]10 </failure>
11 </testcase>
Neels Hofmeyrfc0384a2018-04-11 15:56:41 +0200[diff] [blame]12 <testcase classname='MSC_Tests' name='TC_lu_imsi_timeout_gsup' time='MASKED'>
Neels Hofmeyr3cf797d2018-04-05 16:56:38 +0200[diff] [blame]13 <failure type='fail-verdict'>Timeout waiting for ClearCommand/Release
Neels Hofmeyrfc0384a2018-04-11 15:56:41 +0200[diff] [blame]14 MSC_Tests.ttcn:MASKED MSC_Tests control part
15 MSC_Tests.ttcn:MASKED TC_lu_imsi_timeout_gsup testcase
Neels Hofmeyr3cf797d2018-04-05 16:56:38 +0200[diff] [blame]16 </failure>
17 </testcase>
Neels Hofmeyrfc0384a2018-04-11 15:56:41 +0200[diff] [blame]18 <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi' time='MASKED'/>
19 <testcase classname='MSC_Tests' name='TC_cmserv_imsi_unknown' time='MASKED'/>
20 <testcase classname='MSC_Tests' name='TC_lu_and_mo_call' time='MASKED'/>
21 <testcase classname='MSC_Tests' name='TC_lu_auth_sai_timeout' time='MASKED'/>
22 <testcase classname='MSC_Tests' name='TC_lu_auth_sai_err' time='MASKED'/>
23 <testcase classname='MSC_Tests' name='TC_lu_clear_request' time='MASKED'>
Neels Hofmeyr2b326fa2018-04-06 00:59:36 +0200[diff] [blame]24 <failure type='fail-verdict'>Got a second Clear Command, only one expected
Neels Hofmeyrfc0384a2018-04-11 15:56:41 +0200[diff] [blame]25 MSC_Tests.ttcn:MASKED MSC_Tests control part
26 MSC_Tests.ttcn:MASKED TC_lu_clear_request testcase
Neels Hofmeyr2b326fa2018-04-06 00:59:36 +0200[diff] [blame]27 </failure>
28 </testcase>
Neels Hofmeyrfc0384a2018-04-11 15:56:41 +0200[diff] [blame]29 <testcase classname='MSC_Tests' name='TC_lu_disconnect' time='MASKED'/>
30 <testcase classname='MSC_Tests' name='TC_lu_by_imei' time='MASKED'/>
31 <testcase classname='MSC_Tests' name='TC_lu_by_tmsi_noauth_unknown' time='MASKED'/>
32 <testcase classname='MSC_Tests' name='TC_imsi_detach_by_imsi' time='MASKED'/>
33 <testcase classname='MSC_Tests' name='TC_imsi_detach_by_tmsi' time='MASKED'/>
34 <testcase classname='MSC_Tests' name='TC_imsi_detach_by_imei' time='MASKED'/>
35 <testcase classname='MSC_Tests' name='TC_emerg_call_imei_reject' time='MASKED'>
Neels Hofmeyr3cf797d2018-04-05 16:56:38 +0200[diff] [blame]36 <failure type='fail-verdict'>Timeout waiting for ClearCommand/Release
Neels Hofmeyrfc0384a2018-04-11 15:56:41 +0200[diff] [blame]37 MSC_Tests.ttcn:MASKED MSC_Tests control part
38 MSC_Tests.ttcn:MASKED TC_emerg_call_imei_reject testcase
Neels Hofmeyr3cf797d2018-04-05 16:56:38 +0200[diff] [blame]39 </failure>
40 </testcase>
Neels Hofmeyrfc0384a2018-04-11 15:56:41 +0200[diff] [blame]41 <testcase classname='MSC_Tests' name='TC_emerg_call_imsi' time='MASKED'/>
42 <testcase classname='MSC_Tests' name='TC_cm_serv_req_vgcs_reject' time='MASKED'>
Neels Hofmeyr3cf797d2018-04-05 16:56:38 +0200[diff] [blame]43 <failure type='fail-verdict'>Timeout waiting for ClearCommand/Release
Neels Hofmeyrfc0384a2018-04-11 15:56:41 +0200[diff] [blame]44 MSC_Tests.ttcn:MASKED MSC_Tests control part
45 MSC_Tests.ttcn:MASKED TC_cm_serv_req_vgcs_reject testcase
Neels Hofmeyr3cf797d2018-04-05 16:56:38 +0200[diff] [blame]46 </failure>
47 </testcase>
Neels Hofmeyrfc0384a2018-04-11 15:56:41 +0200[diff] [blame]48 <testcase classname='MSC_Tests' name='TC_cm_serv_req_vbs_reject' time='MASKED'>
Philipp Maierc6e06f72018-04-11 18:12:23 +0200[diff] [blame]49 <failure type='fail-verdict'>Timeout waiting for ClearCommand/Release
Neels Hofmeyrfc0384a2018-04-11 15:56:41 +0200[diff] [blame]50 MSC_Tests.ttcn:MASKED MSC_Tests control part
51 MSC_Tests.ttcn:MASKED TC_cm_serv_req_vbs_reject testcase
Philipp Maierc6e06f72018-04-11 18:12:23 +0200[diff] [blame]52 </failure>
53 </testcase>
Neels Hofmeyrfc0384a2018-04-11 15:56:41 +0200[diff] [blame]54 <testcase classname='MSC_Tests' name='TC_cm_serv_req_lcs_reject' time='MASKED'>
Philipp Maierc6e06f72018-04-11 18:12:23 +0200[diff] [blame]55 <failure type='fail-verdict'>Timeout waiting for ClearCommand/Release
Neels Hofmeyrfc0384a2018-04-11 15:56:41 +0200[diff] [blame]56 MSC_Tests.ttcn:MASKED MSC_Tests control part
57 MSC_Tests.ttcn:MASKED TC_cm_serv_req_lcs_reject testcase
Philipp Maierc6e06f72018-04-11 18:12:23 +0200[diff] [blame]58 </failure>
59 </testcase>
Neels Hofmeyrfc0384a2018-04-11 15:56:41 +0200[diff] [blame]60 <testcase classname='MSC_Tests' name='TC_cm_reest_req_reject' time='MASKED'>
Philipp Maierc6e06f72018-04-11 18:12:23 +0200[diff] [blame]61 <failure type='fail-verdict'>Timeout waiting for ClearCommand/Release
Neels Hofmeyrfc0384a2018-04-11 15:56:41 +0200[diff] [blame]62 MSC_Tests.ttcn:MASKED MSC_Tests control part
63 MSC_Tests.ttcn:MASKED TC_cm_reest_req_reject testcase
Philipp Maierc6e06f72018-04-11 18:12:23 +0200[diff] [blame]64 </failure>
65 </testcase>
Neels Hofmeyrfc0384a2018-04-11 15:56:41 +0200[diff] [blame]66 <testcase classname='MSC_Tests' name='TC_lu_auth_2G_fail' time='MASKED'/>
67 <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_encr_13_13' time='MASKED'/>
68 <testcase classname='MSC_Tests' name='TC_cl3_no_payload' time='MASKED'/>
69 <testcase classname='MSC_Tests' name='TC_cl3_rnd_payload' time='MASKED'>
Neels Hofmeyr3cf797d2018-04-05 16:56:38 +0200[diff] [blame]70 <failure type='fail-verdict'>Timeout waiting for ClearCommand or SCCP Release
Neels Hofmeyrfc0384a2018-04-11 15:56:41 +0200[diff] [blame]71 MSC_Tests.ttcn:MASKED MSC_Tests control part
72 MSC_Tests.ttcn:MASKED TC_cl3_rnd_payload testcase
Neels Hofmeyr3cf797d2018-04-05 16:56:38 +0200[diff] [blame]73 </failure>
74 </testcase>
Neels Hofmeyrfc0384a2018-04-11 15:56:41 +0200[diff] [blame]75 <testcase classname='MSC_Tests' name='TC_establish_and_nothing' time='MASKED'>
Neels Hofmeyr3cf797d2018-04-05 16:56:38 +0200[diff] [blame]76 <failure type='fail-verdict'>Timeout waiting for ClearCommand/Release
Neels Hofmeyrfc0384a2018-04-11 15:56:41 +0200[diff] [blame]77 MSC_Tests.ttcn:MASKED MSC_Tests control part
78 MSC_Tests.ttcn:MASKED TC_establish_and_nothing testcase
Neels Hofmeyr3cf797d2018-04-05 16:56:38 +0200[diff] [blame]79 </failure>
80 </testcase>
Neels Hofmeyrfc0384a2018-04-11 15:56:41 +0200[diff] [blame]81 <testcase classname='MSC_Tests' name='TC_mo_setup_and_nothing' time='MASKED'>
Philipp Maierc6e06f72018-04-11 18:12:23 +0200[diff] [blame]82 <failure type='fail-verdict'>Timeout waiting for ClearCommand/Release
Neels Hofmeyrfc0384a2018-04-11 15:56:41 +0200[diff] [blame]83 MSC_Tests.ttcn:MASKED MSC_Tests control part
84 MSC_Tests.ttcn:MASKED TC_mo_setup_and_nothing testcase
Neels Hofmeyr3cf797d2018-04-05 16:56:38 +0200[diff] [blame]85 </failure>
86 </testcase>
Neels Hofmeyrfc0384a2018-04-11 15:56:41 +0200[diff] [blame]87 <testcase classname='MSC_Tests' name='TC_mo_crcx_ran_timeout' time='MASKED'/>
88 <testcase classname='MSC_Tests' name='TC_mo_crcx_ran_reject' time='MASKED'/>
89 <testcase classname='MSC_Tests' name='TC_mt_crcx_ran_reject' time='MASKED'>
Philipp Maierc6e06f72018-04-11 18:12:23 +0200[diff] [blame]90 <failure type='fail-verdict'>Timeout waiting for channel release
Neels Hofmeyrfc0384a2018-04-11 15:56:41 +0200[diff] [blame]91 MSC_Tests.ttcn:MASKED MSC_Tests control part
92 MSC_Tests.ttcn:MASKED TC_mt_crcx_ran_reject testcase
Philipp Maierc6e06f72018-04-11 18:12:23 +0200[diff] [blame]93 </failure>
94 </testcase>
Neels Hofmeyrfc0384a2018-04-11 15:56:41 +0200[diff] [blame]95 <testcase classname='MSC_Tests' name='TC_mo_setup_and_dtmf_dup' time='MASKED'/>
96 <testcase classname='MSC_Tests' name='TC_gsup_cancel' time='MASKED'>
Neels Hofmeyr3cf797d2018-04-05 16:56:38 +0200[diff] [blame]97 <error type='DTE'></error>
98 </testcase>
Neels Hofmeyrfc0384a2018-04-11 15:56:41 +0200[diff] [blame]99 <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_encr_1_13' time='MASKED'/>
100 <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_encr_3_13' time='MASKED'/>
101 <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_encr_3_1' time='MASKED'/>
102 <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_encr_3_1_no_cm' time='MASKED'/>
103 <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_encr_13_2' time='MASKED'/>
104 <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_encr_013_2' time='MASKED'/>
105 <testcase classname='MSC_Tests' name='TC_mo_release_timeout' time='MASKED'/>
106 <testcase classname='MSC_Tests' name='TC_lu_and_mt_call_no_dlcx_resp' time='MASKED'/>
107 <testcase classname='MSC_Tests' name='TC_reset_two' time='MASKED'/>
108 <testcase classname='MSC_Tests' name='TC_lu_and_mt_call' time='MASKED'/>
Neels Hofmeyr98d428d2018-04-11 15:54:07 +0200[diff] [blame^]109 <testcase classname='MSC_Tests' name='TC_lu_and_mo_sms' time='MASKED'/>
110 <testcase classname='MSC_Tests' name='TC_lu_and_mt_sms' time='MASKED'>
111 <failure type='fail-verdict'>Unexpected SMS related PDU from MSC
112 MSC_Tests.ttcn:MASKED MSC_Tests control part
113 MSC_Tests.ttcn:MASKED TC_lu_and_mt_sms testcase
114 </failure>
115 </testcase>
Neels Hofmeyrfc0384a2018-04-11 15:56:41 +0200[diff] [blame]116 <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_encr_3_1_log_msc_debug' time='MASKED'/>
Neels Hofmeyr3cf797d2018-04-05 16:56:38 +0200[diff] [blame]117</testsuite>