Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /* Auto-generated config file hpl_oscctrl_config.h */ |
| 2 | #ifndef HPL_OSCCTRL_CONFIG_H |
| 3 | #define HPL_OSCCTRL_CONFIG_H |
| 4 | |
| 5 | // <<< Use Configuration Wizard in Context Menu >>> |
| 6 | |
| 7 | // <e> External Multipurpose Crystal Oscillator Configuration |
| 8 | // <i> Indicates whether configuration for XOSC0 is enabled or not |
| 9 | // <id> enable_xosc0 |
| 10 | #ifndef CONF_XOSC0_CONFIG |
| 11 | #define CONF_XOSC0_CONFIG 0 |
| 12 | #endif |
| 13 | |
| 14 | // <o> Frequency <8000000-48000000> |
| 15 | // <i> Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator. |
| 16 | // <id> xosc0_frequency |
| 17 | #ifndef CONF_XOSC_FREQUENCY |
| 18 | #define CONF_XOSC0_FREQUENCY 12000000 |
| 19 | #endif |
| 20 | |
| 21 | // <h> External Multipurpose Crystal Oscillator Control |
| 22 | // <q> Oscillator enable |
| 23 | // <i> Indicates whether External Multipurpose Crystal Oscillator is enabled or not |
| 24 | // <id> xosc0_arch_enable |
| 25 | #ifndef CONF_XOSC0_ENABLE |
| 26 | #define CONF_XOSC0_ENABLE 0 |
| 27 | #endif |
| 28 | |
| 29 | // <o> Start-Up Time |
| 30 | // <0x0=>31us |
| 31 | // <0x1=>61us |
| 32 | // <0x2=>122us |
| 33 | // <0x3=>244us |
| 34 | // <0x4=>488us |
| 35 | // <0x5=>977us |
| 36 | // <0x6=>1953us |
| 37 | // <0x7=>3906us |
| 38 | // <0x8=>7813us |
| 39 | // <0x9=>15625us |
| 40 | // <0xA=>31250us |
| 41 | // <0xB=>62500us |
| 42 | // <0xC=>125000us |
| 43 | // <0xD=>250000us |
| 44 | // <0xE=>500000us |
| 45 | // <0xF=>1000000us |
| 46 | // <id> xosc0_arch_startup |
| 47 | #ifndef CONF_XOSC0_STARTUP |
| 48 | #define CONF_XOSC0_STARTUP 0 |
| 49 | #endif |
| 50 | |
| 51 | // <q> Clock Switch Back |
| 52 | // <i> Indicates whether Clock Switch Back is enabled or not |
| 53 | // <id> xosc0_arch_swben |
| 54 | #ifndef CONF_XOSC0_SWBEN |
| 55 | #define CONF_XOSC0_SWBEN 0 |
| 56 | #endif |
| 57 | |
| 58 | // <q> Clock Failure Detector |
| 59 | // <i> Indicates whether Clock Failure Detector is enabled or not |
| 60 | // <id> xosc0_arch_cfden |
| 61 | #ifndef CONF_XOSC0_CFDEN |
| 62 | #define CONF_XOSC0_CFDEN 0 |
| 63 | #endif |
| 64 | |
| 65 | // <q> Automatic Loop Control Enable |
| 66 | // <i> Indicates whether Automatic Loop Control is enabled or not |
| 67 | // <id> xosc0_arch_enalc |
| 68 | #ifndef CONF_XOSC0_ENALC |
| 69 | #define CONF_XOSC0_ENALC 0 |
| 70 | #endif |
| 71 | |
| 72 | // <q> Low Buffer Gain Enable |
| 73 | // <i> Indicates whether Low Buffer Gain is enabled or not |
| 74 | // <id> xosc0_arch_lowbufgain |
| 75 | #ifndef CONF_XOSC0_LOWBUFGAIN |
| 76 | #define CONF_XOSC0_LOWBUFGAIN 0 |
| 77 | #endif |
| 78 | |
| 79 | // <q> On Demand Control |
| 80 | // <i> Indicates whether On Demand Control is enabled or not |
| 81 | // <id> xosc0_arch_ondemand |
| 82 | #ifndef CONF_XOSC0_ONDEMAND |
| 83 | #define CONF_XOSC0_ONDEMAND 0 |
| 84 | #endif |
| 85 | |
| 86 | // <q> Run in Standby |
| 87 | // <i> Indicates whether Run in Standby is enabled or not |
| 88 | // <id> xosc0_arch_runstdby |
| 89 | #ifndef CONF_XOSC0_RUNSTDBY |
| 90 | #define CONF_XOSC0_RUNSTDBY 0 |
| 91 | #endif |
| 92 | |
| 93 | // <q> Crystal connected to XIN/XOUT Enable |
| 94 | // <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not |
| 95 | // <id> xosc0_arch_xtalen |
| 96 | #ifndef CONF_XOSC0_XTALEN |
| 97 | #define CONF_XOSC0_XTALEN 0 |
| 98 | #endif |
| 99 | //</h> |
| 100 | //</e> |
| 101 | |
| 102 | #if CONF_XOSC0_FREQUENCY >= 32000000 |
| 103 | #define CONF_XOSC0_CFDPRESC 0x0 |
| 104 | #define CONF_XOSC0_IMULT 0x7 |
| 105 | #define CONF_XOSC0_IPTAT 0x3 |
| 106 | #elif CONF_XOSC0_FREQUENCY >= 24000000 |
| 107 | #define CONF_XOSC0_CFDPRESC 0x1 |
| 108 | #define CONF_XOSC0_IMULT 0x6 |
| 109 | #define CONF_XOSC0_IPTAT 0x3 |
| 110 | #elif CONF_XOSC0_FREQUENCY >= 16000000 |
| 111 | #define CONF_XOSC0_CFDPRESC 0x2 |
| 112 | #define CONF_XOSC0_IMULT 0x5 |
| 113 | #define CONF_XOSC0_IPTAT 0x3 |
| 114 | #elif CONF_XOSC0_FREQUENCY >= 8000000 |
| 115 | #define CONF_XOSC0_CFDPRESC 0x3 |
| 116 | #define CONF_XOSC0_IMULT 0x4 |
| 117 | #define CONF_XOSC0_IPTAT 0x3 |
| 118 | #endif |
| 119 | |
| 120 | // <e> External Multipurpose Crystal Oscillator Configuration |
| 121 | // <i> Indicates whether configuration for XOSC1 is enabled or not |
| 122 | // <id> enable_xosc1 |
| 123 | #ifndef CONF_XOSC1_CONFIG |
| 124 | #define CONF_XOSC1_CONFIG 1 |
| 125 | #endif |
| 126 | |
| 127 | // <o> Frequency <8000000-48000000> |
| 128 | // <i> Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator. |
| 129 | // <id> xosc1_frequency |
| 130 | #ifndef CONF_XOSC_FREQUENCY |
| 131 | #define CONF_XOSC1_FREQUENCY 12000000 |
| 132 | #endif |
| 133 | |
| 134 | // <h> External Multipurpose Crystal Oscillator Control |
| 135 | // <q> Oscillator enable |
| 136 | // <i> Indicates whether External Multipurpose Crystal Oscillator is enabled or not |
| 137 | // <id> xosc1_arch_enable |
| 138 | #ifndef CONF_XOSC1_ENABLE |
| 139 | #define CONF_XOSC1_ENABLE 1 |
| 140 | #endif |
| 141 | |
| 142 | // <o> Start-Up Time |
| 143 | // <0x0=>31us |
| 144 | // <0x1=>61us |
| 145 | // <0x2=>122us |
| 146 | // <0x3=>244us |
| 147 | // <0x4=>488us |
| 148 | // <0x5=>977us |
| 149 | // <0x6=>1953us |
| 150 | // <0x7=>3906us |
| 151 | // <0x8=>7813us |
| 152 | // <0x9=>15625us |
| 153 | // <0xA=>31250us |
| 154 | // <0xB=>62500us |
| 155 | // <0xC=>125000us |
| 156 | // <0xD=>250000us |
| 157 | // <0xE=>500000us |
| 158 | // <0xF=>1000000us |
| 159 | // <id> xosc1_arch_startup |
| 160 | #ifndef CONF_XOSC1_STARTUP |
| 161 | #define CONF_XOSC1_STARTUP 0 |
| 162 | #endif |
| 163 | |
| 164 | // <q> Clock Switch Back |
| 165 | // <i> Indicates whether Clock Switch Back is enabled or not |
| 166 | // <id> xosc1_arch_swben |
| 167 | #ifndef CONF_XOSC1_SWBEN |
| 168 | #define CONF_XOSC1_SWBEN 0 |
| 169 | #endif |
| 170 | |
| 171 | // <q> Clock Failure Detector |
| 172 | // <i> Indicates whether Clock Failure Detector is enabled or not |
| 173 | // <id> xosc1_arch_cfden |
| 174 | #ifndef CONF_XOSC1_CFDEN |
| 175 | #define CONF_XOSC1_CFDEN 0 |
| 176 | #endif |
| 177 | |
| 178 | // <q> Automatic Loop Control Enable |
| 179 | // <i> Indicates whether Automatic Loop Control is enabled or not |
| 180 | // <id> xosc1_arch_enalc |
| 181 | #ifndef CONF_XOSC1_ENALC |
| 182 | #define CONF_XOSC1_ENALC 0 |
| 183 | #endif |
| 184 | |
| 185 | // <q> Low Buffer Gain Enable |
| 186 | // <i> Indicates whether Low Buffer Gain is enabled or not |
| 187 | // <id> xosc1_arch_lowbufgain |
| 188 | #ifndef CONF_XOSC1_LOWBUFGAIN |
| 189 | #define CONF_XOSC1_LOWBUFGAIN 0 |
| 190 | #endif |
| 191 | |
| 192 | // <q> On Demand Control |
| 193 | // <i> Indicates whether On Demand Control is enabled or not |
| 194 | // <id> xosc1_arch_ondemand |
| 195 | #ifndef CONF_XOSC1_ONDEMAND |
| 196 | #define CONF_XOSC1_ONDEMAND 0 |
| 197 | #endif |
| 198 | |
| 199 | // <q> Run in Standby |
| 200 | // <i> Indicates whether Run in Standby is enabled or not |
| 201 | // <id> xosc1_arch_runstdby |
| 202 | #ifndef CONF_XOSC1_RUNSTDBY |
| 203 | #define CONF_XOSC1_RUNSTDBY 0 |
| 204 | #endif |
| 205 | |
| 206 | // <q> Crystal connected to XIN/XOUT Enable |
| 207 | // <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not |
| 208 | // <id> xosc1_arch_xtalen |
| 209 | #ifndef CONF_XOSC1_XTALEN |
| 210 | #define CONF_XOSC1_XTALEN 1 |
| 211 | #endif |
| 212 | //</h> |
| 213 | //</e> |
| 214 | |
| 215 | #if CONF_XOSC1_FREQUENCY >= 32000000 |
| 216 | #define CONF_XOSC1_CFDPRESC 0x0 |
| 217 | #define CONF_XOSC1_IMULT 0x7 |
| 218 | #define CONF_XOSC1_IPTAT 0x3 |
| 219 | #elif CONF_XOSC1_FREQUENCY >= 24000000 |
| 220 | #define CONF_XOSC1_CFDPRESC 0x1 |
| 221 | #define CONF_XOSC1_IMULT 0x6 |
| 222 | #define CONF_XOSC1_IPTAT 0x3 |
| 223 | #elif CONF_XOSC1_FREQUENCY >= 16000000 |
| 224 | #define CONF_XOSC1_CFDPRESC 0x2 |
| 225 | #define CONF_XOSC1_IMULT 0x5 |
| 226 | #define CONF_XOSC1_IPTAT 0x3 |
| 227 | #elif CONF_XOSC1_FREQUENCY >= 8000000 |
| 228 | #define CONF_XOSC1_CFDPRESC 0x3 |
| 229 | #define CONF_XOSC1_IMULT 0x4 |
| 230 | #define CONF_XOSC1_IPTAT 0x3 |
| 231 | #endif |
| 232 | |
| 233 | // <e> DFLL Configuration |
| 234 | // <i> Indicates whether configuration for DFLL is enabled or not |
| 235 | // <id> enable_dfll |
| 236 | #ifndef CONF_DFLL_CONFIG |
| 237 | #define CONF_DFLL_CONFIG 1 |
| 238 | #endif |
| 239 | |
| 240 | // <y> Reference Clock Source |
| 241 | // <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 |
| 242 | // <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 |
| 243 | // <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 |
| 244 | // <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 |
| 245 | // <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 |
| 246 | // <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 |
| 247 | // <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 |
| 248 | // <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 |
| 249 | // <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8 |
| 250 | // <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9 |
| 251 | // <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10 |
| 252 | // <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11 |
| 253 | // <i> Select the clock source |
| 254 | // <id> dfll_ref_clock |
| 255 | #ifndef CONF_DFLL_GCLK |
| 256 | #define CONF_DFLL_GCLK GCLK_PCHCTRL_GEN_GCLK3_Val |
| 257 | #endif |
| 258 | |
| 259 | // <h> Digital Frequency Locked Loop Control |
| 260 | // <q> DFLL Enable |
| 261 | // <i> Indicates whether DFLL is enabled or not |
| 262 | // <id> dfll_arch_enable |
| 263 | #ifndef CONF_DFLL_ENABLE |
| 264 | #define CONF_DFLL_ENABLE 1 |
| 265 | #endif |
| 266 | |
| 267 | // <q> On Demand Control |
| 268 | // <i> Indicates whether On Demand Control is enabled or not |
| 269 | // <id> dfll_arch_ondemand |
| 270 | #ifndef CONF_DFLL_ONDEMAND |
| 271 | #define CONF_DFLL_ONDEMAND 0 |
| 272 | #endif |
| 273 | |
| 274 | // <q> Run in Standby |
| 275 | // <i> Indicates whether Run in Standby is enabled or not |
| 276 | // <id> dfll_arch_runstdby |
| 277 | #ifndef CONF_DFLL_RUNSTDBY |
| 278 | #define CONF_DFLL_RUNSTDBY 0 |
| 279 | #endif |
| 280 | |
| 281 | // <q> USB Clock Recovery Mode |
| 282 | // <i> Indicates whether USB Clock Recovery Mode is enabled or not |
| 283 | // <id> dfll_arch_usbcrm |
| 284 | #ifndef CONF_DFLL_USBCRM |
| 285 | #define CONF_DFLL_USBCRM 1 |
| 286 | #endif |
| 287 | |
| 288 | // <q> Wait Lock |
| 289 | // <i> Indicates whether Wait Lock is enabled or not |
| 290 | // <id> dfll_arch_waitlock |
| 291 | #ifndef CONF_DFLL_WAITLOCK |
| 292 | #define CONF_DFLL_WAITLOCK 0 |
| 293 | #endif |
| 294 | |
| 295 | // <q> Bypass Coarse Lock |
| 296 | // <i> Indicates whether Bypass Coarse Lock is enabled or not |
| 297 | // <id> dfll_arch_bplckc |
| 298 | #ifndef CONF_DFLL_BPLCKC |
| 299 | #define CONF_DFLL_BPLCKC 0 |
| 300 | #endif |
| 301 | |
| 302 | // <q> Quick Lock Disable |
| 303 | // <i> Indicates whether Quick Lock Disable is enabled or not |
| 304 | // <id> dfll_arch_qldis |
| 305 | #ifndef CONF_DFLL_QLDIS |
| 306 | #define CONF_DFLL_QLDIS 0 |
| 307 | #endif |
| 308 | |
| 309 | // <q> Chill Cycle Disable |
| 310 | // <i> Indicates whether Chill Cycle Disable is enabled or not |
| 311 | // <id> dfll_arch_ccdis |
| 312 | #ifndef CONF_DFLL_CCDIS |
| 313 | #define CONF_DFLL_CCDIS 1 |
| 314 | #endif |
| 315 | |
| 316 | // <q> Lose Lock After Wake |
| 317 | // <i> Indicates whether Lose Lock After Wake is enabled or not |
| 318 | // <id> dfll_arch_llaw |
| 319 | #ifndef CONF_DFLL_LLAW |
| 320 | #define CONF_DFLL_LLAW 0 |
| 321 | #endif |
| 322 | |
| 323 | // <q> Stable DFLL Frequency |
| 324 | // <i> Indicates whether Stable DFLL Frequency is enabled or not |
| 325 | // <id> dfll_arch_stable |
| 326 | #ifndef CONF_DFLL_STABLE |
| 327 | #define CONF_DFLL_STABLE 0 |
| 328 | #endif |
| 329 | |
| 330 | // <o> Operating Mode Selection |
| 331 | // <0=>Open Loop Mode |
| 332 | // <1=>Closed Loop Mode |
| 333 | // <id> dfll_mode |
| 334 | #ifndef CONF_DFLL_MODE |
| 335 | #define CONF_DFLL_MODE 0x1 |
| 336 | #endif |
| 337 | |
| 338 | // <o> Coarse Maximum Step <0x0-0x1F> |
| 339 | // <id> dfll_arch_cstep |
| 340 | #ifndef CONF_DFLL_CSTEP |
| 341 | #define CONF_DFLL_CSTEP 0x1 |
| 342 | #endif |
| 343 | |
| 344 | // <o> Fine Maximum Step <0x0-0xFF> |
| 345 | // <id> dfll_arch_fstep |
| 346 | #ifndef CONF_DFLL_FSTEP |
| 347 | #define CONF_DFLL_FSTEP 0x1 |
| 348 | #endif |
| 349 | |
| 350 | // <o> DFLL Multiply Factor <0x0-0xFFFF> |
| 351 | // <id> dfll_mul |
| 352 | #ifndef CONF_DFLL_MUL |
| 353 | #define CONF_DFLL_MUL 0xbb80 |
| 354 | #endif |
| 355 | |
| 356 | // <e> DFLL Calibration Overwrite |
| 357 | // <i> Indicates whether Overwrite Calibration value of DFLL |
| 358 | // <id> dfll_arch_calibration |
| 359 | #ifndef CONF_DFLL_OVERWRITE_CALIBRATION |
| 360 | #define CONF_DFLL_OVERWRITE_CALIBRATION 0 |
| 361 | #endif |
| 362 | |
| 363 | // <o> Coarse Value <0x0-0x3F> |
| 364 | // <id> dfll_arch_coarse |
| 365 | #ifndef CONF_DFLL_COARSE |
| 366 | #define CONF_DFLL_COARSE (0x1f / 4) |
| 367 | #endif |
| 368 | |
| 369 | // <o> Fine Value <0x0-0xFF> |
| 370 | // <id> dfll_arch_fine |
| 371 | #ifndef CONF_DFLL_FINE |
| 372 | #define CONF_DFLL_FINE (0x80) |
| 373 | #endif |
| 374 | |
| 375 | //</e> |
| 376 | |
| 377 | //</h> |
| 378 | |
| 379 | //</e> |
| 380 | |
| 381 | // <e> FDPLL0 Configuration |
| 382 | // <i> Indicates whether configuration for FDPLL0 is enabled or not |
| 383 | // <id> enable_fdpll0 |
| 384 | #ifndef CONF_FDPLL0_CONFIG |
Kévin Redon | 4a2d8f4 | 2019-01-24 17:15:10 +0100 | [diff] [blame] | 385 | #define CONF_FDPLL0_CONFIG 1 |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 386 | #endif |
| 387 | |
| 388 | // <y> Reference Clock Source |
| 389 | // <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) |
| 390 | // <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0) |
| 391 | // <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1) |
| 392 | // <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 |
| 393 | // <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 |
| 394 | // <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 |
| 395 | // <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 |
| 396 | // <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 |
| 397 | // <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 |
| 398 | // <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 |
| 399 | // <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 |
| 400 | // <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8 |
| 401 | // <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9 |
| 402 | // <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10 |
| 403 | // <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11 |
| 404 | // <i> Select the clock source. |
| 405 | // <id> fdpll0_ref_clock |
| 406 | #ifndef CONF_FDPLL0_GCLK |
Kévin Redon | 293c841 | 2019-01-30 11:18:10 +0100 | [diff] [blame] | 407 | // directly use XOSC1 as clock input (no need to use an additional GCLK) |
Kévin Redon | 6b9363c | 2019-01-24 17:21:33 +0100 | [diff] [blame] | 408 | #define CONF_FDPLL0_GCLK GCLK_GENCTRL_SRC_XOSC1 |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 409 | #endif |
| 410 | |
| 411 | // <h> Digital Phase Locked Loop Control |
| 412 | // <q> Enable |
| 413 | // <i> Indicates whether Digital Phase Locked Loop is enabled or not |
| 414 | // <id> fdpll0_arch_enable |
| 415 | #ifndef CONF_FDPLL0_ENABLE |
Kévin Redon | 4a2d8f4 | 2019-01-24 17:15:10 +0100 | [diff] [blame] | 416 | #define CONF_FDPLL0_ENABLE 1 |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 417 | #endif |
| 418 | |
| 419 | // <q> On Demand Control |
| 420 | // <i> Indicates whether On Demand Control is enabled or not |
| 421 | // <id> fdpll0_arch_ondemand |
| 422 | #ifndef CONF_FDPLL0_ONDEMAND |
| 423 | #define CONF_FDPLL0_ONDEMAND 0 |
| 424 | #endif |
| 425 | |
| 426 | // <q> Run in Standby |
| 427 | // <i> Indicates whether Run in Standby is enabled or not |
| 428 | // <id> fdpll0_arch_runstdby |
| 429 | #ifndef CONF_FDPLL0_RUNSTDBY |
| 430 | #define CONF_FDPLL0_RUNSTDBY 0 |
| 431 | #endif |
| 432 | |
| 433 | // <o> Loop Divider Ratio Fractional Part <0x0-0x1F> |
| 434 | // <id> fdpll0_ldrfrac |
| 435 | #ifndef CONF_FDPLL0_LDRFRAC |
Kévin Redon | 4a2d8f4 | 2019-01-24 17:15:10 +0100 | [diff] [blame] | 436 | #define CONF_FDPLL0_LDRFRAC 0x0 |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 437 | #endif |
| 438 | |
| 439 | // <o> Loop Divider Ratio Integer Part <0x0-0x1FFF> |
| 440 | // <id> fdpll0_ldr |
| 441 | #ifndef CONF_FDPLL0_LDR |
Kévin Redon | 293c841 | 2019-01-30 11:18:10 +0100 | [diff] [blame] | 442 | // 2 MHz input clock * ( <59> + 1 = 60 ) = 120 MHz output clock |
| 443 | #define CONF_FDPLL0_LDR 59 |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 444 | #endif |
| 445 | |
| 446 | // <o> Clock Divider <0x0-0x7FF> |
| 447 | // <id> fdpll0_clock_div |
| 448 | #ifndef CONF_FDPLL0_DIV |
Kévin Redon | 293c841 | 2019-01-30 11:18:10 +0100 | [diff] [blame] | 449 | // XOSC1 = 12 MHz, divide by 2 * ( <2> + 1 ) = 6 to have a 2 MHz clock input (maximum is 3.4 MHz) |
| 450 | #define CONF_FDPLL0_DIV 2 |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 451 | #endif |
| 452 | |
| 453 | // <q> DCO Filter Enable |
| 454 | // <i> Indicates whether DCO Filter Enable is enabled or not |
| 455 | // <id> fdpll0_arch_dcoen |
| 456 | #ifndef CONF_FDPLL0_DCOEN |
| 457 | #define CONF_FDPLL0_DCOEN 0 |
| 458 | #endif |
| 459 | |
| 460 | // <o> Sigma-Delta DCO Filter Selection <0x0-0x7> |
| 461 | // <id> fdpll0_clock_dcofilter |
| 462 | #ifndef CONF_FDPLL0_DCOFILTER |
| 463 | #define CONF_FDPLL0_DCOFILTER 0x0 |
| 464 | #endif |
| 465 | |
| 466 | // <q> Lock Bypass |
| 467 | // <i> Indicates whether Lock Bypass is enabled or not |
| 468 | // <id> fdpll0_arch_lbypass |
| 469 | #ifndef CONF_FDPLL0_LBYPASS |
| 470 | #define CONF_FDPLL0_LBYPASS 0 |
| 471 | #endif |
| 472 | |
| 473 | // <o> Lock Time |
| 474 | // <0x0=>No time-out, automatic lock |
| 475 | // <0x4=>The Time-out if no lock within 800 us |
| 476 | // <0x5=>The Time-out if no lock within 900 us |
| 477 | // <0x6=>The Time-out if no lock within 1 ms |
| 478 | // <0x7=>The Time-out if no lock within 11 ms |
| 479 | // <id> fdpll0_arch_ltime |
| 480 | #ifndef CONF_FDPLL0_LTIME |
| 481 | #define CONF_FDPLL0_LTIME 0x0 |
| 482 | #endif |
| 483 | |
| 484 | // <o> Reference Clock Selection |
| 485 | // <0x0=>GCLK clock reference |
| 486 | // <0x1=>XOSC32K clock reference |
| 487 | // <0x2=>XOSC0 clock reference |
| 488 | // <0x3=>XOSC1 clock reference |
| 489 | // <id> fdpll0_arch_refclk |
| 490 | #ifndef CONF_FDPLL0_REFCLK |
Kévin Redon | 293c841 | 2019-01-30 11:18:10 +0100 | [diff] [blame] | 491 | // XOSC1 is used as input signal, thus also use it as reference |
Kévin Redon | 4a2d8f4 | 2019-01-24 17:15:10 +0100 | [diff] [blame] | 492 | #define CONF_FDPLL0_REFCLK 0x3 |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 493 | #endif |
| 494 | |
| 495 | // <q> Wake Up Fast |
| 496 | // <i> Indicates whether Wake Up Fast is enabled or not |
| 497 | // <id> fdpll0_arch_wuf |
| 498 | #ifndef CONF_FDPLL0_WUF |
| 499 | #define CONF_FDPLL0_WUF 0 |
| 500 | #endif |
| 501 | |
| 502 | // <o> Proportional Integral Filter Selection <0x0-0xF> |
| 503 | // <id> fdpll0_arch_filter |
| 504 | #ifndef CONF_FDPLL0_FILTER |
| 505 | #define CONF_FDPLL0_FILTER 0x0 |
| 506 | #endif |
| 507 | |
| 508 | //</h> |
| 509 | //</e> |
| 510 | // <e> FDPLL1 Configuration |
| 511 | // <i> Indicates whether configuration for FDPLL1 is enabled or not |
| 512 | // <id> enable_fdpll1 |
| 513 | #ifndef CONF_FDPLL1_CONFIG |
Kévin Redon | 4cb8e32 | 2019-01-24 17:41:44 +0100 | [diff] [blame] | 514 | #define CONF_FDPLL1_CONFIG 1 |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 515 | #endif |
| 516 | |
| 517 | // <y> Reference Clock Source |
| 518 | // <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) |
| 519 | // <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0) |
| 520 | // <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1) |
| 521 | // <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 |
| 522 | // <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 |
| 523 | // <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 |
| 524 | // <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 |
| 525 | // <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 |
| 526 | // <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 |
| 527 | // <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 |
| 528 | // <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 |
| 529 | // <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8 |
| 530 | // <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9 |
| 531 | // <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10 |
| 532 | // <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11 |
| 533 | // <i> Select the clock source. |
| 534 | // <id> fdpll1_ref_clock |
| 535 | #ifndef CONF_FDPLL1_GCLK |
Kévin Redon | 293c841 | 2019-01-30 11:18:10 +0100 | [diff] [blame] | 536 | // directly use XOSC1 as clock input (no need to use an additional GCLK) |
Kévin Redon | 4cb8e32 | 2019-01-24 17:41:44 +0100 | [diff] [blame] | 537 | #define CONF_FDPLL1_GCLK GCLK_GENCTRL_SRC_XOSC1 |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 538 | #endif |
| 539 | |
| 540 | // <h> Digital Phase Locked Loop Control |
| 541 | // <q> Enable |
| 542 | // <i> Indicates whether Digital Phase Locked Loop is enabled or not |
| 543 | // <id> fdpll1_arch_enable |
| 544 | #ifndef CONF_FDPLL1_ENABLE |
Kévin Redon | 20abc4f | 2019-01-24 17:32:17 +0100 | [diff] [blame] | 545 | #define CONF_FDPLL1_ENABLE 1 |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 546 | #endif |
| 547 | |
| 548 | // <q> On Demand Control |
| 549 | // <i> Indicates whether On Demand Control is enabled or not |
| 550 | // <id> fdpll1_arch_ondemand |
| 551 | #ifndef CONF_FDPLL1_ONDEMAND |
| 552 | #define CONF_FDPLL1_ONDEMAND 0 |
| 553 | #endif |
| 554 | |
| 555 | // <q> Run in Standby |
| 556 | // <i> Indicates whether Run in Standby is enabled or not |
| 557 | // <id> fdpll1_arch_runstdby |
| 558 | #ifndef CONF_FDPLL1_RUNSTDBY |
| 559 | #define CONF_FDPLL1_RUNSTDBY 0 |
| 560 | #endif |
| 561 | |
| 562 | // <o> Loop Divider Ratio Fractional Part <0x0-0x1F> |
| 563 | // <id> fdpll1_ldrfrac |
| 564 | #ifndef CONF_FDPLL1_LDRFRAC |
Kévin Redon | 20abc4f | 2019-01-24 17:32:17 +0100 | [diff] [blame] | 565 | #define CONF_FDPLL1_LDRFRAC 0x0 |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 566 | #endif |
| 567 | |
| 568 | // <o> Loop Divider Ratio Integer Part <0x0-0x1FFF> |
| 569 | // <id> fdpll1_ldr |
| 570 | #ifndef CONF_FDPLL1_LDR |
Kévin Redon | 293c841 | 2019-01-30 11:18:10 +0100 | [diff] [blame] | 571 | // 2 MHz input clock * ( <49> + 1 = 50 ) = 100 MHz output clock |
| 572 | #define CONF_FDPLL1_LDR 49 |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 573 | #endif |
| 574 | |
| 575 | // <o> Clock Divider <0x0-0x7FF> |
| 576 | // <id> fdpll1_clock_div |
| 577 | #ifndef CONF_FDPLL1_DIV |
Kévin Redon | 293c841 | 2019-01-30 11:18:10 +0100 | [diff] [blame] | 578 | // XOSC1 = 12 MHz, divide by 2 * ( <2> + 1 ) = 6 to have a 2 MHz clock input (maximum is 3.4 MHz) |
| 579 | #define CONF_FDPLL1_DIV 2 |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 580 | #endif |
| 581 | |
| 582 | // <q> DCO Filter Enable |
| 583 | // <i> Indicates whether DCO Filter Enable is enabled or not |
| 584 | // <id> fdpll1_arch_dcoen |
| 585 | #ifndef CONF_FDPLL1_DCOEN |
| 586 | #define CONF_FDPLL1_DCOEN 0 |
| 587 | #endif |
| 588 | |
| 589 | // <o> Sigma-Delta DCO Filter Selection <0x0-0x7> |
| 590 | // <id> fdpll1_clock_dcofilter |
| 591 | #ifndef CONF_FDPLL1_DCOFILTER |
| 592 | #define CONF_FDPLL1_DCOFILTER 0x0 |
| 593 | #endif |
| 594 | |
| 595 | // <q> Lock Bypass |
| 596 | // <i> Indicates whether Lock Bypass is enabled or not |
| 597 | // <id> fdpll1_arch_lbypass |
| 598 | #ifndef CONF_FDPLL1_LBYPASS |
| 599 | #define CONF_FDPLL1_LBYPASS 0 |
| 600 | #endif |
| 601 | |
| 602 | // <o> Lock Time |
| 603 | // <0x0=>No time-out, automatic lock |
| 604 | // <0x4=>The Time-out if no lock within 800 us |
| 605 | // <0x5=>The Time-out if no lock within 900 us |
| 606 | // <0x6=>The Time-out if no lock within 1 ms |
| 607 | // <0x7=>The Time-out if no lock within 11 ms |
| 608 | // <id> fdpll1_arch_ltime |
| 609 | #ifndef CONF_FDPLL1_LTIME |
| 610 | #define CONF_FDPLL1_LTIME 0x0 |
| 611 | #endif |
| 612 | |
| 613 | // <o> Reference Clock Selection |
| 614 | // <0x0=>GCLK clock reference |
| 615 | // <0x1=>XOSC32K clock reference |
| 616 | // <0x2=>XOSC0 clock reference |
| 617 | // <0x3=>XOSC1 clock reference |
| 618 | // <id> fdpll1_arch_refclk |
| 619 | #ifndef CONF_FDPLL1_REFCLK |
Kévin Redon | 293c841 | 2019-01-30 11:18:10 +0100 | [diff] [blame] | 620 | // XOSC1 is used as input signal, thus also use it as reference |
Kévin Redon | 20abc4f | 2019-01-24 17:32:17 +0100 | [diff] [blame] | 621 | #define CONF_FDPLL1_REFCLK 0x3 |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 622 | #endif |
| 623 | |
| 624 | // <q> Wake Up Fast |
| 625 | // <i> Indicates whether Wake Up Fast is enabled or not |
| 626 | // <id> fdpll1_arch_wuf |
| 627 | #ifndef CONF_FDPLL1_WUF |
| 628 | #define CONF_FDPLL1_WUF 0 |
| 629 | #endif |
| 630 | |
| 631 | // <o> Proportional Integral Filter Selection <0x0-0xF> |
| 632 | // <id> fdpll1_arch_filter |
| 633 | #ifndef CONF_FDPLL1_FILTER |
| 634 | #define CONF_FDPLL1_FILTER 0x0 |
| 635 | #endif |
| 636 | |
| 637 | //</h> |
| 638 | //</e> |
| 639 | |
| 640 | // <<< end of configuration section >>> |
| 641 | |
| 642 | #endif // HPL_OSCCTRL_CONFIG_H |