remove usage of GCLK11
DPLL0 can take directly XOSC1 as input and divide it to 2 MHz.
thus the intermediate GCLK11 is not needed.
this configuration is not supported by Atmel START since it does
not know about the division and thinks the input frequency
exceeds the maximum
Change-Id: I121ad850cf118b641fe522b513ffd7e00b30b710
diff --git a/sysmoOCTSIM/config/hpl_oscctrl_config.h b/sysmoOCTSIM/config/hpl_oscctrl_config.h
index d59ac43..6b3cc19 100644
--- a/sysmoOCTSIM/config/hpl_oscctrl_config.h
+++ b/sysmoOCTSIM/config/hpl_oscctrl_config.h
@@ -404,7 +404,7 @@
// <i> Select the clock source.
// <id> fdpll0_ref_clock
#ifndef CONF_FDPLL0_GCLK
-#define CONF_FDPLL0_GCLK GCLK_PCHCTRL_GEN_GCLK11_Val
+#define CONF_FDPLL0_GCLK GCLK_GENCTRL_SRC_XOSC1
#endif
// <h> Digital Phase Locked Loop Control