use XOSC1 directly for DPLL1
DPLL1 can take directly XOSC1 as input and divide it to 2 MHz.
thus the intermediate GCLK11 is not needed.
we now also completely de-configure GCLK11
this configuration is not supported by Atmel START since it does
not know about the division and thinks the input frequency
exceeds the maximum
GCLK2 is also disabled for now because it is not used
Change-Id: Icee7f5a13019c47cebc23376cabb18cb31178ece
diff --git a/sysmoOCTSIM/config/hpl_oscctrl_config.h b/sysmoOCTSIM/config/hpl_oscctrl_config.h
index 06ee571..0676cb5 100644
--- a/sysmoOCTSIM/config/hpl_oscctrl_config.h
+++ b/sysmoOCTSIM/config/hpl_oscctrl_config.h
@@ -507,7 +507,7 @@
// <i> Indicates whether configuration for FDPLL1 is enabled or not
// <id> enable_fdpll1
#ifndef CONF_FDPLL1_CONFIG
-#define CONF_FDPLL1_CONFIG 0
+#define CONF_FDPLL1_CONFIG 1
#endif
// <y> Reference Clock Source
@@ -529,7 +529,7 @@
// <i> Select the clock source.
// <id> fdpll1_ref_clock
#ifndef CONF_FDPLL1_GCLK
-#define CONF_FDPLL1_GCLK GCLK_PCHCTRL_GEN_GCLK11_Val
+#define CONF_FDPLL1_GCLK GCLK_GENCTRL_SRC_XOSC1
#endif
// <h> Digital Phase Locked Loop Control