Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /* Auto-generated config file peripheral_clk_config.h */ |
| 2 | #ifndef PERIPHERAL_CLK_CONFIG_H |
| 3 | #define PERIPHERAL_CLK_CONFIG_H |
| 4 | |
| 5 | // <<< Use Configuration Wizard in Context Menu >>> |
| 6 | |
| 7 | /** |
| 8 | * \def CONF_CPU_FREQUENCY |
| 9 | * \brief CPU's Clock frequency |
| 10 | */ |
| 11 | #ifndef CONF_CPU_FREQUENCY |
Kévin Redon | 4a2d8f4 | 2019-01-24 17:15:10 +0100 | [diff] [blame] | 12 | #define CONF_CPU_FREQUENCY 120000000 |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 13 | #endif |
| 14 | |
Harald Welte | d1bd5c4 | 2019-05-17 16:38:30 +0200 | [diff] [blame] | 15 | // <y> RTC Clock Source |
| 16 | // <id> rtc_clk_selection |
| 17 | // <RTC_CLOCK_SOURCE"> RTC source |
| 18 | // <i> Select the clock source for RTC. |
| 19 | #ifndef CONF_GCLK_RTC_SRC |
| 20 | #define CONF_GCLK_RTC_SRC RTC_CLOCK_SOURCE |
| 21 | #endif |
| 22 | |
| 23 | /** |
| 24 | * \def CONF_GCLK_RTC_FREQUENCY |
| 25 | * \brief RTC's Clock frequency |
| 26 | */ |
| 27 | #ifndef CONF_GCLK_RTC_FREQUENCY |
| 28 | #define CONF_GCLK_RTC_FREQUENCY 32768 |
| 29 | #endif |
| 30 | |
Kévin Redon | 4cd3f7d | 2019-01-24 17:57:13 +0100 | [diff] [blame] | 31 | // <y> Core Clock Source |
| 32 | // <id> core_gclk_selection |
| 33 | |
| 34 | // <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 |
| 35 | |
| 36 | // <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 |
| 37 | |
| 38 | // <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 |
| 39 | |
| 40 | // <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 |
| 41 | |
| 42 | // <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 |
| 43 | |
| 44 | // <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 |
| 45 | |
| 46 | // <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 |
| 47 | |
| 48 | // <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 |
| 49 | |
| 50 | // <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8 |
| 51 | |
| 52 | // <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9 |
| 53 | |
| 54 | // <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10 |
| 55 | |
| 56 | // <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11 |
| 57 | |
| 58 | // <i> Select the clock source for CORE. |
Kévin Redon | 1f8ecef | 2019-01-31 13:36:12 +0100 | [diff] [blame] | 59 | #ifndef CONF_GCLK_SERCOM0_CORE_SRC |
| 60 | #define CONF_GCLK_SERCOM0_CORE_SRC GCLK_PCHCTRL_GEN_GCLK2_Val |
| 61 | #endif |
| 62 | |
| 63 | // <y> Slow Clock Source |
| 64 | // <id> slow_gclk_selection |
| 65 | |
| 66 | // <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 |
| 67 | |
| 68 | // <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 |
| 69 | |
| 70 | // <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 |
| 71 | |
| 72 | // <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 |
| 73 | |
| 74 | // <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 |
| 75 | |
| 76 | // <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 |
| 77 | |
| 78 | // <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 |
| 79 | |
| 80 | // <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 |
| 81 | |
| 82 | // <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8 |
| 83 | |
| 84 | // <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9 |
| 85 | |
| 86 | // <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10 |
| 87 | |
| 88 | // <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11 |
| 89 | |
| 90 | // <i> Select the slow clock source. |
| 91 | #ifndef CONF_GCLK_SERCOM0_SLOW_SRC |
| 92 | #define CONF_GCLK_SERCOM0_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val |
| 93 | #endif |
| 94 | |
| 95 | /** |
| 96 | * \def CONF_GCLK_SERCOM0_CORE_FREQUENCY |
| 97 | * \brief SERCOM0's Core Clock frequency |
| 98 | */ |
| 99 | #ifndef CONF_GCLK_SERCOM0_CORE_FREQUENCY |
Kévin Redon | 5e7cfae | 2019-04-25 15:50:30 +0200 | [diff] [blame] | 100 | #define CONF_GCLK_SERCOM0_CORE_FREQUENCY 500000 |
Kévin Redon | 1f8ecef | 2019-01-31 13:36:12 +0100 | [diff] [blame] | 101 | #endif |
| 102 | |
| 103 | /** |
| 104 | * \def CONF_GCLK_SERCOM0_SLOW_FREQUENCY |
| 105 | * \brief SERCOM0's Slow Clock frequency |
| 106 | */ |
| 107 | #ifndef CONF_GCLK_SERCOM0_SLOW_FREQUENCY |
| 108 | #define CONF_GCLK_SERCOM0_SLOW_FREQUENCY 32768 |
| 109 | #endif |
| 110 | |
| 111 | // <y> Core Clock Source |
| 112 | // <id> core_gclk_selection |
| 113 | |
| 114 | // <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 |
| 115 | |
| 116 | // <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 |
| 117 | |
| 118 | // <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 |
| 119 | |
| 120 | // <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 |
| 121 | |
| 122 | // <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 |
| 123 | |
| 124 | // <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 |
| 125 | |
| 126 | // <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 |
| 127 | |
| 128 | // <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 |
| 129 | |
| 130 | // <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8 |
| 131 | |
| 132 | // <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9 |
| 133 | |
| 134 | // <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10 |
| 135 | |
| 136 | // <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11 |
| 137 | |
| 138 | // <i> Select the clock source for CORE. |
| 139 | #ifndef CONF_GCLK_SERCOM1_CORE_SRC |
| 140 | #define CONF_GCLK_SERCOM1_CORE_SRC GCLK_PCHCTRL_GEN_GCLK2_Val |
| 141 | #endif |
| 142 | |
| 143 | // <y> Slow Clock Source |
| 144 | // <id> slow_gclk_selection |
| 145 | |
| 146 | // <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 |
| 147 | |
| 148 | // <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 |
| 149 | |
| 150 | // <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 |
| 151 | |
| 152 | // <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 |
| 153 | |
| 154 | // <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 |
| 155 | |
| 156 | // <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 |
| 157 | |
| 158 | // <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 |
| 159 | |
| 160 | // <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 |
| 161 | |
| 162 | // <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8 |
| 163 | |
| 164 | // <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9 |
| 165 | |
| 166 | // <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10 |
| 167 | |
| 168 | // <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11 |
| 169 | |
| 170 | // <i> Select the slow clock source. |
| 171 | #ifndef CONF_GCLK_SERCOM1_SLOW_SRC |
| 172 | #define CONF_GCLK_SERCOM1_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val |
| 173 | #endif |
| 174 | |
| 175 | /** |
| 176 | * \def CONF_GCLK_SERCOM1_CORE_FREQUENCY |
| 177 | * \brief SERCOM1's Core Clock frequency |
| 178 | */ |
| 179 | #ifndef CONF_GCLK_SERCOM1_CORE_FREQUENCY |
Kévin Redon | 5e7cfae | 2019-04-25 15:50:30 +0200 | [diff] [blame] | 180 | #define CONF_GCLK_SERCOM1_CORE_FREQUENCY 500000 |
Kévin Redon | 1f8ecef | 2019-01-31 13:36:12 +0100 | [diff] [blame] | 181 | #endif |
| 182 | |
| 183 | /** |
| 184 | * \def CONF_GCLK_SERCOM1_SLOW_FREQUENCY |
| 185 | * \brief SERCOM1's Slow Clock frequency |
| 186 | */ |
| 187 | #ifndef CONF_GCLK_SERCOM1_SLOW_FREQUENCY |
| 188 | #define CONF_GCLK_SERCOM1_SLOW_FREQUENCY 32768 |
| 189 | #endif |
| 190 | |
| 191 | // <y> Core Clock Source |
| 192 | // <id> core_gclk_selection |
| 193 | |
| 194 | // <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 |
| 195 | |
| 196 | // <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 |
| 197 | |
| 198 | // <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 |
| 199 | |
| 200 | // <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 |
| 201 | |
| 202 | // <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 |
| 203 | |
| 204 | // <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 |
| 205 | |
| 206 | // <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 |
| 207 | |
| 208 | // <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 |
| 209 | |
| 210 | // <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8 |
| 211 | |
| 212 | // <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9 |
| 213 | |
| 214 | // <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10 |
| 215 | |
| 216 | // <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11 |
| 217 | |
| 218 | // <i> Select the clock source for CORE. |
| 219 | #ifndef CONF_GCLK_SERCOM2_CORE_SRC |
| 220 | #define CONF_GCLK_SERCOM2_CORE_SRC GCLK_PCHCTRL_GEN_GCLK2_Val |
| 221 | #endif |
| 222 | |
| 223 | // <y> Slow Clock Source |
| 224 | // <id> slow_gclk_selection |
| 225 | |
| 226 | // <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 |
| 227 | |
| 228 | // <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 |
| 229 | |
| 230 | // <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 |
| 231 | |
| 232 | // <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 |
| 233 | |
| 234 | // <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 |
| 235 | |
| 236 | // <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 |
| 237 | |
| 238 | // <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 |
| 239 | |
| 240 | // <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 |
| 241 | |
| 242 | // <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8 |
| 243 | |
| 244 | // <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9 |
| 245 | |
| 246 | // <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10 |
| 247 | |
| 248 | // <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11 |
| 249 | |
| 250 | // <i> Select the slow clock source. |
| 251 | #ifndef CONF_GCLK_SERCOM2_SLOW_SRC |
| 252 | #define CONF_GCLK_SERCOM2_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val |
| 253 | #endif |
| 254 | |
| 255 | /** |
| 256 | * \def CONF_GCLK_SERCOM2_CORE_FREQUENCY |
| 257 | * \brief SERCOM2's Core Clock frequency |
| 258 | */ |
| 259 | #ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY |
Kévin Redon | 5e7cfae | 2019-04-25 15:50:30 +0200 | [diff] [blame] | 260 | #define CONF_GCLK_SERCOM2_CORE_FREQUENCY 500000 |
Kévin Redon | 1f8ecef | 2019-01-31 13:36:12 +0100 | [diff] [blame] | 261 | #endif |
| 262 | |
| 263 | /** |
| 264 | * \def CONF_GCLK_SERCOM2_SLOW_FREQUENCY |
| 265 | * \brief SERCOM2's Slow Clock frequency |
| 266 | */ |
| 267 | #ifndef CONF_GCLK_SERCOM2_SLOW_FREQUENCY |
| 268 | #define CONF_GCLK_SERCOM2_SLOW_FREQUENCY 32768 |
| 269 | #endif |
| 270 | |
| 271 | // <y> Core Clock Source |
| 272 | // <id> core_gclk_selection |
| 273 | |
| 274 | // <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 |
| 275 | |
| 276 | // <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 |
| 277 | |
| 278 | // <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 |
| 279 | |
| 280 | // <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 |
| 281 | |
| 282 | // <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 |
| 283 | |
| 284 | // <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 |
| 285 | |
| 286 | // <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 |
| 287 | |
| 288 | // <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 |
| 289 | |
| 290 | // <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8 |
| 291 | |
| 292 | // <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9 |
| 293 | |
| 294 | // <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10 |
| 295 | |
| 296 | // <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11 |
| 297 | |
| 298 | // <i> Select the clock source for CORE. |
| 299 | #ifndef CONF_GCLK_SERCOM3_CORE_SRC |
| 300 | #define CONF_GCLK_SERCOM3_CORE_SRC GCLK_PCHCTRL_GEN_GCLK2_Val |
| 301 | #endif |
| 302 | |
| 303 | // <y> Slow Clock Source |
| 304 | // <id> slow_gclk_selection |
| 305 | |
| 306 | // <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 |
| 307 | |
| 308 | // <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 |
| 309 | |
| 310 | // <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 |
| 311 | |
| 312 | // <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 |
| 313 | |
| 314 | // <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 |
| 315 | |
| 316 | // <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 |
| 317 | |
| 318 | // <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 |
| 319 | |
| 320 | // <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 |
| 321 | |
| 322 | // <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8 |
| 323 | |
| 324 | // <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9 |
| 325 | |
| 326 | // <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10 |
| 327 | |
| 328 | // <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11 |
| 329 | |
| 330 | // <i> Select the slow clock source. |
| 331 | #ifndef CONF_GCLK_SERCOM3_SLOW_SRC |
| 332 | #define CONF_GCLK_SERCOM3_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val |
| 333 | #endif |
| 334 | |
| 335 | /** |
| 336 | * \def CONF_GCLK_SERCOM3_CORE_FREQUENCY |
| 337 | * \brief SERCOM3's Core Clock frequency |
| 338 | */ |
| 339 | #ifndef CONF_GCLK_SERCOM3_CORE_FREQUENCY |
Kévin Redon | 5e7cfae | 2019-04-25 15:50:30 +0200 | [diff] [blame] | 340 | #define CONF_GCLK_SERCOM3_CORE_FREQUENCY 500000 |
Kévin Redon | 1f8ecef | 2019-01-31 13:36:12 +0100 | [diff] [blame] | 341 | #endif |
| 342 | |
| 343 | /** |
| 344 | * \def CONF_GCLK_SERCOM3_SLOW_FREQUENCY |
| 345 | * \brief SERCOM3's Slow Clock frequency |
| 346 | */ |
| 347 | #ifndef CONF_GCLK_SERCOM3_SLOW_FREQUENCY |
| 348 | #define CONF_GCLK_SERCOM3_SLOW_FREQUENCY 32768 |
| 349 | #endif |
| 350 | |
| 351 | // <y> Core Clock Source |
| 352 | // <id> core_gclk_selection |
| 353 | |
| 354 | // <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 |
| 355 | |
| 356 | // <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 |
| 357 | |
| 358 | // <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 |
| 359 | |
| 360 | // <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 |
| 361 | |
| 362 | // <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 |
| 363 | |
| 364 | // <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 |
| 365 | |
| 366 | // <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 |
| 367 | |
| 368 | // <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 |
| 369 | |
| 370 | // <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8 |
| 371 | |
| 372 | // <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9 |
| 373 | |
| 374 | // <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10 |
| 375 | |
| 376 | // <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11 |
| 377 | |
| 378 | // <i> Select the clock source for CORE. |
| 379 | #ifndef CONF_GCLK_SERCOM4_CORE_SRC |
| 380 | #define CONF_GCLK_SERCOM4_CORE_SRC GCLK_PCHCTRL_GEN_GCLK2_Val |
| 381 | #endif |
| 382 | |
| 383 | // <y> Slow Clock Source |
| 384 | // <id> slow_gclk_selection |
| 385 | |
| 386 | // <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 |
| 387 | |
| 388 | // <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 |
| 389 | |
| 390 | // <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 |
| 391 | |
| 392 | // <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 |
| 393 | |
| 394 | // <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 |
| 395 | |
| 396 | // <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 |
| 397 | |
| 398 | // <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 |
| 399 | |
| 400 | // <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 |
| 401 | |
| 402 | // <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8 |
| 403 | |
| 404 | // <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9 |
| 405 | |
| 406 | // <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10 |
| 407 | |
| 408 | // <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11 |
| 409 | |
| 410 | // <i> Select the slow clock source. |
| 411 | #ifndef CONF_GCLK_SERCOM4_SLOW_SRC |
| 412 | #define CONF_GCLK_SERCOM4_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val |
| 413 | #endif |
| 414 | |
| 415 | /** |
| 416 | * \def CONF_GCLK_SERCOM4_CORE_FREQUENCY |
| 417 | * \brief SERCOM4's Core Clock frequency |
| 418 | */ |
| 419 | #ifndef CONF_GCLK_SERCOM4_CORE_FREQUENCY |
Kévin Redon | 5e7cfae | 2019-04-25 15:50:30 +0200 | [diff] [blame] | 420 | #define CONF_GCLK_SERCOM4_CORE_FREQUENCY 500000 |
Kévin Redon | 1f8ecef | 2019-01-31 13:36:12 +0100 | [diff] [blame] | 421 | #endif |
| 422 | |
| 423 | /** |
| 424 | * \def CONF_GCLK_SERCOM4_SLOW_FREQUENCY |
| 425 | * \brief SERCOM4's Slow Clock frequency |
| 426 | */ |
| 427 | #ifndef CONF_GCLK_SERCOM4_SLOW_FREQUENCY |
| 428 | #define CONF_GCLK_SERCOM4_SLOW_FREQUENCY 32768 |
| 429 | #endif |
| 430 | |
| 431 | // <y> Core Clock Source |
| 432 | // <id> core_gclk_selection |
| 433 | |
| 434 | // <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 |
| 435 | |
| 436 | // <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 |
| 437 | |
| 438 | // <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 |
| 439 | |
| 440 | // <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 |
| 441 | |
| 442 | // <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 |
| 443 | |
| 444 | // <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 |
| 445 | |
| 446 | // <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 |
| 447 | |
| 448 | // <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 |
| 449 | |
| 450 | // <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8 |
| 451 | |
| 452 | // <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9 |
| 453 | |
| 454 | // <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10 |
| 455 | |
| 456 | // <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11 |
| 457 | |
| 458 | // <i> Select the clock source for CORE. |
| 459 | #ifndef CONF_GCLK_SERCOM5_CORE_SRC |
| 460 | #define CONF_GCLK_SERCOM5_CORE_SRC GCLK_PCHCTRL_GEN_GCLK2_Val |
| 461 | #endif |
| 462 | |
| 463 | // <y> Slow Clock Source |
| 464 | // <id> slow_gclk_selection |
| 465 | |
| 466 | // <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 |
| 467 | |
| 468 | // <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 |
| 469 | |
| 470 | // <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 |
| 471 | |
| 472 | // <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 |
| 473 | |
| 474 | // <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 |
| 475 | |
| 476 | // <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 |
| 477 | |
| 478 | // <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 |
| 479 | |
| 480 | // <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 |
| 481 | |
| 482 | // <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8 |
| 483 | |
| 484 | // <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9 |
| 485 | |
| 486 | // <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10 |
| 487 | |
| 488 | // <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11 |
| 489 | |
| 490 | // <i> Select the slow clock source. |
| 491 | #ifndef CONF_GCLK_SERCOM5_SLOW_SRC |
| 492 | #define CONF_GCLK_SERCOM5_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val |
| 493 | #endif |
| 494 | |
| 495 | /** |
| 496 | * \def CONF_GCLK_SERCOM5_CORE_FREQUENCY |
| 497 | * \brief SERCOM5's Core Clock frequency |
| 498 | */ |
| 499 | #ifndef CONF_GCLK_SERCOM5_CORE_FREQUENCY |
Kévin Redon | 5e7cfae | 2019-04-25 15:50:30 +0200 | [diff] [blame] | 500 | #define CONF_GCLK_SERCOM5_CORE_FREQUENCY 500000 |
Kévin Redon | 1f8ecef | 2019-01-31 13:36:12 +0100 | [diff] [blame] | 501 | #endif |
| 502 | |
| 503 | /** |
| 504 | * \def CONF_GCLK_SERCOM5_SLOW_FREQUENCY |
| 505 | * \brief SERCOM5's Slow Clock frequency |
| 506 | */ |
| 507 | #ifndef CONF_GCLK_SERCOM5_SLOW_FREQUENCY |
| 508 | #define CONF_GCLK_SERCOM5_SLOW_FREQUENCY 32768 |
| 509 | #endif |
| 510 | |
| 511 | // <y> Core Clock Source |
| 512 | // <id> core_gclk_selection |
| 513 | |
| 514 | // <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 |
| 515 | |
| 516 | // <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 |
| 517 | |
| 518 | // <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 |
| 519 | |
| 520 | // <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 |
| 521 | |
| 522 | // <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 |
| 523 | |
| 524 | // <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 |
| 525 | |
| 526 | // <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 |
| 527 | |
| 528 | // <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 |
| 529 | |
| 530 | // <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8 |
| 531 | |
| 532 | // <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9 |
| 533 | |
| 534 | // <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10 |
| 535 | |
| 536 | // <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11 |
| 537 | |
| 538 | // <i> Select the clock source for CORE. |
| 539 | #ifndef CONF_GCLK_SERCOM6_CORE_SRC |
| 540 | #define CONF_GCLK_SERCOM6_CORE_SRC GCLK_PCHCTRL_GEN_GCLK2_Val |
| 541 | #endif |
| 542 | |
| 543 | // <y> Slow Clock Source |
| 544 | // <id> slow_gclk_selection |
| 545 | |
| 546 | // <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 |
| 547 | |
| 548 | // <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 |
| 549 | |
| 550 | // <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 |
| 551 | |
| 552 | // <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 |
| 553 | |
| 554 | // <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 |
| 555 | |
| 556 | // <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 |
| 557 | |
| 558 | // <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 |
| 559 | |
| 560 | // <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 |
| 561 | |
| 562 | // <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8 |
| 563 | |
| 564 | // <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9 |
| 565 | |
| 566 | // <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10 |
| 567 | |
| 568 | // <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11 |
| 569 | |
| 570 | // <i> Select the slow clock source. |
| 571 | #ifndef CONF_GCLK_SERCOM6_SLOW_SRC |
| 572 | #define CONF_GCLK_SERCOM6_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val |
| 573 | #endif |
| 574 | |
| 575 | /** |
| 576 | * \def CONF_GCLK_SERCOM6_CORE_FREQUENCY |
| 577 | * \brief SERCOM6's Core Clock frequency |
| 578 | */ |
| 579 | #ifndef CONF_GCLK_SERCOM6_CORE_FREQUENCY |
Kévin Redon | 5e7cfae | 2019-04-25 15:50:30 +0200 | [diff] [blame] | 580 | #define CONF_GCLK_SERCOM6_CORE_FREQUENCY 500000 |
Kévin Redon | 1f8ecef | 2019-01-31 13:36:12 +0100 | [diff] [blame] | 581 | #endif |
| 582 | |
| 583 | /** |
| 584 | * \def CONF_GCLK_SERCOM6_SLOW_FREQUENCY |
| 585 | * \brief SERCOM6's Slow Clock frequency |
| 586 | */ |
| 587 | #ifndef CONF_GCLK_SERCOM6_SLOW_FREQUENCY |
| 588 | #define CONF_GCLK_SERCOM6_SLOW_FREQUENCY 32768 |
| 589 | #endif |
| 590 | |
| 591 | // <y> Core Clock Source |
| 592 | // <id> core_gclk_selection |
| 593 | |
| 594 | // <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 |
| 595 | |
| 596 | // <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 |
| 597 | |
| 598 | // <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 |
| 599 | |
| 600 | // <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 |
| 601 | |
| 602 | // <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 |
| 603 | |
| 604 | // <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 |
| 605 | |
| 606 | // <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 |
| 607 | |
| 608 | // <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 |
| 609 | |
| 610 | // <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8 |
| 611 | |
| 612 | // <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9 |
| 613 | |
| 614 | // <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10 |
| 615 | |
| 616 | // <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11 |
| 617 | |
| 618 | // <i> Select the clock source for CORE. |
Kévin Redon | 4e39b01 | 2019-01-30 15:55:58 +0100 | [diff] [blame] | 619 | #ifndef CONF_GCLK_SERCOM7_CORE_SRC |
Kévin Redon | 37e5fa9 | 2019-04-17 01:09:11 +0200 | [diff] [blame] | 620 | #define CONF_GCLK_SERCOM7_CORE_SRC GCLK_PCHCTRL_GEN_GCLK4_Val |
Kévin Redon | 4cd3f7d | 2019-01-24 17:57:13 +0100 | [diff] [blame] | 621 | #endif |
| 622 | |
| 623 | // <y> Slow Clock Source |
| 624 | // <id> slow_gclk_selection |
| 625 | |
| 626 | // <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 |
| 627 | |
| 628 | // <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 |
| 629 | |
| 630 | // <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 |
| 631 | |
| 632 | // <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 |
| 633 | |
| 634 | // <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 |
| 635 | |
| 636 | // <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 |
| 637 | |
| 638 | // <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 |
| 639 | |
| 640 | // <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 |
| 641 | |
| 642 | // <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8 |
| 643 | |
| 644 | // <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9 |
| 645 | |
| 646 | // <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10 |
| 647 | |
| 648 | // <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11 |
| 649 | |
| 650 | // <i> Select the slow clock source. |
Kévin Redon | 4e39b01 | 2019-01-30 15:55:58 +0100 | [diff] [blame] | 651 | #ifndef CONF_GCLK_SERCOM7_SLOW_SRC |
| 652 | #define CONF_GCLK_SERCOM7_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val |
Kévin Redon | 4cd3f7d | 2019-01-24 17:57:13 +0100 | [diff] [blame] | 653 | #endif |
| 654 | |
| 655 | /** |
Kévin Redon | 4e39b01 | 2019-01-30 15:55:58 +0100 | [diff] [blame] | 656 | * \def CONF_GCLK_SERCOM7_CORE_FREQUENCY |
| 657 | * \brief SERCOM7's Core Clock frequency |
Kévin Redon | 4cd3f7d | 2019-01-24 17:57:13 +0100 | [diff] [blame] | 658 | */ |
Kévin Redon | 4e39b01 | 2019-01-30 15:55:58 +0100 | [diff] [blame] | 659 | #ifndef CONF_GCLK_SERCOM7_CORE_FREQUENCY |
Kévin Redon | f53d366 | 2019-04-25 13:55:06 +0200 | [diff] [blame] | 660 | #define CONF_GCLK_SERCOM7_CORE_FREQUENCY 50000000 |
Kévin Redon | 4cd3f7d | 2019-01-24 17:57:13 +0100 | [diff] [blame] | 661 | #endif |
| 662 | |
| 663 | /** |
Kévin Redon | 4e39b01 | 2019-01-30 15:55:58 +0100 | [diff] [blame] | 664 | * \def CONF_GCLK_SERCOM7_SLOW_FREQUENCY |
| 665 | * \brief SERCOM7's Slow Clock frequency |
Kévin Redon | 4cd3f7d | 2019-01-24 17:57:13 +0100 | [diff] [blame] | 666 | */ |
Kévin Redon | 4e39b01 | 2019-01-30 15:55:58 +0100 | [diff] [blame] | 667 | #ifndef CONF_GCLK_SERCOM7_SLOW_FREQUENCY |
| 668 | #define CONF_GCLK_SERCOM7_SLOW_FREQUENCY 32768 |
Kévin Redon | 4cd3f7d | 2019-01-24 17:57:13 +0100 | [diff] [blame] | 669 | #endif |
| 670 | |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 671 | // <y> USB Clock Source |
| 672 | // <id> usb_gclk_selection |
| 673 | |
| 674 | // <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 |
| 675 | |
| 676 | // <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 |
| 677 | |
| 678 | // <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 |
| 679 | |
| 680 | // <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 |
| 681 | |
| 682 | // <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 |
| 683 | |
| 684 | // <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 |
| 685 | |
| 686 | // <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 |
| 687 | |
| 688 | // <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 |
| 689 | |
| 690 | // <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8 |
| 691 | |
| 692 | // <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9 |
| 693 | |
| 694 | // <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10 |
| 695 | |
| 696 | // <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11 |
| 697 | |
| 698 | // <i> Select the clock source for USB. |
| 699 | #ifndef CONF_GCLK_USB_SRC |
| 700 | #define CONF_GCLK_USB_SRC GCLK_PCHCTRL_GEN_GCLK1_Val |
| 701 | |
| 702 | #endif |
| 703 | |
| 704 | /** |
| 705 | * \def CONF_GCLK_USB_FREQUENCY |
| 706 | * \brief USB's Clock frequency |
| 707 | */ |
| 708 | #ifndef CONF_GCLK_USB_FREQUENCY |
| 709 | #define CONF_GCLK_USB_FREQUENCY 48000000 |
| 710 | #endif |
| 711 | |
| 712 | // <<< end of configuration section >>> |
| 713 | |
| 714 | #endif // PERIPHERAL_CLK_CONFIG_H |