commit 5e7cfaed369ff335b44ebda69e15061a663b5584
author Kévin Redon <kredon@sysmocom.de> Thu Apr 25 15:50:30 2019 +0200
committer Kévin Redon <kredon@sysmocom.de> Thu May 09 15:46:38 2019 +0200
tree 5ca52c94f19a0eec8934bef603eb48c9e2b91a62
parent f53d366c1d3daa0f5ac88af7b8a1ce53a5018a2c

configure GCLK for ISO baud rates

the SERCOMM clock triplet 0.5 MHz (100 MHz / 200),
7.0588 MHz (120 MHz / 17), and 50 MHz (100 MHz / 2) allows to
generate all possible ISO 7816 baud rates (from
F = 2048 / D = 1 @ f = 2.5 MHz -> 1220 bps to
F = 372 / D = 64 @ f = 20 MHz -> 3.4 Mbps) with a maximum baud
rate error of 2.57 %, for available SIM clocks 2.5, 5, 10, 20 MHz.
2.57% means a bit more than quarter a bit might be wrong after the
11 bits ISO transmission (still less than half a bit).
This triplet is one of the optimum when 3 clocks are used.
An additional clock would be required for higher accuracy.

The 50 MHz clock is re-used from the RMII clock output.

Change-Id: I2c69848582e49031fa6453f535a2bf1408f8e22e

sysmoOCTSIM/config/peripheral_clk_config.h

diff --git a/sysmoOCTSIM/config/peripheral_clk_config.h b/sysmoOCTSIM/config/peripheral_clk_config.h
index 2ae1f63..f794792 100644
--- a/sysmoOCTSIM/config/peripheral_clk_config.h
+++ b/sysmoOCTSIM/config/peripheral_clk_config.h
@@ -81,7 +81,7 @@
  * \brief SERCOM0's Core Clock frequency
  */
 #ifndef CONF_GCLK_SERCOM0_CORE_FREQUENCY
-#define CONF_GCLK_SERCOM0_CORE_FREQUENCY 3333333
+#define CONF_GCLK_SERCOM0_CORE_FREQUENCY 500000
 #endif
 
 /**
@@ -161,7 +161,7 @@
  * \brief SERCOM1's Core Clock frequency
  */
 #ifndef CONF_GCLK_SERCOM1_CORE_FREQUENCY
-#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 3333333
+#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 500000
 #endif
 
 /**
@@ -241,7 +241,7 @@
  * \brief SERCOM2's Core Clock frequency
  */
 #ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY
-#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 3333333
+#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 500000
 #endif
 
 /**
@@ -321,7 +321,7 @@
  * \brief SERCOM3's Core Clock frequency
  */
 #ifndef CONF_GCLK_SERCOM3_CORE_FREQUENCY
-#define CONF_GCLK_SERCOM3_CORE_FREQUENCY 3333333
+#define CONF_GCLK_SERCOM3_CORE_FREQUENCY 500000
 #endif
 
 /**
@@ -401,7 +401,7 @@
  * \brief SERCOM4's Core Clock frequency
  */
 #ifndef CONF_GCLK_SERCOM4_CORE_FREQUENCY
-#define CONF_GCLK_SERCOM4_CORE_FREQUENCY 3333333
+#define CONF_GCLK_SERCOM4_CORE_FREQUENCY 500000
 #endif
 
 /**
@@ -481,7 +481,7 @@
  * \brief SERCOM5's Core Clock frequency
  */
 #ifndef CONF_GCLK_SERCOM5_CORE_FREQUENCY
-#define CONF_GCLK_SERCOM5_CORE_FREQUENCY 3333333
+#define CONF_GCLK_SERCOM5_CORE_FREQUENCY 500000
 #endif
 
 /**
@@ -561,7 +561,7 @@
  * \brief SERCOM6's Core Clock frequency
  */
 #ifndef CONF_GCLK_SERCOM6_CORE_FREQUENCY
-#define CONF_GCLK_SERCOM6_CORE_FREQUENCY 3333333
+#define CONF_GCLK_SERCOM6_CORE_FREQUENCY 500000
 #endif
 
 /**