commit 37e5fa913b7059be400cda5094d372054c332705
author Kévin Redon <kredon@sysmocom.de> Wed Apr 17 01:09:11 2019 +0200
committer Harald Welte <laforge@gnumonks.org> Wed Apr 17 11:52:00 2019 +0200
tree f6527466cec5e68d9d1a89edc988d1a89237acdf
parent ee4912966b4654c8d7a56f0a7e5e5a073ef4791d

change SERCOM clock to 3.3 MHz

we use the SERCOM peripheral for USART (in 7816 mode SIM card
communication) in synchronous mode (TX and RX clock are the same).
in this mode only the 8 least significant bits of the BAUD register
are used (see TRM 33.6.2.3 Clock Generation – Baud-Rate Generator).
When the SERCOM is clocked at 100 MHz the minimum resulting baud
rate would be 100E6 / (2 * 255 + 1) = 195694 bps.
clocking SERCOM at 3.33 MHz also to have a baud rate of 6720 bps
(~ 3.33E6 / (2 * 247 + 1)), used after reset to read the ATR.

Change-Id: Id60322e092a6652a89821fc737d5336d79a1420c

sysmoOCTSIM/config/peripheral_clk_config.h

diff --git a/sysmoOCTSIM/config/peripheral_clk_config.h b/sysmoOCTSIM/config/peripheral_clk_config.h
index 91c5c86..4bff6ff 100644
--- a/sysmoOCTSIM/config/peripheral_clk_config.h
+++ b/sysmoOCTSIM/config/peripheral_clk_config.h
@@ -81,7 +81,7 @@
  * \brief SERCOM0's Core Clock frequency
  */
 #ifndef CONF_GCLK_SERCOM0_CORE_FREQUENCY
-#define CONF_GCLK_SERCOM0_CORE_FREQUENCY 100000000
+#define CONF_GCLK_SERCOM0_CORE_FREQUENCY 3333333
 #endif
 
 /**
@@ -161,7 +161,7 @@
  * \brief SERCOM1's Core Clock frequency
  */
 #ifndef CONF_GCLK_SERCOM1_CORE_FREQUENCY
-#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 100000000
+#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 3333333
 #endif
 
 /**
@@ -241,7 +241,7 @@
  * \brief SERCOM2's Core Clock frequency
  */
 #ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY
-#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 100000000
+#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 3333333
 #endif
 
 /**
@@ -321,7 +321,7 @@
  * \brief SERCOM3's Core Clock frequency
  */
 #ifndef CONF_GCLK_SERCOM3_CORE_FREQUENCY
-#define CONF_GCLK_SERCOM3_CORE_FREQUENCY 100000000
+#define CONF_GCLK_SERCOM3_CORE_FREQUENCY 3333333
 #endif
 
 /**
@@ -401,7 +401,7 @@
  * \brief SERCOM4's Core Clock frequency
  */
 #ifndef CONF_GCLK_SERCOM4_CORE_FREQUENCY
-#define CONF_GCLK_SERCOM4_CORE_FREQUENCY 100000000
+#define CONF_GCLK_SERCOM4_CORE_FREQUENCY 3333333
 #endif
 
 /**
@@ -481,7 +481,7 @@
  * \brief SERCOM5's Core Clock frequency
  */
 #ifndef CONF_GCLK_SERCOM5_CORE_FREQUENCY
-#define CONF_GCLK_SERCOM5_CORE_FREQUENCY 100000000
+#define CONF_GCLK_SERCOM5_CORE_FREQUENCY 3333333
 #endif
 
 /**
@@ -561,7 +561,7 @@
  * \brief SERCOM6's Core Clock frequency
  */
 #ifndef CONF_GCLK_SERCOM6_CORE_FREQUENCY
-#define CONF_GCLK_SERCOM6_CORE_FREQUENCY 100000000
+#define CONF_GCLK_SERCOM6_CORE_FREQUENCY 3333333
 #endif
 
 /**
@@ -601,7 +601,7 @@
 
 // <i> Select the clock source for CORE.
 #ifndef CONF_GCLK_SERCOM7_CORE_SRC
-#define CONF_GCLK_SERCOM7_CORE_SRC GCLK_PCHCTRL_GEN_GCLK2_Val
+#define CONF_GCLK_SERCOM7_CORE_SRC GCLK_PCHCTRL_GEN_GCLK4_Val
 #endif
 
 // <y> Slow Clock Source