1. 293c841 fix DPLL input clock division by Kévin Redon · 5 years ago
  2. 4cb8e32 use XOSC1 directly for DPLL1 by Kévin Redon · 5 years ago
  3. 20abc4f set DPLL1 to 100 MHz by Kévin Redon · 5 years ago
  4. 6b9363c remove usage of GCLK11 by Kévin Redon · 5 years ago
  5. 4a2d8f4 switch CPU clock to 120 MHz by Kévin Redon · 5 years ago
  6. 69b92d9 start with USB CDC echo example by Kévin Redon · 5 years ago