Sylvain Munaut | 546493e | 2020-09-14 10:12:56 +0200 | [diff] [blame] | 1 | /* |
| 2 | * misc.v |
| 3 | * |
| 4 | * vim: ts=4 sw=4 |
| 5 | * |
| 6 | * Misc peripheral functions |
| 7 | * |
| 8 | * Copyright (C) 2019-2020 Sylvain Munaut <tnt@246tNt.com> |
| 9 | * SPDX-License-Identifier: CERN-OHL-S-2.0 |
| 10 | */ |
| 11 | |
| 12 | `default_nettype none |
| 13 | |
| 14 | module misc ( |
| 15 | // Button |
| 16 | input wire btn, |
| 17 | |
| 18 | // Ticks |
Sylvain Munaut | 60f664f | 2024-04-29 16:14:54 +0200 | [diff] [blame] | 19 | input wire [7:0] tick_e1, |
Sylvain Munaut | 546493e | 2020-09-14 10:12:56 +0200 | [diff] [blame] | 20 | input wire tick_usb_sof, |
| 21 | |
| 22 | // Reset request |
| 23 | output wire rst_req, |
| 24 | |
| 25 | // Wishbone |
| 26 | input wire [ 7:0] wb_addr, |
| 27 | output reg [31:0] wb_rdata, |
| 28 | input wire [31:0] wb_wdata, |
| 29 | input wire wb_we, |
| 30 | input wire wb_cyc, |
| 31 | output reg wb_ack, |
| 32 | |
| 33 | // Clock / Reset |
| 34 | input wire clk, |
| 35 | input wire rst |
| 36 | ); |
| 37 | |
| 38 | // Signals |
| 39 | // ------- |
| 40 | |
| 41 | genvar i; |
| 42 | |
| 43 | // Bus |
| 44 | wire bus_clr; |
| 45 | reg bus_we_boot; |
Sylvain Munaut | 60f664f | 2024-04-29 16:14:54 +0200 | [diff] [blame] | 46 | reg bus_we_tick_sel; |
Sylvain Munaut | 546493e | 2020-09-14 10:12:56 +0200 | [diff] [blame] | 47 | |
| 48 | // Counters |
Sylvain Munaut | 60f664f | 2024-04-29 16:14:54 +0200 | [diff] [blame] | 49 | reg [1:0] tick_e1_sel[0:1]; |
| 50 | wire [1:0] tick_e1_mux; |
| 51 | |
| 52 | wire [15:0] cap_e1[0:1]; |
Sylvain Munaut | ff0ab3e | 2020-10-03 20:15:28 +0200 | [diff] [blame] | 53 | wire [31:0] cnt_time; |
Sylvain Munaut | 546493e | 2020-09-14 10:12:56 +0200 | [diff] [blame] | 54 | |
| 55 | // Boot |
| 56 | reg [1:0] boot_sel; |
| 57 | reg boot_now; |
| 58 | |
| 59 | |
| 60 | // Bus interface |
| 61 | // ------------- |
| 62 | |
| 63 | // Ack |
| 64 | always @(posedge clk) |
| 65 | wb_ack <= wb_cyc & ~wb_ack; |
| 66 | |
| 67 | assign bus_clr = ~wb_cyc | wb_ack; |
| 68 | |
| 69 | // Write enables |
| 70 | always @(posedge clk) |
Sylvain Munaut | 60f664f | 2024-04-29 16:14:54 +0200 | [diff] [blame] | 71 | if (bus_clr | ~wb_we) begin |
| 72 | bus_we_boot <= 1'b0; |
| 73 | bus_we_tick_sel <= 1'b0; |
| 74 | end else begin |
| 75 | bus_we_boot <= wb_addr == 4'h0; |
| 76 | bus_we_tick_sel <= wb_addr == 4'h4; |
| 77 | end |
Sylvain Munaut | 546493e | 2020-09-14 10:12:56 +0200 | [diff] [blame] | 78 | |
| 79 | // Read mux |
| 80 | always @(posedge clk) |
| 81 | if (bus_clr) |
| 82 | wb_rdata <= 32'h00000000; |
| 83 | else |
| 84 | case (wb_addr[3:0]) |
Sylvain Munaut | 60f664f | 2024-04-29 16:14:54 +0200 | [diff] [blame] | 85 | 4'h4: wb_rdata <= { cap_e1[1], cap_e1[0] }; |
Sylvain Munaut | 546493e | 2020-09-14 10:12:56 +0200 | [diff] [blame] | 86 | 4'h7: wb_rdata <= cnt_time; |
| 87 | default: wb_rdata <= 32'hxxxxxxxx; |
| 88 | endcase |
| 89 | |
| 90 | |
| 91 | // Counters |
| 92 | // -------- |
| 93 | |
| 94 | // E1 ticks |
Sylvain Munaut | 60f664f | 2024-04-29 16:14:54 +0200 | [diff] [blame] | 95 | always @(posedge clk) |
| 96 | if (bus_we_tick_sel) begin |
| 97 | tick_e1_sel[1] <= wb_wdata[17:16]; |
| 98 | tick_e1_sel[0] <= wb_wdata[ 1: 0]; |
| 99 | end |
| 100 | |
| 101 | assign tick_e1_mux[0] = tick_e1[{1'b0, tick_e1_sel[0]}]; |
| 102 | assign tick_e1_mux[1] = tick_e1[{1'b1, tick_e1_sel[1]}]; |
| 103 | |
Sylvain Munaut | ff0ab3e | 2020-10-03 20:15:28 +0200 | [diff] [blame] | 104 | capcnt #( |
| 105 | .W(16) |
| 106 | ) e1_cnt_I[1:0] ( |
| 107 | .cnt_cur (), |
Sylvain Munaut | 60f664f | 2024-04-29 16:14:54 +0200 | [diff] [blame] | 108 | .cnt_cap ({ cap_e1[1], cap_e1[0] }), |
| 109 | .inc ({ tick_e1_mux[1], tick_e1_mux[0] }), |
Sylvain Munaut | ff0ab3e | 2020-10-03 20:15:28 +0200 | [diff] [blame] | 110 | .cap (tick_usb_sof), |
| 111 | .clk (clk), |
| 112 | .rst (rst) |
| 113 | ); |
Sylvain Munaut | 546493e | 2020-09-14 10:12:56 +0200 | [diff] [blame] | 114 | |
Sylvain Munaut | ff0ab3e | 2020-10-03 20:15:28 +0200 | [diff] [blame] | 115 | // Time |
| 116 | capcnt #( |
| 117 | .W(32) |
| 118 | ) time_cnt_I ( |
| 119 | .cnt_cur (cnt_time), |
| 120 | .cnt_cap (), |
| 121 | .inc (1'b1), |
| 122 | .cap (1'b0), |
| 123 | .clk (clk), |
| 124 | .rst (rst) |
| 125 | ); |
Sylvain Munaut | 546493e | 2020-09-14 10:12:56 +0200 | [diff] [blame] | 126 | |
| 127 | |
| 128 | // DFU / Reboot |
| 129 | // ------------ |
| 130 | |
| 131 | always @(posedge clk or posedge rst) |
| 132 | if (rst) begin |
| 133 | boot_now <= 1'b0; |
| 134 | boot_sel <= 2'b00; |
| 135 | end else if (bus_we_boot) begin |
| 136 | boot_now <= wb_wdata[2]; |
| 137 | boot_sel <= wb_wdata[1:0]; |
| 138 | end |
| 139 | |
| 140 | dfu_helper #( |
| 141 | .TIMER_WIDTH(26), |
| 142 | .BTN_MODE(3), |
| 143 | .DFU_MODE(0) |
| 144 | ) dfu_I ( |
| 145 | .boot_sel(boot_sel), |
| 146 | .boot_now(boot_now), |
| 147 | .btn_pad (btn), |
| 148 | .btn_val (), |
| 149 | .rst_req (rst_req), |
| 150 | .clk (clk), |
| 151 | .rst (rst) |
| 152 | ); |
| 153 | |
| 154 | endmodule // misc |