gateware: Rework the low-level line state monitoring ticks
The 'tick' system was meant to allow the firmware to monitor the
low level state of the line, beyong just "not aligned", but it was
never really useful in the present state.
Now we have more tick source available (but only one can be measured
at the same time). More specifically, the firmware can monitor the
presence/absence of raw pulses (LOS condition), it can also monitor
the number of '1' pulses to detect an AIS signals, or simply the rate
of RX pulses (to tune the local oscillator to incoming signal rate).
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
Change-Id: I31fa8a717a26643f1b6ca5644bee1d8c41a2512e
diff --git a/gateware/e1-tracer/rtl/misc.v b/gateware/e1-tracer/rtl/misc.v
index e39a787..5d1c1f4 100644
--- a/gateware/e1-tracer/rtl/misc.v
+++ b/gateware/e1-tracer/rtl/misc.v
@@ -16,7 +16,7 @@
input wire btn,
// Ticks
- input wire [1:0] tick_e1_rx,
+ input wire [7:0] tick_e1,
input wire tick_usb_sof,
// Reset request
@@ -43,9 +43,13 @@
// Bus
wire bus_clr;
reg bus_we_boot;
+ reg bus_we_tick_sel;
// Counters
- wire [15:0] cap_e1_rx[0:1];
+ reg [1:0] tick_e1_sel[0:1];
+ wire [1:0] tick_e1_mux;
+
+ wire [15:0] cap_e1[0:1];
wire [31:0] cnt_time;
// Boot
@@ -64,10 +68,13 @@
// Write enables
always @(posedge clk)
- if (bus_clr | ~wb_we)
- bus_we_boot <= 1'b0;
- else
- bus_we_boot <= wb_addr == 4'h0;
+ if (bus_clr | ~wb_we) begin
+ bus_we_boot <= 1'b0;
+ bus_we_tick_sel <= 1'b0;
+ end else begin
+ bus_we_boot <= wb_addr == 4'h0;
+ bus_we_tick_sel <= wb_addr == 4'h4;
+ end
// Read mux
always @(posedge clk)
@@ -75,8 +82,7 @@
wb_rdata <= 32'h00000000;
else
case (wb_addr[3:0])
- 4'h4: wb_rdata <= { 16'h000, cap_e1_rx[0] };
- 4'h5: wb_rdata <= { 16'h000, cap_e1_rx[1] };
+ 4'h4: wb_rdata <= { cap_e1[1], cap_e1[0] };
4'h7: wb_rdata <= cnt_time;
default: wb_rdata <= 32'hxxxxxxxx;
endcase
@@ -86,12 +92,21 @@
// --------
// E1 ticks
+ always @(posedge clk)
+ if (bus_we_tick_sel) begin
+ tick_e1_sel[1] <= wb_wdata[17:16];
+ tick_e1_sel[0] <= wb_wdata[ 1: 0];
+ end
+
+ assign tick_e1_mux[0] = tick_e1[{1'b0, tick_e1_sel[0]}];
+ assign tick_e1_mux[1] = tick_e1[{1'b1, tick_e1_sel[1]}];
+
capcnt #(
.W(16)
) e1_cnt_I[1:0] (
.cnt_cur (),
- .cnt_cap ({cap_e1_rx[1], cap_e1_rx[0] }),
- .inc ({tick_e1_rx[1], tick_e1_rx[0]}),
+ .cnt_cap ({ cap_e1[1], cap_e1[0] }),
+ .inc ({ tick_e1_mux[1], tick_e1_mux[0] }),
.cap (tick_usb_sof),
.clk (clk),
.rst (rst)