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Sylvain Munaut546493e2020-09-14 10:12:56 +02001/*
2 * misc.v
3 *
4 * vim: ts=4 sw=4
5 *
6 * Misc peripheral functions
7 *
8 * Copyright (C) 2019-2020 Sylvain Munaut <tnt@246tNt.com>
9 * SPDX-License-Identifier: CERN-OHL-S-2.0
10 */
11
12`default_nettype none
13
14module misc (
15 // Button
16 input wire btn,
17
18 // Ticks
19 input wire [1:0] tick_e1_rx,
20 input wire tick_usb_sof,
21
22 // Reset request
23 output wire rst_req,
24
25 // Wishbone
26 input wire [ 7:0] wb_addr,
27 output reg [31:0] wb_rdata,
28 input wire [31:0] wb_wdata,
29 input wire wb_we,
30 input wire wb_cyc,
31 output reg wb_ack,
32
33 // Clock / Reset
34 input wire clk,
35 input wire rst
36);
37
38 // Signals
39 // -------
40
41 genvar i;
42
43 // Bus
44 wire bus_clr;
45 reg bus_we_boot;
46
47 // Counters
Sylvain Munautff0ab3e2020-10-03 20:15:28 +020048 wire [15:0] cap_e1_rx[0:1];
49 wire [31:0] cnt_time;
Sylvain Munaut546493e2020-09-14 10:12:56 +020050
51 // Boot
52 reg [1:0] boot_sel;
53 reg boot_now;
54
55
56 // Bus interface
57 // -------------
58
59 // Ack
60 always @(posedge clk)
61 wb_ack <= wb_cyc & ~wb_ack;
62
63 assign bus_clr = ~wb_cyc | wb_ack;
64
65 // Write enables
66 always @(posedge clk)
67 if (bus_clr | ~wb_we)
68 bus_we_boot <= 1'b0;
69 else
70 bus_we_boot <= wb_addr == 4'h0;
71
72 // Read mux
73 always @(posedge clk)
74 if (bus_clr)
75 wb_rdata <= 32'h00000000;
76 else
77 case (wb_addr[3:0])
Sylvain Munautc1d117b2020-09-15 21:57:52 +020078 4'h4: wb_rdata <= { 16'h000, cap_e1_rx[0] };
79 4'h5: wb_rdata <= { 16'h000, cap_e1_rx[1] };
Sylvain Munaut546493e2020-09-14 10:12:56 +020080 4'h7: wb_rdata <= cnt_time;
81 default: wb_rdata <= 32'hxxxxxxxx;
82 endcase
83
84
85 // Counters
86 // --------
87
88 // E1 ticks
Sylvain Munautff0ab3e2020-10-03 20:15:28 +020089 capcnt #(
90 .W(16)
91 ) e1_cnt_I[1:0] (
92 .cnt_cur (),
93 .cnt_cap ({cap_e1_rx[1], cap_e1_rx[0] }),
94 .inc ({tick_e1_rx[1], tick_e1_rx[0]}),
95 .cap (tick_usb_sof),
96 .clk (clk),
97 .rst (rst)
98 );
Sylvain Munaut546493e2020-09-14 10:12:56 +020099
Sylvain Munautff0ab3e2020-10-03 20:15:28 +0200100 // Time
101 capcnt #(
102 .W(32)
103 ) time_cnt_I (
104 .cnt_cur (cnt_time),
105 .cnt_cap (),
106 .inc (1'b1),
107 .cap (1'b0),
108 .clk (clk),
109 .rst (rst)
110 );
Sylvain Munaut546493e2020-09-14 10:12:56 +0200111
112
113 // DFU / Reboot
114 // ------------
115
116 always @(posedge clk or posedge rst)
117 if (rst) begin
118 boot_now <= 1'b0;
119 boot_sel <= 2'b00;
120 end else if (bus_we_boot) begin
121 boot_now <= wb_wdata[2];
122 boot_sel <= wb_wdata[1:0];
123 end
124
125 dfu_helper #(
126 .TIMER_WIDTH(26),
127 .BTN_MODE(3),
128 .DFU_MODE(0)
129 ) dfu_I (
130 .boot_sel(boot_sel),
131 .boot_now(boot_now),
132 .btn_pad (btn),
133 .btn_val (),
134 .rst_req (rst_req),
135 .clk (clk),
136 .rst (rst)
137 );
138
139endmodule // misc