Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 1 | /* ----------------------------------------------------------------------------
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| 2 | * ATMEL Microcontroller Software Support
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| 3 | * ----------------------------------------------------------------------------
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| 4 | * Copyright (c) 2009, Atmel Corporation
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| 5 | *
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| 6 | * All rights reserved.
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| 7 | *
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| 8 | * Redistribution and use in source and binary forms, with or without
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| 9 | * modification, are permitted provided that the following conditions are met:
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| 10 | *
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| 11 | * - Redistributions of source code must retain the above copyright notice,
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| 12 | * this list of conditions and the disclaimer below.
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| 13 | *
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| 14 | * Atmel's name may not be used to endorse or promote products derived from
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| 15 | * this software without specific prior written permission.
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| 16 | *
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| 17 | * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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| 19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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| 20 | * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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| 22 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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| 23 | * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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| 24 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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| 25 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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| 26 | * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | * ----------------------------------------------------------------------------
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| 28 | */
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| 29 |
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| 30 | /**
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| 31 | * \file
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| 32 | *
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| 33 | * Provides the low-level initialization function that called on chip startup.
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| 34 | */
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| 35 |
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| 36 | /*----------------------------------------------------------------------------
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| 37 | * Headers
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| 38 | *----------------------------------------------------------------------------*/
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| 39 |
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| 40 | #include "board.h"
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 41 |
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| 42 | /*----------------------------------------------------------------------------
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| 43 | * Local definitions
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| 44 | *----------------------------------------------------------------------------*/
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| 45 |
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 46 | #define BOARD_OSCOUNT (CKGR_MOR_MOSCXTST(0x8))
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Christina Quast | 530f208 | 2014-12-05 13:03:59 +0100 | [diff] [blame] | 47 | #define BOARD_MCKR (PMC_MCKR_PRES_CLK | PMC_MCKR_CSS_PLLA_CLK)
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Harald Welte | fb3f308 | 2017-01-12 18:16:23 +0100 | [diff] [blame] | 48 |
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| 49 | #if (BOARD_MCK == 48000000)
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| 50 | #if (BOARD_MAINOSC == 18432000)
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| 51 | /* Clock settings at 48MHz for 18 MHz crystal */
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| 52 | #define BOARD_PLLAR (CKGR_PLLAR_STUCKTO1 \
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| 53 | | CKGR_PLLAR_MULA(13-1) \
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| 54 | | CKGR_PLLAR_PLLACOUNT(0x1) \
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| 55 | | CKGR_PLLAR_DIVA(5))
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| 56 | #elif (BOARD_MAINOSC == 12000000)
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Harald Welte | 7861132 | 2017-01-12 11:07:04 +0100 | [diff] [blame] | 57 | /* QMod has 12 MHz clock, so multply by 8 (96 MHz) and divide by 2 */
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Harald Welte | a02b641 | 2016-08-21 18:32:12 +0200 | [diff] [blame] | 58 | #define BOARD_PLLAR (CKGR_PLLAR_STUCKTO1 \
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Harald Welte | 7861132 | 2017-01-12 11:07:04 +0100 | [diff] [blame] | 59 | | CKGR_PLLAR_MULA(8-1) \
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Harald Welte | a02b641 | 2016-08-21 18:32:12 +0200 | [diff] [blame] | 60 | | CKGR_PLLAR_PLLACOUNT(0x1) \
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Harald Welte | 7861132 | 2017-01-12 11:07:04 +0100 | [diff] [blame] | 61 | | CKGR_PLLAR_DIVA(2))
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 62 | #else
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Harald Welte | fb3f308 | 2017-01-12 18:16:23 +0100 | [diff] [blame] | 63 | #error "Please define PLLA config for your MAINOSC frequency"
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| 64 | #endif /* MAINOSC */
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| 65 | #elif (BOARD_MCK == 64000000)
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| 66 | #if (BOARD_MAINOSC == 18432000)
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| 67 | /* Clock settings at 64MHz for 18 MHz crystal: 64.512 MHz */
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| 68 | #define BOARD_PLLAR (CKGR_PLLAR_STUCKTO1 \
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| 69 | | CKGR_PLLAR_MULA(7-1) \
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| 70 | | CKGR_PLLAR_PLLACOUNT(0x1) \
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| 71 | | CKGR_PLLAR_DIVA(2))
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| 72 | #elif (BOARD_MAINOSC == 12000000)
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| 73 | /* QMod has 12 MHz clock, so multply by 10 / div by 2: 60 MHz */
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| 74 | #define BOARD_PLLAR (CKGR_PLLAR_STUCKTO1 \
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| 75 | | CKGR_PLLAR_MULA(10-1) \
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| 76 | | CKGR_PLLAR_PLLACOUNT(0x1) \
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| 77 | | CKGR_PLLAR_DIVA(2))
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| 78 | #error "Please define PLLA config for your MAINOSC frequency"
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| 79 | #endif /* MAINOSC */
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| 80 | #else
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| 81 | #error "No PLL settings for current BOARD_MCK."
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 82 | #endif
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| 83 |
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Harald Welte | 0395bd1 | 2017-02-28 01:28:56 +0100 | [diff] [blame] | 84 | #if (BOARD_MAINOSC == 12000000)
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| 85 | #define PLLB_CFG (CKGR_PLLBR_DIVB(2)|CKGR_PLLBR_MULB(8-1)|CKGR_PLLBR_PLLBCOUNT_Msk)
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| 86 | #elif (BOARD_MAINOSC == 18432000)
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| 87 | #define PLLB_CFG (CKGR_PLLBR_DIVB(5)|CKGR_PLLBR_MULB(13-1)|CKGR_PLLBR_PLLBCOUNT_Msk)
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| 88 | #else
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| 89 | #error "Please configure PLLB for your MAINOSC freq"
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| 90 | #endif
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| 91 |
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 92 | /* Define clock timeout */
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| 93 | #define CLOCK_TIMEOUT 0xFFFFFFFF
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| 94 |
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Harald Welte | 0395bd1 | 2017-02-28 01:28:56 +0100 | [diff] [blame] | 95 | /**
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| 96 | * \brief Configure 48MHz Clock for USB
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| 97 | */
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| 98 | static void _ConfigureUsbClock(void)
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| 99 | {
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| 100 | /* Enable PLLB for USB */
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| 101 | PMC->CKGR_PLLBR = PLLB_CFG;
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| 102 | while ((PMC->PMC_SR & PMC_SR_LOCKB) == 0) ;
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| 103 |
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| 104 | /* USB Clock uses PLLB */
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| 105 | PMC->PMC_USB = PMC_USB_USBDIV(0) /* /1 (no divider) */
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| 106 | | PMC_USB_USBS; /* PLLB */
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| 107 | }
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| 108 |
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 109 | /*----------------------------------------------------------------------------
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| 110 | * Exported functions
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| 111 | *----------------------------------------------------------------------------*/
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| 112 |
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| 113 | /**
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| 114 | * \brief Performs the low-level initialization of the chip.
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| 115 | * This includes EFC and master clock configuration.
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| 116 | * It also enable a low level on the pin NRST triggers a user reset.
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| 117 | */
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Christina Quast | 8be71e4 | 2014-12-02 13:06:01 +0100 | [diff] [blame] | 118 | extern WEAK void LowLevelInit( void )
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 119 | {
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| 120 | uint32_t timeout = 0;
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| 121 |
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Harald Welte | aaba4af | 2017-03-03 18:48:13 +0100 | [diff] [blame] | 122 | /* Configure the Supply Monitor to reset the CPU in case VDDIO is
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| 123 | * lower than 3.0V. As we run the board on 3.3V, any lower voltage
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| 124 | * might be some kind of leakage that creeps in some way, but is not
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| 125 | * the "official" power supply */
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| 126 | SUPC->SUPC_SMMR = SUPC_SMMR_SMTH_3_0V | SUPC_SMMR_SMSMPL_CSM |
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| 127 | SUPC_SMMR_SMRSTEN_ENABLE;
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| 128 |
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Harald Welte | 372f4cc | 2016-03-16 22:17:39 +0100 | [diff] [blame] | 129 | /* enable both LED and green LED */
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Harald Welte | abba8a8 | 2017-03-06 16:58:00 +0100 | [diff] [blame] | 130 | PIOA->PIO_PER |= PIO_LED_RED | PIO_LED_GREEN;
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| 131 | PIOA->PIO_OER |= PIO_LED_RED | PIO_LED_GREEN;
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| 132 | PIOA->PIO_CODR |= PIO_LED_RED | PIO_LED_GREEN;
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Harald Welte | 7abdb51 | 2016-03-03 17:48:32 +0100 | [diff] [blame] | 133 |
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 134 | /* Set 3 FWS for Embedded Flash Access */
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| 135 | EFC->EEFC_FMR = EEFC_FMR_FWS(3);
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| 136 |
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| 137 | /* Select external slow clock */
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Christina Quast | 8be71e4 | 2014-12-02 13:06:01 +0100 | [diff] [blame] | 138 | /* if ((SUPC->SUPC_SR & SUPC_SR_OSCSEL) != SUPC_SR_OSCSEL_CRYST)
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 139 | {
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| 140 | SUPC->SUPC_CR = (uint32_t)(SUPC_CR_XTALSEL_CRYSTAL_SEL | SUPC_CR_KEY(0xA5));
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| 141 | timeout = 0;
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| 142 | while (!(SUPC->SUPC_SR & SUPC_SR_OSCSEL_CRYST) );
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| 143 | }
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Christina Quast | 8be71e4 | 2014-12-02 13:06:01 +0100 | [diff] [blame] | 144 | */
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 145 |
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Harald Welte | a02b641 | 2016-08-21 18:32:12 +0200 | [diff] [blame] | 146 | #ifndef qmod
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 147 | /* Initialize main oscillator */
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Harald Welte | 5e00400 | 2016-03-16 20:40:19 +0100 | [diff] [blame] | 148 | if ( !(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) )
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 149 | {
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| 150 | PMC->CKGR_MOR = CKGR_MOR_KEY(0x37) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;
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| 151 | timeout = 0;
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| 152 | while (!(PMC->PMC_SR & PMC_SR_MOSCXTS) && (timeout++ < CLOCK_TIMEOUT));
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Harald Welte | 5e00400 | 2016-03-16 20:40:19 +0100 | [diff] [blame] | 153 | }
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 154 |
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| 155 | /* Switch to 3-20MHz Xtal oscillator */
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Harald Welte | 5e00400 | 2016-03-16 20:40:19 +0100 | [diff] [blame] | 156 | PIOB->PIO_PDR = (1 << 8) | (1 << 9);
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| 157 | PIOB->PIO_PUDR = (1 << 8) | (1 << 9);
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| 158 | PIOB->PIO_PPDDR = (1 << 8) | (1 << 9);
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 159 | PMC->CKGR_MOR = CKGR_MOR_KEY(0x37) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;
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Harald Welte | 4678388 | 2016-02-29 19:45:59 +0100 | [diff] [blame] | 160 | /* wait for Main XTAL oscillator stabilization */
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 161 | timeout = 0;
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| 162 | while (!(PMC->PMC_SR & PMC_SR_MOSCSELS) && (timeout++ < CLOCK_TIMEOUT));
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Harald Welte | a02b641 | 2016-08-21 18:32:12 +0200 | [diff] [blame] | 163 | #else
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| 164 | /* QMOD has external 12MHz clock source */
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| 165 | PIOB->PIO_PDR = (1 << 9);
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| 166 | PIOB->PIO_PUDR = (1 << 9);
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| 167 | PIOB->PIO_PPDDR = (1 << 9);
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| 168 | PMC->CKGR_MOR = CKGR_MOR_KEY(0x37) | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTBY| CKGR_MOR_MOSCSEL;
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| 169 | #endif
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Harald Welte | 4678388 | 2016-02-29 19:45:59 +0100 | [diff] [blame] | 170 |
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Harald Welte | 372f4cc | 2016-03-16 22:17:39 +0100 | [diff] [blame] | 171 | /* disable the red LED after main clock initialization */
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Harald Welte | abba8a8 | 2017-03-06 16:58:00 +0100 | [diff] [blame] | 172 | PIOA->PIO_SODR = PIO_LED_RED;
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Harald Welte | 7abdb51 | 2016-03-03 17:48:32 +0100 | [diff] [blame] | 173 |
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Harald Welte | 4678388 | 2016-02-29 19:45:59 +0100 | [diff] [blame] | 174 | /* "switch" to main clock as master clock source (should already be the case */
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 175 | PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
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Harald Welte | 4678388 | 2016-02-29 19:45:59 +0100 | [diff] [blame] | 176 | /* wait for master clock to be ready */
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 177 | for ( timeout = 0; !(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT) ; );
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| 178 |
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| 179 | /* Initialize PLLA */
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| 180 | PMC->CKGR_PLLAR = BOARD_PLLAR;
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Harald Welte | 4678388 | 2016-02-29 19:45:59 +0100 | [diff] [blame] | 181 | /* Wait for PLLA to lock */
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 182 | timeout = 0;
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| 183 | while (!(PMC->PMC_SR & PMC_SR_LOCKA) && (timeout++ < CLOCK_TIMEOUT));
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| 184 |
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Harald Welte | 4678388 | 2016-02-29 19:45:59 +0100 | [diff] [blame] | 185 | /* Switch to main clock (again ?!?) */
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 186 | PMC->PMC_MCKR = (BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
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Harald Welte | 4678388 | 2016-02-29 19:45:59 +0100 | [diff] [blame] | 187 | /* wait for master clock to be ready */
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 188 | for ( timeout = 0; !(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT) ; );
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| 189 |
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Harald Welte | 4678388 | 2016-02-29 19:45:59 +0100 | [diff] [blame] | 190 | /* switch to PLLA as master clock source */
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 191 | PMC->PMC_MCKR = BOARD_MCKR ;
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Harald Welte | 4678388 | 2016-02-29 19:45:59 +0100 | [diff] [blame] | 192 | /* wait for master clock to be ready */
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 193 | for ( timeout = 0; !(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT) ; );
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Harald Welte | 83207e0 | 2017-02-03 22:16:47 +0100 | [diff] [blame] | 194 |
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| 195 | /* Configure SysTick for 1ms */
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| 196 | SysTick_Config(BOARD_MCK/1000);
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Harald Welte | 0395bd1 | 2017-02-28 01:28:56 +0100 | [diff] [blame] | 197 |
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| 198 | _ConfigureUsbClock();
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Harald Welte | 83207e0 | 2017-02-03 22:16:47 +0100 | [diff] [blame] | 199 | }
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| 200 |
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| 201 | /* SysTick based delay function */
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| 202 |
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| 203 | volatile uint32_t jiffies;
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| 204 |
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| 205 | /* Interrupt handler for SysTick interrupt */
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| 206 | void SysTick_Handler(void)
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| 207 | {
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| 208 | jiffies++;
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| 209 | }
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| 210 |
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| 211 | void mdelay(unsigned int msecs)
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| 212 | {
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| 213 | uint32_t jiffies_start = jiffies;
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| 214 | do {
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| 215 | } while ((jiffies - jiffies_start) < msecs);
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 216 | }
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