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gerrit.osmocom.org / osmo-ttcn3-hacks / 4d1e9c92541606459923031d53247ad9fe625650 / . / bts / expected-results.xml
blob: bad4d6f127933b74bc102e24bcbaa28542a3de86 [file] [log] [blame]
Neels Hofmeyr29402a12018-05-08 17:32:06 +0200[diff] [blame]1<?xml version="1.0"?>
Neels Hofmeyr873ae202018-09-06 14:13:34 +0200[diff] [blame]2<testsuite name='Titan' tests='85' failures='1' errors='0' skipped='1' inconc='0' time='MASKED'>
Neels Hofmeyr29402a12018-05-08 17:32:06 +0200[diff] [blame]3 <testcase classname='BTS_Tests' name='TC_chan_act_stress' time='MASKED'/>
4 <testcase classname='BTS_Tests' name='TC_chan_act_react' time='MASKED'/>
5 <testcase classname='BTS_Tests' name='TC_chan_deact_not_active' time='MASKED'/>
6 <testcase classname='BTS_Tests' name='TC_chan_act_wrong_nr' time='MASKED'/>
7 <testcase classname='BTS_Tests' name='TC_deact_sacch' time='MASKED'/>
8 <testcase classname='BTS_Tests' name='TC_sacch_filling' time='MASKED'/>
9 <testcase classname='BTS_Tests' name='TC_sacch_info_mod' time='MASKED'/>
10 <testcase classname='BTS_Tests' name='TC_sacch_multi' time='MASKED'/>
Stefan Sperlingcd9e86f2018-07-25 11:50:33 +0200[diff] [blame]11 <testcase classname='BTS_Tests' name='TC_sacch_multi_chg' time='MASKED'/>
Neels Hofmeyr29402a12018-05-08 17:32:06 +0200[diff] [blame]12 <testcase classname='BTS_Tests' name='TC_rach_content' time='MASKED'/>
13 <testcase classname='BTS_Tests' name='TC_rach_count' time='MASKED'/>
14 <testcase classname='BTS_Tests' name='TC_rach_max_ta' time='MASKED'/>
15 <testcase classname='BTS_Tests' name='TC_meas_res_sign_tchf' time='MASKED'/>
16 <testcase classname='BTS_Tests' name='TC_meas_res_sign_tchh' time='MASKED'/>
17 <testcase classname='BTS_Tests' name='TC_meas_res_sign_sdcch4' time='MASKED'/>
18 <testcase classname='BTS_Tests' name='TC_meas_res_sign_sdcch8' time='MASKED'/>
19 <testcase classname='BTS_Tests' name='TC_meas_res_sign_tchh_toa256' time='MASKED'/>
Philipp Maier4d1e9c92018-12-20 11:11:56 +0100[diff] [blame^]20 <testcase classname='BTS_Tests' name='TC_rsl_ms_pwr_ctrl' time='MASKED'/>
Neels Hofmeyr29402a12018-05-08 17:32:06 +0200[diff] [blame]21 <testcase classname='BTS_Tests' name='TC_conn_fail_crit' time='MASKED'/>
22 <testcase classname='BTS_Tests' name='TC_paging_imsi_80percent' time='MASKED'/>
23 <testcase classname='BTS_Tests' name='TC_paging_tmsi_80percent' time='MASKED'/>
24 <testcase classname='BTS_Tests' name='TC_paging_imsi_200percent' time='MASKED'/>
25 <testcase classname='BTS_Tests' name='TC_paging_tmsi_200percent' time='MASKED'/>
26 <testcase classname='BTS_Tests' name='TC_rsl_protocol_error' time='MASKED'/>
27 <testcase classname='BTS_Tests' name='TC_rsl_mand_ie_error' time='MASKED'/>
28 <testcase classname='BTS_Tests' name='TC_rsl_ie_content_error' time='MASKED'/>
29 <testcase classname='BTS_Tests' name='TC_si_sched_default' time='MASKED'/>
30 <testcase classname='BTS_Tests' name='TC_si_sched_1' time='MASKED'/>
31 <testcase classname='BTS_Tests' name='TC_si_sched_2bis' time='MASKED'/>
32 <testcase classname='BTS_Tests' name='TC_si_sched_2ter' time='MASKED'/>
33 <testcase classname='BTS_Tests' name='TC_si_sched_2ter_2bis' time='MASKED'/>
34 <testcase classname='BTS_Tests' name='TC_si_sched_2quater' time='MASKED'/>
35 <testcase classname='BTS_Tests' name='TC_si_sched_13' time='MASKED'/>
36 <testcase classname='BTS_Tests' name='TC_si_sched_13_2bis_2ter_2quater' time='MASKED'/>
37 <testcase classname='BTS_Tests' name='TC_ipa_dlcx_not_active' time='MASKED'/>
38 <testcase classname='BTS_Tests' name='TC_ipa_crcx_twice_not_active' time='MASKED'/>
39 <testcase classname='BTS_Tests' name='TC_ipa_crcx_mdcx_dlcx_not_active' time='MASKED'/>
40 <testcase classname='BTS_Tests' name='TC_ipa_crcx_mdcx_mdcx_dlcx_not_active' time='MASKED'/>
41 <testcase classname='BTS_Tests' name='TC_ipa_crcx_sdcch_not_active' time='MASKED'/>
42 <testcase classname='BTS_Tests' name='TC_pcu_act_req' time='MASKED'/>
43 <testcase classname='BTS_Tests' name='TC_pcu_act_req_wrong_ts' time='MASKED'/>
44 <testcase classname='BTS_Tests' name='TC_pcu_act_req_wrong_bts' time='MASKED'/>
45 <testcase classname='BTS_Tests' name='TC_pcu_act_req_wrong_trx' time='MASKED'/>
46 <testcase classname='BTS_Tests' name='TC_pcu_deact_req' time='MASKED'/>
47 <testcase classname='BTS_Tests' name='TC_pcu_deact_req_wrong_ts' time='MASKED'/>
48 <testcase classname='BTS_Tests' name='TC_pcu_ver_si13' time='MASKED'/>
49 <testcase classname='BTS_Tests' name='TC_pcu_data_req_wrong_bts' time='MASKED'/>
50 <testcase classname='BTS_Tests' name='TC_pcu_data_req_wrong_trx' time='MASKED'/>
51 <testcase classname='BTS_Tests' name='TC_pcu_data_req_wrong_ts' time='MASKED'/>
52 <testcase classname='BTS_Tests' name='TC_pcu_data_req_ts_inactive' time='MASKED'>
53 <skipped>no verdict</skipped>
54 </testcase>
55 <testcase classname='BTS_Tests' name='TC_pcu_data_req_pdtch' time='MASKED'/>
56 <testcase classname='BTS_Tests' name='TC_pcu_data_req_ptcch' time='MASKED'/>
57 <testcase classname='BTS_Tests' name='TC_pcu_data_req_agch' time='MASKED'/>
58 <testcase classname='BTS_Tests' name='TC_pcu_data_req_imm_ass_pch' time='MASKED'/>
59 <testcase classname='BTS_Tests' name='TC_pcu_rach_content' time='MASKED'/>
60 <testcase classname='BTS_Tests' name='TC_pcu_paging_from_rsl' time='MASKED'/>
61 <testcase classname='BTS_Tests' name='TC_dyn_osmo_pdch_act_deact' time='MASKED'/>
Harald Welte8e8cd672018-05-10 23:11:54 +0200[diff] [blame]62 <testcase classname='BTS_Tests' name='TC_dyn_osmo_pdch_unsol_deact' time='MASKED'/>
63 <testcase classname='BTS_Tests' name='TC_dyn_osmo_pdch_double_act' time='MASKED'/>
Neels Hofmeyr29402a12018-05-08 17:32:06 +0200[diff] [blame]64 <testcase classname='BTS_Tests' name='TC_dyn_osmo_pdch_tchf_act' time='MASKED'/>
65 <testcase classname='BTS_Tests' name='TC_dyn_osmo_pdch_tchh_act' time='MASKED'/>
66 <testcase classname='BTS_Tests' name='TC_dyn_ipa_pdch_act_deact' time='MASKED'/>
67 <testcase classname='BTS_Tests' name='TC_dyn_ipa_pdch_tchf_act' time='MASKED'/>
Harald Welte8e8cd672018-05-10 23:11:54 +0200[diff] [blame]68 <testcase classname='BTS_Tests' name='TC_dyn_ipa_pdch_tchf_act_pdch_act_nack' time='MASKED'/>
69 <testcase classname='BTS_Tests' name='TC_dyn_ipa_pdch_act_tchf_act_nack' time='MASKED'/>
70 <testcase classname='BTS_Tests' name='TC_rll_est_ind' time='MASKED'/>
71 <testcase classname='BTS_Tests' name='TC_rll_est_req_DCCH_3' time='MASKED'/>
72 <testcase classname='BTS_Tests' name='TC_rll_est_req_ACCH_3' time='MASKED'/>
73 <testcase classname='BTS_Tests' name='TC_rll_rel_ind_DCCH_0' time='MASKED'/>
74 <testcase classname='BTS_Tests' name='TC_rll_rel_ind_DCCH_3' time='MASKED'/>
75 <testcase classname='BTS_Tests' name='TC_rll_rel_ind_ACCH_0' time='MASKED'/>
76 <testcase classname='BTS_Tests' name='TC_rll_rel_ind_ACCH_3' time='MASKED'/>
Neels Hofmeyr4fefb302018-05-14 14:20:09 +0200[diff] [blame]77 <testcase classname='BTS_Tests' name='TC_rll_rel_req' time='MASKED'/>
Harald Welte8e8cd672018-05-10 23:11:54 +0200[diff] [blame]78 <testcase classname='BTS_Tests' name='TC_rll_unit_data_req_DCCH' time='MASKED'/>
79 <testcase classname='BTS_Tests' name='TC_rll_unit_data_req_ACCH' time='MASKED'/>
80 <testcase classname='BTS_Tests' name='TC_rll_unit_data_ind_DCCH' time='MASKED'/>
81 <testcase classname='BTS_Tests' name='TC_rll_unit_data_ind_ACCH' time='MASKED'/>
82 <testcase classname='BTS_Tests' name='TC_chan_act_a51' time='MASKED'/>
83 <testcase classname='BTS_Tests' name='TC_chan_act_a52' time='MASKED'/>
84 <testcase classname='BTS_Tests' name='TC_chan_act_a53' time='MASKED'/>
85 <testcase classname='BTS_Tests' name='TC_encr_cmd_a51' time='MASKED'/>
86 <testcase classname='BTS_Tests' name='TC_encr_cmd_a52' time='MASKED'/>
87 <testcase classname='BTS_Tests' name='TC_encr_cmd_a53' time='MASKED'/>
88 <testcase classname='BTS_Tests' name='TC_lapdm_selftest' time='MASKED'/>
Stefan Sperling4880be42018-08-07 18:12:59 +0200[diff] [blame]89 <testcase classname='BTS_Tests' name='TC_tch_sign_l2_fill_frame' time='MASKED'/>
90 <testcase classname='BTS_Tests' name='TC_tch_sign_l2_fill_frame_dtxd' time='MASKED'>
Neels Hofmeyr873ae202018-09-06 14:13:34 +0200[diff] [blame]91 <failure type='fail-verdict'>Not enough fill frames received
Stefan Sperling4880be42018-08-07 18:12:59 +0200[diff] [blame]92 BTS_Tests.ttcn:MASKED BTS_Tests control part
93 BTS_Tests.ttcn:MASKED TC_tch_sign_l2_fill_frame_dtxd testcase
94 </failure>
95 </testcase>
Neels Hofmeyr29402a12018-05-08 17:32:06 +0200[diff] [blame]96</testsuite>