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Pau Espin Pedrol5ea18172018-02-20 16:48:15 +01001#pragma once
2
3#include <osmocom/vty/command.h>
4
Pau Espin Pedrola3ab8c22018-02-21 15:41:03 +01005#include "config_defs.h"
6
Pau Espin Pedrol5ea18172018-02-20 16:48:15 +01007extern struct vty_app_info g_vty_info;
Pau Espin Pedrola7bf6cd2020-01-14 17:52:15 +01008extern const struct value_string clock_ref_names[];
Alexander Chemeris9a87d902019-10-15 00:33:07 +03009extern const struct value_string filler_names[];
Pau Espin Pedrol5ea18172018-02-20 16:48:15 +010010
Tom Tsoud2800452019-04-01 07:55:48 +070011/* Maximum number of physical RF channels */
Pau Espin Pedrola3ab8c22018-02-21 15:41:03 +010012#define TRX_CHAN_MAX 8
Tom Tsoud2800452019-04-01 07:55:48 +070013/* Maximum number of carriers in multi-ARFCN mode */
14#define TRX_MCHAN_MAX 3
Pau Espin Pedrola3ab8c22018-02-21 15:41:03 +010015
16/* Samples-per-symbol for downlink path
17 * 4 - Uses precision modulator (more computation, less distortion)
18 * 1 - Uses minimized modulator (less computation, more distortion)
19 *
20 * Other values are invalid. Receive path (uplink) is always
21 * downsampled to 1 sps. Default to 4 sps for all cases.
22 */
23#define DEFAULT_TX_SPS 4
24
25/*
26 * Samples-per-symbol for uplink (receiver) path
27 * Do not modify this value. EDGE configures 4 sps automatically on
28 * B200/B210 devices only. Use of 4 sps on the receive path for other
29 * configurations is not supported.
30 */
31#define DEFAULT_RX_SPS 1
32
33/* Default configuration parameters */
34#define DEFAULT_TRX_PORT 5700
35#define DEFAULT_TRX_IP "127.0.0.1"
36#define DEFAULT_CHANS 1
37
38struct trx_ctx;
39
40struct trx_chan {
41 struct trx_ctx *trx; /* backpointer */
42 unsigned int idx; /* channel index */
43 char *rx_path;
44 char *tx_path;
45};
46
Pau Espin Pedrol5ea18172018-02-20 16:48:15 +010047struct trx_ctx {
48 struct {
49 char *bind_addr;
Pau Espin Pedrola3ab8c22018-02-21 15:41:03 +010050 char *remote_addr;
51 char *dev_args;
52 unsigned int base_port;
53 unsigned int tx_sps;
54 unsigned int rx_sps;
55 unsigned int rtsc;
Pau Espin Pedrola3ab8c22018-02-21 15:41:03 +010056 unsigned int rach_delay;
Pau Espin Pedrola3ab8c22018-02-21 15:41:03 +010057 enum ReferenceType clock_ref;
58 enum FillerType filler;
59 bool multi_arfcn;
60 double offset;
61 double rssi_offset;
62 bool swap_channels;
Vadim Yanitskiya8b35652018-10-22 02:52:18 +020063 bool ext_rach;
Pau Espin Pedrola3ab8c22018-02-21 15:41:03 +010064 bool egprs;
65 unsigned int sched_rr;
Eric Wildac0487e2019-06-17 13:02:44 +020066 unsigned int stack_size;
Pau Espin Pedrola3ab8c22018-02-21 15:41:03 +010067 unsigned int num_chans;
68 struct trx_chan chans[TRX_CHAN_MAX];
Pau Espin Pedrol5ea18172018-02-20 16:48:15 +010069 } cfg;
70};
71
72int trx_vty_init(struct trx_ctx* trx);
Pau Espin Pedrola3ab8c22018-02-21 15:41:03 +010073struct trx_ctx *vty_trx_ctx_alloc(void *talloc_ctx);