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Pau Espin Pedrol5ea18172018-02-20 16:48:15 +01001#pragma once
2
3#include <osmocom/vty/command.h>
4
Pau Espin Pedrola3ab8c22018-02-21 15:41:03 +01005#include "config_defs.h"
6
Pau Espin Pedrol5ea18172018-02-20 16:48:15 +01007extern struct vty_app_info g_vty_info;
Alexander Chemeris9a87d902019-10-15 00:33:07 +03008extern const struct value_string filler_names[];
Pau Espin Pedrol5ea18172018-02-20 16:48:15 +01009
Tom Tsoud2800452019-04-01 07:55:48 +070010/* Maximum number of physical RF channels */
Pau Espin Pedrola3ab8c22018-02-21 15:41:03 +010011#define TRX_CHAN_MAX 8
Tom Tsoud2800452019-04-01 07:55:48 +070012/* Maximum number of carriers in multi-ARFCN mode */
13#define TRX_MCHAN_MAX 3
Pau Espin Pedrola3ab8c22018-02-21 15:41:03 +010014
15/* Samples-per-symbol for downlink path
16 * 4 - Uses precision modulator (more computation, less distortion)
17 * 1 - Uses minimized modulator (less computation, more distortion)
18 *
19 * Other values are invalid. Receive path (uplink) is always
20 * downsampled to 1 sps. Default to 4 sps for all cases.
21 */
22#define DEFAULT_TX_SPS 4
23
24/*
25 * Samples-per-symbol for uplink (receiver) path
26 * Do not modify this value. EDGE configures 4 sps automatically on
27 * B200/B210 devices only. Use of 4 sps on the receive path for other
28 * configurations is not supported.
29 */
30#define DEFAULT_RX_SPS 1
31
32/* Default configuration parameters */
33#define DEFAULT_TRX_PORT 5700
34#define DEFAULT_TRX_IP "127.0.0.1"
35#define DEFAULT_CHANS 1
36
37struct trx_ctx;
38
39struct trx_chan {
40 struct trx_ctx *trx; /* backpointer */
41 unsigned int idx; /* channel index */
42 char *rx_path;
43 char *tx_path;
44};
45
Pau Espin Pedrol5ea18172018-02-20 16:48:15 +010046struct trx_ctx {
47 struct {
48 char *bind_addr;
Pau Espin Pedrola3ab8c22018-02-21 15:41:03 +010049 char *remote_addr;
50 char *dev_args;
51 unsigned int base_port;
52 unsigned int tx_sps;
53 unsigned int rx_sps;
54 unsigned int rtsc;
Pau Espin Pedrola3ab8c22018-02-21 15:41:03 +010055 unsigned int rach_delay;
Pau Espin Pedrola3ab8c22018-02-21 15:41:03 +010056 enum ReferenceType clock_ref;
57 enum FillerType filler;
58 bool multi_arfcn;
59 double offset;
60 double rssi_offset;
61 bool swap_channels;
Vadim Yanitskiya8b35652018-10-22 02:52:18 +020062 bool ext_rach;
Pau Espin Pedrola3ab8c22018-02-21 15:41:03 +010063 bool egprs;
64 unsigned int sched_rr;
Eric Wildac0487e2019-06-17 13:02:44 +020065 unsigned int stack_size;
Pau Espin Pedrola3ab8c22018-02-21 15:41:03 +010066 unsigned int num_chans;
67 struct trx_chan chans[TRX_CHAN_MAX];
Pau Espin Pedrol5ea18172018-02-20 16:48:15 +010068 } cfg;
69};
70
71int trx_vty_init(struct trx_ctx* trx);
Pau Espin Pedrola3ab8c22018-02-21 15:41:03 +010072struct trx_ctx *vty_trx_ctx_alloc(void *talloc_ctx);