blob: 2bfd1b54bd3773d158f0d3c44c2389d8873b8214 [file] [log] [blame]
Sylvain Munautbd83e532020-09-15 22:11:29 +02001# Project config
2PROJ=icE1usb
3
4PROJ_DEPS := no2e1 no2ice40 no2misc no2usb
5PROJ_RTL_SRCS := $(addprefix rtl/, \
6 i2c_master.v \
7 i2c_master_wb.v \
8 led_blinker.v \
9 misc.v \
10 sr_btn_if.v \
11 sysmgr.v \
12)
13PROJ_RTL_SRCS += $(addprefix ../common/rtl/, \
Sylvain Munautff0ab3e2020-10-03 20:15:28 +020014 capcnt.v \
15 capcnt_sb_mac16.v \
Sylvain Munautbd83e532020-09-15 22:11:29 +020016 dfu_helper.v \
17 picorv32.v \
Sylvain Munautc75f71e2020-10-03 20:01:58 +020018 picorv32_ice40_regs.v \
Sylvain Munautbd83e532020-09-15 22:11:29 +020019 soc_base.v \
20 soc_bram.v \
21 soc_iobuf.v \
22 soc_picorv32_bridge.v \
23 soc_spram.v \
24 wb_arbiter.v \
25 wb_dma.v \
26 wb_epbuf.v \
27)
28PROJ_PREREQ = \
29 $(BUILD_TMP)/boot.hex \
30 $(NULL)
31PROJ_TOP_SRC := rtl/top.v
32PROJ_TOP_MOD := top
33
34# Target config
35BOARD ?= ice1usb
Sylvain Munaut0f29d6a2020-10-09 13:22:58 +020036DEVICE := up5k
37PACKAGE := sg48
Sylvain Munautbd83e532020-09-15 22:11:29 +020038
Sylvain Munaut0f29d6a2020-10-09 13:22:58 +020039SEED ?= 15
Sylvain Munautbd399e92020-10-09 13:40:16 +020040YOSYS_SYNTH_ARGS :=
41NEXTPNR_ARGS := --pre-pack data/clocks.py --pre-pack data/opt.py --seed $(SEED)
Sylvain Munaut0f29d6a2020-10-09 13:22:58 +020042
43ifeq ($(IGNORE_TIMING),1)
44 NEXTPNR_ARGS += --timing-allow-fail
45endif
Sylvain Munautd420ffc2020-10-09 13:25:51 +020046ifeq ($(SINGLE_CHANNEL),1)
47 YOSYS_READ_ARGS += -DWITH_SINGLE_CHANNEL
48endif
Sylvain Munautbd83e532020-09-15 22:11:29 +020049
50# Include default rules
Sylvain Munaut84717d62020-10-03 20:18:00 +020051NO2BUILD_DIR ?= ../build
Sylvain Munautbd83e532020-09-15 22:11:29 +020052include $(NO2BUILD_DIR)/project-rules.mk
53
54# Custom rules
55../common/fw/boot.hex:
56 make -C ../common/fw boot.hex
57
58$(BUILD_TMP)/boot.hex: ../common/fw/boot.hex
59 cp $< $@