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Sylvain Munautbc9f5c42020-09-14 10:22:29 +02001/*
2 * e1.c
3 *
4 * Copyright (C) 2019-2020 Sylvain Munaut <tnt@246tNt.com>
5 * SPDX-License-Identifier: GPL-3.0-or-later
6 */
7
8#include <stdint.h>
9#include <stdbool.h>
10#include <string.h>
11
12#include "config.h"
13#include "console.h"
14#include "e1.h"
Harald Weltef74dad72020-12-15 23:32:53 +010015#include "e1_hw.h"
Sylvain Munautbc9f5c42020-09-14 10:22:29 +020016
17#include "dma.h"
18#include "led.h" // FIXME
19
20
Sylvain Munautbc9f5c42020-09-14 10:22:29 +020021static volatile struct e1_core * const e1_regs = (void *)(E1_CORE_BASE);
22static volatile uint8_t * const e1_data = (void *)(E1_DATA_BASE);
23
Sylvain Munautbc9f5c42020-09-14 10:22:29 +020024unsigned int
25e1_data_ofs(int mf, int frame, int ts)
26{
27 return (mf << 9) | (frame << 5) | ts;
28}
29
Harald Weltea59ef2b2020-12-14 17:02:13 +010030volatile uint8_t *
31e1_data_ptr(int mf, int frame, int ts)
32{
33 return &e1_data[e1_data_ofs(mf, frame, ts)];
34}
Sylvain Munautbc9f5c42020-09-14 10:22:29 +020035
36// FIFOs
37// -----
38/* Note: FIFO works at 'frame' level (i.e. 32 bytes) */
39
40struct e1_fifo {
41 /* Buffer zone associated with the FIFO */
42 unsigned int base;
43 unsigned int mask;
44
45 /* Pointers / Levels */
46 unsigned int wptr[2]; /* 0=committed 1=allocated */
47 unsigned int rptr[2]; /* 0=discared 1=peeked */
48};
49
50 /* Utils */
51static void
52e1f_reset(struct e1_fifo *fifo, unsigned int base, unsigned int len)
53{
54 memset(fifo, 0x00, sizeof(struct e1_fifo));
55 fifo->base = base;
56 fifo->mask = len - 1;
57}
58
59static unsigned int
60e1f_allocd_frames(struct e1_fifo *fifo)
61{
62 /* Number of frames that are allocated (i.e. where we can't write to) */
63 return (fifo->wptr[1] - fifo->rptr[0]) & fifo->mask;
64}
65
66static unsigned int
67e1f_valid_frames(struct e1_fifo *fifo)
68{
69 /* Number of valid frames */
70 return (fifo->wptr[0] - fifo->rptr[0]) & fifo->mask;
71}
72
73static unsigned int
74e1f_unseen_frames(struct e1_fifo *fifo)
75{
76 /* Number of valid frames that haven't been peeked yet */
77 return (fifo->wptr[0] - fifo->rptr[1]) & fifo->mask;
78}
79
80static unsigned int
81e1f_free_frames(struct e1_fifo *fifo)
82{
83 /* Number of frames that aren't allocated */
84 return (fifo->rptr[0] - fifo->wptr[1] - 1) & fifo->mask;
85}
86
87static unsigned int
88e1f_ofs_to_dma(unsigned int ofs)
89{
90 /* DMA address are 32-bits word address. Offsets are 32 byte address */
91 return (ofs << 3);
92}
93
94static unsigned int
95e1f_ofs_to_mf(unsigned int ofs)
96{
97 /* E1 Buffer Descriptors are always multiframe aligned */
98 return (ofs >> 4);
99}
100
101
102 /* Debug */
103static void
104e1f_debug(struct e1_fifo *fifo, const char *name)
105{
106 unsigned int la, lv, lu, lf;
107
108 la = e1f_allocd_frames(fifo);
109 lv = e1f_valid_frames(fifo);
110 lu = e1f_unseen_frames(fifo);
111 lf = e1f_free_frames(fifo);
112
113 printf("%s: R: %u / %u | W: %u / %u | A:%u V:%u U:%u F:%u\n",
114 name,
115 fifo->rptr[0], fifo->rptr[1], fifo->wptr[0], fifo->wptr[1],
116 la, lv, lu, lf
117 );
118}
119
120 /* Frame level read/write */
121static unsigned int
122e1f_frame_write(struct e1_fifo *fifo, unsigned int *ofs, unsigned int max_frames)
123{
124 unsigned int lf, le;
125
126 lf = e1f_free_frames(fifo);
127 le = fifo->mask - fifo->wptr[0] + 1;
128
129 if (max_frames > le)
130 max_frames = le;
131 if (max_frames > lf)
132 max_frames = lf;
133
134 *ofs = fifo->base + fifo->wptr[0];
135 fifo->wptr[1] = fifo->wptr[0] = (fifo->wptr[0] + max_frames) & fifo->mask;
136
137 return max_frames;
138}
139
140static unsigned int
Sylvain Munautde20fb72020-10-29 13:24:50 +0100141e1f_frame_read(struct e1_fifo *fifo, unsigned int *ofs, unsigned int max_frames)
Sylvain Munautbc9f5c42020-09-14 10:22:29 +0200142{
143 unsigned int lu, le;
144
145 lu = e1f_unseen_frames(fifo);
146 le = fifo->mask - fifo->rptr[1] + 1;
147
148 if (max_frames > le)
149 max_frames = le;
150 if (max_frames > lu)
151 max_frames = lu;
152
153 *ofs = fifo->base + fifo->rptr[1];
154 fifo->rptr[0] = fifo->rptr[1] = (fifo->rptr[1] + max_frames) & fifo->mask;
155
156 return max_frames;
157}
158
159
160 /* MultiFrame level split read/write */
161static bool
162e1f_multiframe_write_prepare(struct e1_fifo *fifo, unsigned int *ofs)
163{
164 unsigned int lf;
165
166 lf = e1f_free_frames(fifo);
167 if (lf < 16)
168 return false;
169
170 *ofs = fifo->base + fifo->wptr[1];
171 fifo->wptr[1] = (fifo->wptr[1] + 16) & fifo->mask;
172
173 return true;
174}
175
176static void
177e1f_multiframe_write_commit(struct e1_fifo *fifo)
178{
179 fifo->wptr[0] = (fifo->wptr[0] + 16) & fifo->mask;
180}
181
182static bool
183e1f_multiframe_read_peek(struct e1_fifo *fifo, unsigned int *ofs)
184{
185 unsigned int lu;
186
187 lu = e1f_unseen_frames(fifo);
188 if (lu < 16)
189 return false;
190
191 *ofs = fifo->base + fifo->rptr[1];
192 fifo->rptr[1] = (fifo->rptr[1] + 16) & fifo->mask;
193
194 return true;
195}
196
197static void
198e1f_multiframe_read_discard(struct e1_fifo *fifo)
199{
200 fifo->rptr[0] = (fifo->rptr[0] + 16) & fifo->mask;
201}
202
203static void
204e1f_multiframe_empty(struct e1_fifo *fifo)
205{
206 fifo->rptr[0] = fifo->rptr[1] = (fifo->wptr[0] & ~15);
207}
208
209
210
211// Main logic
212// ----------
213
214enum e1_pipe_state {
Harald Welte30fc5602020-12-14 15:56:28 +0100215 IDLE = 0, /* not yet initialized */
216 BOOT = 1, /* after e1_init(), regiters are programmed */
217 RUN = 2, /* normal operation */
218 RECOVER = 3, /* after underflow, overflow or alignment error */
Sylvain Munautbc9f5c42020-09-14 10:22:29 +0200219};
220
221static struct {
222 struct {
223 uint32_t cr;
224 struct e1_fifo fifo;
225 int in_flight;
226 enum e1_pipe_state state;
227 } rx;
228
229 struct {
230 uint32_t cr;
231 struct e1_fifo fifo;
232 int in_flight;
233 enum e1_pipe_state state;
234 } tx;
235} g_e1;
236
237
238
239
240void
Harald Welte9469e042020-12-15 23:09:40 +0100241e1_init(uint16_t rx_cr, uint16_t tx_cr)
Sylvain Munautbc9f5c42020-09-14 10:22:29 +0200242{
243 /* Global state init */
244 memset(&g_e1, 0x00, sizeof(g_e1));
245
246 /* Reset FIFOs */
247 e1f_reset(&g_e1.rx.fifo, 0, 128);
248 e1f_reset(&g_e1.tx.fifo, 128, 128);
249
250 /* Enable Rx */
Harald Welte9469e042020-12-15 23:09:40 +0100251 g_e1.rx.cr = E1_RX_CR_ENABLE | rx_cr;
Harald Welte7f74fe62020-12-27 14:33:37 +0100252 e1_regs->rx.csr = E1_RX_CR_OVFL_CLR | g_e1.rx.cr;
Sylvain Munautbc9f5c42020-09-14 10:22:29 +0200253
254 /* Enable Tx */
Harald Welte9469e042020-12-15 23:09:40 +0100255 g_e1.tx.cr = E1_TX_CR_ENABLE | tx_cr;
Harald Welte7f74fe62020-12-27 14:33:37 +0100256 e1_regs->tx.csr = E1_TX_CR_UNFL_CLR | g_e1.tx.cr;
Sylvain Munautbc9f5c42020-09-14 10:22:29 +0200257
258 /* State */
259 g_e1.rx.state = BOOT;
260 g_e1.tx.state = BOOT;
261}
262
Harald Welte6add0aa2020-12-16 00:02:11 +0100263#define TXCR_PERMITTED ( \
264 E1_TX_CR_MODE_TS0_CRC_E | \
265 E1_TX_CR_TICK_REMOTE | \
266 E1_TX_CR_ALARM | \
267 E1_TX_CR_LOOPBACK | \
268 E1_TX_CR_LOOPBACK_CROSS )
269
270void
271e1_tx_config(uint16_t cr)
272{
273 g_e1.tx.cr = (g_e1.tx.cr & ~TXCR_PERMITTED) | (cr & TXCR_PERMITTED);
274 e1_regs->tx.csr = g_e1.tx.cr;
275}
276
277#define RXCR_PERMITTED ( \
278 E1_RX_CR_MODE_MFA )
279
280void
281e1_rx_config(uint16_t cr)
282{
283 g_e1.rx.cr = (g_e1.rx.cr & ~RXCR_PERMITTED) | (cr & RXCR_PERMITTED);
284 e1_regs->rx.csr = g_e1.rx.cr;
285}
Sylvain Munautbc9f5c42020-09-14 10:22:29 +0200286
287#include "dma.h"
288
289unsigned int
Harald Weltedaff4f62020-12-14 17:39:23 +0100290e1_rx_need_data(unsigned int usb_addr, unsigned int max_frames, unsigned int *pos)
Sylvain Munautbc9f5c42020-09-14 10:22:29 +0200291{
292 unsigned int ofs;
293 int tot_frames = 0;
294 int n_frames;
295
296 while (max_frames) {
297 /* Get some data from the FIFO */
298 n_frames = e1f_frame_read(&g_e1.rx.fifo, &ofs, max_frames);
299 if (!n_frames)
300 break;
301
Harald Weltedaff4f62020-12-14 17:39:23 +0100302 /* Give pos */
303 if (pos) {
304 *pos = ofs & g_e1.rx.fifo.mask;
305 pos = NULL;
306 }
307
Sylvain Munautbc9f5c42020-09-14 10:22:29 +0200308 /* Copy from FIFO to USB */
309 dma_exec(e1f_ofs_to_dma(ofs), usb_addr, n_frames * (32 / 4), false, NULL, NULL);
310
311 /* Prepare Next */
312 usb_addr += n_frames * (32 / 4);
313 max_frames -= n_frames;
314 tot_frames += n_frames;
315
316 /* Wait for DMA completion */
317 while (dma_poll());
318 }
319
320 return tot_frames;
321}
322
323unsigned int
324e1_tx_feed_data(unsigned int usb_addr, unsigned int frames)
325{
326 unsigned int ofs;
327 int n_frames;
328
329 while (frames) {
330 /* Get some space in FIFO */
331 n_frames = e1f_frame_write(&g_e1.tx.fifo, &ofs, frames);
332 if (!n_frames) {
333 printf("[!] TX FIFO Overflow %d %d\n", frames, n_frames);
334 break;
335 }
336
337 /* Copy from USB to FIFO */
338 dma_exec(e1f_ofs_to_dma(ofs), usb_addr, n_frames * (32 / 4), true, NULL, NULL);
339
340 /* Prepare next */
341 usb_addr += n_frames * (32 / 4);
342 frames -= n_frames;
343
344 /* Wait for DMA completion */
345 while (dma_poll());
346 }
347
348 return frames;
349}
350
351unsigned int
352e1_tx_level(void)
353{
354 return e1f_valid_frames(&g_e1.tx.fifo);
355}
356
357unsigned int
358e1_rx_level(void)
359{
360 return e1f_valid_frames(&g_e1.rx.fifo);
361}
362
363void
364e1_poll(void)
365{
366 uint32_t bd;
367 unsigned int ofs;
368
369 /* Active ? */
370 if ((g_e1.rx.state == IDLE) && (g_e1.tx.state == IDLE))
371 return;
372
373 /* HACK: LED link status */
Harald Welte52765672020-12-15 18:35:42 +0100374 if (e1_regs->rx.csr & E1_RX_SR_ALIGNED) {
375 e1_platform_led_set(0, E1P_LED_GREEN, E1P_LED_ST_ON);
Sylvain Munautbc9f5c42020-09-14 10:22:29 +0200376 led_color(0, 48, 0);
Harald Welte52765672020-12-15 18:35:42 +0100377 } else {
378 e1_platform_led_set(0, E1P_LED_GREEN, E1P_LED_ST_BLINK);
379 /* TODO: completely off if rx tick counter not incrementing */
Sylvain Munautbc9f5c42020-09-14 10:22:29 +0200380 led_color(48, 0, 0);
Harald Welte52765672020-12-15 18:35:42 +0100381 }
Sylvain Munautbc9f5c42020-09-14 10:22:29 +0200382
383 /* Recover any done TX BD */
384 while ( (bd = e1_regs->tx.bd) & E1_BD_VALID ) {
385 e1f_multiframe_read_discard(&g_e1.tx.fifo);
386 g_e1.tx.in_flight--;
387 }
388
389 /* Recover any done RX BD */
390 while ( (bd = e1_regs->rx.bd) & E1_BD_VALID ) {
391 /* FIXME: CRC status ? */
392 e1f_multiframe_write_commit(&g_e1.rx.fifo);
393 if ((bd & (E1_BD_CRC0 | E1_BD_CRC1)) != (E1_BD_CRC0 | E1_BD_CRC1))
394 printf("b: %03x\n", bd);
395 g_e1.rx.in_flight--;
396 }
397
398 /* Boot procedure */
399 if (g_e1.tx.state == BOOT) {
400 if (e1f_unseen_frames(&g_e1.tx.fifo) < (16 * 5))
401 return;
402 /* HACK: LED flow status */
403 led_blink(true, 200, 1000);
404 led_breathe(true, 100, 200);
405 }
406
407 /* Handle RX */
408 /* Misalign ? */
409 if (g_e1.rx.state == RUN) {
410 if (!(e1_regs->rx.csr & E1_RX_SR_ALIGNED)) {
411 printf("[!] E1 rx misalign\n");
412 g_e1.rx.state = RECOVER;
413 }
414 }
415
416 /* Overflow ? */
417 if (g_e1.rx.state == RUN) {
418 if (e1_regs->rx.csr & E1_RX_SR_OVFL) {
419 printf("[!] E1 overflow %d\n", g_e1.rx.in_flight);
420 g_e1.rx.state = RECOVER;
421 }
422 }
423
424 /* Recover ready ? */
425 if (g_e1.rx.state == RECOVER) {
426 if (g_e1.rx.in_flight != 0)
427 goto done_rx;
428 e1f_multiframe_empty(&g_e1.rx.fifo);
429 }
430
431 /* Fill new RX BD */
432 while (g_e1.rx.in_flight < 4) {
433 if (!e1f_multiframe_write_prepare(&g_e1.rx.fifo, &ofs))
434 break;
435 e1_regs->rx.bd = e1f_ofs_to_mf(ofs);
436 g_e1.rx.in_flight++;
437 }
438
439 /* Clear overflow if needed */
440 if (g_e1.rx.state != RUN) {
441 e1_regs->rx.csr = g_e1.rx.cr | E1_RX_CR_OVFL_CLR;
442 g_e1.rx.state = RUN;
443 }
444done_rx:
445
446 /* Handle TX */
447 /* Underflow ? */
448 if (g_e1.tx.state == RUN) {
449 if (e1_regs->tx.csr & E1_TX_SR_UNFL) {
450 printf("[!] E1 underflow %d\n", g_e1.tx.in_flight);
451 g_e1.tx.state = RECOVER;
452 }
453 }
454
455 /* Recover ready ? */
456 if (g_e1.tx.state == RECOVER) {
457 if (e1f_unseen_frames(&g_e1.tx.fifo) < (16 * 5))
458 return;
459 }
460
461 /* Fill new TX BD */
462 while (g_e1.tx.in_flight < 4) {
463 if (!e1f_multiframe_read_peek(&g_e1.tx.fifo, &ofs))
464 break;
465 e1_regs->tx.bd = e1f_ofs_to_mf(ofs);
466 g_e1.tx.in_flight++;
467 }
468
469 /* Clear underflow if needed */
470 if (g_e1.tx.state != RUN) {
471 e1_regs->tx.csr = g_e1.tx.cr | E1_TX_CR_UNFL_CLR;
472 g_e1.tx.state = RUN;
473 }
474}
475
476void
477e1_debug_print(bool data)
478{
479 volatile uint8_t *p;
480
481 puts("E1\n");
482 printf("CSR: Rx %04x / Tx %04x\n", e1_regs->rx.csr, e1_regs->tx.csr);
483 printf("InF: Rx %d / Tx %d\n", g_e1.rx.in_flight, g_e1.tx.in_flight);
484 printf("Sta: Rx %d / Tx %d\n", g_e1.rx.state, g_e1.tx.state);
485
486 e1f_debug(&g_e1.rx.fifo, "Rx FIFO");
487 e1f_debug(&g_e1.tx.fifo, "Tx FIFO");
488
489 if (data) {
490 puts("\nE1 Data\n");
491 for (int f=0; f<16; f++) {
492 p = e1_data_ptr(0, f, 0);
493 for (int ts=0; ts<32; ts++)
494 printf(" %02x", p[ts]);
495 printf("\n");
496 }
497 }
498}