Sylvain Munaut | bc9f5c4 | 2020-09-14 10:22:29 +0200 | [diff] [blame] | 1 | /* |
| 2 | * e1.c |
| 3 | * |
| 4 | * Copyright (C) 2019-2020 Sylvain Munaut <tnt@246tNt.com> |
| 5 | * SPDX-License-Identifier: GPL-3.0-or-later |
| 6 | */ |
| 7 | |
| 8 | #include <stdint.h> |
| 9 | #include <stdbool.h> |
| 10 | #include <string.h> |
| 11 | |
| 12 | #include "config.h" |
| 13 | #include "console.h" |
| 14 | #include "e1.h" |
Harald Welte | f74dad7 | 2020-12-15 23:32:53 +0100 | [diff] [blame^] | 15 | #include "e1_hw.h" |
Sylvain Munaut | bc9f5c4 | 2020-09-14 10:22:29 +0200 | [diff] [blame] | 16 | |
| 17 | #include "dma.h" |
| 18 | #include "led.h" // FIXME |
| 19 | |
| 20 | |
Sylvain Munaut | bc9f5c4 | 2020-09-14 10:22:29 +0200 | [diff] [blame] | 21 | static volatile struct e1_core * const e1_regs = (void *)(E1_CORE_BASE); |
| 22 | static volatile uint8_t * const e1_data = (void *)(E1_DATA_BASE); |
| 23 | |
Sylvain Munaut | bc9f5c4 | 2020-09-14 10:22:29 +0200 | [diff] [blame] | 24 | unsigned int |
| 25 | e1_data_ofs(int mf, int frame, int ts) |
| 26 | { |
| 27 | return (mf << 9) | (frame << 5) | ts; |
| 28 | } |
| 29 | |
Harald Welte | a59ef2b | 2020-12-14 17:02:13 +0100 | [diff] [blame] | 30 | volatile uint8_t * |
| 31 | e1_data_ptr(int mf, int frame, int ts) |
| 32 | { |
| 33 | return &e1_data[e1_data_ofs(mf, frame, ts)]; |
| 34 | } |
Sylvain Munaut | bc9f5c4 | 2020-09-14 10:22:29 +0200 | [diff] [blame] | 35 | |
| 36 | // FIFOs |
| 37 | // ----- |
| 38 | /* Note: FIFO works at 'frame' level (i.e. 32 bytes) */ |
| 39 | |
| 40 | struct e1_fifo { |
| 41 | /* Buffer zone associated with the FIFO */ |
| 42 | unsigned int base; |
| 43 | unsigned int mask; |
| 44 | |
| 45 | /* Pointers / Levels */ |
| 46 | unsigned int wptr[2]; /* 0=committed 1=allocated */ |
| 47 | unsigned int rptr[2]; /* 0=discared 1=peeked */ |
| 48 | }; |
| 49 | |
| 50 | /* Utils */ |
| 51 | static void |
| 52 | e1f_reset(struct e1_fifo *fifo, unsigned int base, unsigned int len) |
| 53 | { |
| 54 | memset(fifo, 0x00, sizeof(struct e1_fifo)); |
| 55 | fifo->base = base; |
| 56 | fifo->mask = len - 1; |
| 57 | } |
| 58 | |
| 59 | static unsigned int |
| 60 | e1f_allocd_frames(struct e1_fifo *fifo) |
| 61 | { |
| 62 | /* Number of frames that are allocated (i.e. where we can't write to) */ |
| 63 | return (fifo->wptr[1] - fifo->rptr[0]) & fifo->mask; |
| 64 | } |
| 65 | |
| 66 | static unsigned int |
| 67 | e1f_valid_frames(struct e1_fifo *fifo) |
| 68 | { |
| 69 | /* Number of valid frames */ |
| 70 | return (fifo->wptr[0] - fifo->rptr[0]) & fifo->mask; |
| 71 | } |
| 72 | |
| 73 | static unsigned int |
| 74 | e1f_unseen_frames(struct e1_fifo *fifo) |
| 75 | { |
| 76 | /* Number of valid frames that haven't been peeked yet */ |
| 77 | return (fifo->wptr[0] - fifo->rptr[1]) & fifo->mask; |
| 78 | } |
| 79 | |
| 80 | static unsigned int |
| 81 | e1f_free_frames(struct e1_fifo *fifo) |
| 82 | { |
| 83 | /* Number of frames that aren't allocated */ |
| 84 | return (fifo->rptr[0] - fifo->wptr[1] - 1) & fifo->mask; |
| 85 | } |
| 86 | |
| 87 | static unsigned int |
| 88 | e1f_ofs_to_dma(unsigned int ofs) |
| 89 | { |
| 90 | /* DMA address are 32-bits word address. Offsets are 32 byte address */ |
| 91 | return (ofs << 3); |
| 92 | } |
| 93 | |
| 94 | static unsigned int |
| 95 | e1f_ofs_to_mf(unsigned int ofs) |
| 96 | { |
| 97 | /* E1 Buffer Descriptors are always multiframe aligned */ |
| 98 | return (ofs >> 4); |
| 99 | } |
| 100 | |
| 101 | |
| 102 | /* Debug */ |
| 103 | static void |
| 104 | e1f_debug(struct e1_fifo *fifo, const char *name) |
| 105 | { |
| 106 | unsigned int la, lv, lu, lf; |
| 107 | |
| 108 | la = e1f_allocd_frames(fifo); |
| 109 | lv = e1f_valid_frames(fifo); |
| 110 | lu = e1f_unseen_frames(fifo); |
| 111 | lf = e1f_free_frames(fifo); |
| 112 | |
| 113 | printf("%s: R: %u / %u | W: %u / %u | A:%u V:%u U:%u F:%u\n", |
| 114 | name, |
| 115 | fifo->rptr[0], fifo->rptr[1], fifo->wptr[0], fifo->wptr[1], |
| 116 | la, lv, lu, lf |
| 117 | ); |
| 118 | } |
| 119 | |
| 120 | /* Frame level read/write */ |
| 121 | static unsigned int |
| 122 | e1f_frame_write(struct e1_fifo *fifo, unsigned int *ofs, unsigned int max_frames) |
| 123 | { |
| 124 | unsigned int lf, le; |
| 125 | |
| 126 | lf = e1f_free_frames(fifo); |
| 127 | le = fifo->mask - fifo->wptr[0] + 1; |
| 128 | |
| 129 | if (max_frames > le) |
| 130 | max_frames = le; |
| 131 | if (max_frames > lf) |
| 132 | max_frames = lf; |
| 133 | |
| 134 | *ofs = fifo->base + fifo->wptr[0]; |
| 135 | fifo->wptr[1] = fifo->wptr[0] = (fifo->wptr[0] + max_frames) & fifo->mask; |
| 136 | |
| 137 | return max_frames; |
| 138 | } |
| 139 | |
| 140 | static unsigned int |
Sylvain Munaut | de20fb7 | 2020-10-29 13:24:50 +0100 | [diff] [blame] | 141 | e1f_frame_read(struct e1_fifo *fifo, unsigned int *ofs, unsigned int max_frames) |
Sylvain Munaut | bc9f5c4 | 2020-09-14 10:22:29 +0200 | [diff] [blame] | 142 | { |
| 143 | unsigned int lu, le; |
| 144 | |
| 145 | lu = e1f_unseen_frames(fifo); |
| 146 | le = fifo->mask - fifo->rptr[1] + 1; |
| 147 | |
| 148 | if (max_frames > le) |
| 149 | max_frames = le; |
| 150 | if (max_frames > lu) |
| 151 | max_frames = lu; |
| 152 | |
| 153 | *ofs = fifo->base + fifo->rptr[1]; |
| 154 | fifo->rptr[0] = fifo->rptr[1] = (fifo->rptr[1] + max_frames) & fifo->mask; |
| 155 | |
| 156 | return max_frames; |
| 157 | } |
| 158 | |
| 159 | |
| 160 | /* MultiFrame level split read/write */ |
| 161 | static bool |
| 162 | e1f_multiframe_write_prepare(struct e1_fifo *fifo, unsigned int *ofs) |
| 163 | { |
| 164 | unsigned int lf; |
| 165 | |
| 166 | lf = e1f_free_frames(fifo); |
| 167 | if (lf < 16) |
| 168 | return false; |
| 169 | |
| 170 | *ofs = fifo->base + fifo->wptr[1]; |
| 171 | fifo->wptr[1] = (fifo->wptr[1] + 16) & fifo->mask; |
| 172 | |
| 173 | return true; |
| 174 | } |
| 175 | |
| 176 | static void |
| 177 | e1f_multiframe_write_commit(struct e1_fifo *fifo) |
| 178 | { |
| 179 | fifo->wptr[0] = (fifo->wptr[0] + 16) & fifo->mask; |
| 180 | } |
| 181 | |
| 182 | static bool |
| 183 | e1f_multiframe_read_peek(struct e1_fifo *fifo, unsigned int *ofs) |
| 184 | { |
| 185 | unsigned int lu; |
| 186 | |
| 187 | lu = e1f_unseen_frames(fifo); |
| 188 | if (lu < 16) |
| 189 | return false; |
| 190 | |
| 191 | *ofs = fifo->base + fifo->rptr[1]; |
| 192 | fifo->rptr[1] = (fifo->rptr[1] + 16) & fifo->mask; |
| 193 | |
| 194 | return true; |
| 195 | } |
| 196 | |
| 197 | static void |
| 198 | e1f_multiframe_read_discard(struct e1_fifo *fifo) |
| 199 | { |
| 200 | fifo->rptr[0] = (fifo->rptr[0] + 16) & fifo->mask; |
| 201 | } |
| 202 | |
| 203 | static void |
| 204 | e1f_multiframe_empty(struct e1_fifo *fifo) |
| 205 | { |
| 206 | fifo->rptr[0] = fifo->rptr[1] = (fifo->wptr[0] & ~15); |
| 207 | } |
| 208 | |
| 209 | |
| 210 | |
| 211 | // Main logic |
| 212 | // ---------- |
| 213 | |
| 214 | enum e1_pipe_state { |
Harald Welte | 30fc560 | 2020-12-14 15:56:28 +0100 | [diff] [blame] | 215 | IDLE = 0, /* not yet initialized */ |
| 216 | BOOT = 1, /* after e1_init(), regiters are programmed */ |
| 217 | RUN = 2, /* normal operation */ |
| 218 | RECOVER = 3, /* after underflow, overflow or alignment error */ |
Sylvain Munaut | bc9f5c4 | 2020-09-14 10:22:29 +0200 | [diff] [blame] | 219 | }; |
| 220 | |
| 221 | static struct { |
| 222 | struct { |
| 223 | uint32_t cr; |
| 224 | struct e1_fifo fifo; |
| 225 | int in_flight; |
| 226 | enum e1_pipe_state state; |
| 227 | } rx; |
| 228 | |
| 229 | struct { |
| 230 | uint32_t cr; |
| 231 | struct e1_fifo fifo; |
| 232 | int in_flight; |
| 233 | enum e1_pipe_state state; |
| 234 | } tx; |
| 235 | } g_e1; |
| 236 | |
| 237 | |
| 238 | |
| 239 | |
| 240 | void |
| 241 | e1_init(bool clk_mode) |
| 242 | { |
| 243 | /* Global state init */ |
| 244 | memset(&g_e1, 0x00, sizeof(g_e1)); |
| 245 | |
| 246 | /* Reset FIFOs */ |
| 247 | e1f_reset(&g_e1.rx.fifo, 0, 128); |
| 248 | e1f_reset(&g_e1.tx.fifo, 128, 128); |
| 249 | |
| 250 | /* Enable Rx */ |
| 251 | g_e1.rx.cr = E1_RX_CR_OVFL_CLR | |
| 252 | E1_RX_CR_MODE_MFA | |
| 253 | E1_RX_CR_ENABLE; |
| 254 | e1_regs->rx.csr = g_e1.rx.cr; |
| 255 | |
| 256 | /* Enable Tx */ |
| 257 | g_e1.tx.cr = E1_TX_CR_UNFL_CLR | |
| 258 | (clk_mode ? E1_TX_CR_TICK_REMOTE : E1_TX_CR_TICK_LOCAL) | |
| 259 | E1_TX_CR_MODE_TS0_CRC_E | |
| 260 | E1_TX_CR_ENABLE; |
| 261 | e1_regs->tx.csr = g_e1.tx.cr; |
| 262 | |
| 263 | /* State */ |
| 264 | g_e1.rx.state = BOOT; |
| 265 | g_e1.tx.state = BOOT; |
| 266 | } |
| 267 | |
| 268 | |
| 269 | #include "dma.h" |
| 270 | |
| 271 | unsigned int |
Harald Welte | daff4f6 | 2020-12-14 17:39:23 +0100 | [diff] [blame] | 272 | e1_rx_need_data(unsigned int usb_addr, unsigned int max_frames, unsigned int *pos) |
Sylvain Munaut | bc9f5c4 | 2020-09-14 10:22:29 +0200 | [diff] [blame] | 273 | { |
| 274 | unsigned int ofs; |
| 275 | int tot_frames = 0; |
| 276 | int n_frames; |
| 277 | |
| 278 | while (max_frames) { |
| 279 | /* Get some data from the FIFO */ |
| 280 | n_frames = e1f_frame_read(&g_e1.rx.fifo, &ofs, max_frames); |
| 281 | if (!n_frames) |
| 282 | break; |
| 283 | |
Harald Welte | daff4f6 | 2020-12-14 17:39:23 +0100 | [diff] [blame] | 284 | /* Give pos */ |
| 285 | if (pos) { |
| 286 | *pos = ofs & g_e1.rx.fifo.mask; |
| 287 | pos = NULL; |
| 288 | } |
| 289 | |
Sylvain Munaut | bc9f5c4 | 2020-09-14 10:22:29 +0200 | [diff] [blame] | 290 | /* Copy from FIFO to USB */ |
| 291 | dma_exec(e1f_ofs_to_dma(ofs), usb_addr, n_frames * (32 / 4), false, NULL, NULL); |
| 292 | |
| 293 | /* Prepare Next */ |
| 294 | usb_addr += n_frames * (32 / 4); |
| 295 | max_frames -= n_frames; |
| 296 | tot_frames += n_frames; |
| 297 | |
| 298 | /* Wait for DMA completion */ |
| 299 | while (dma_poll()); |
| 300 | } |
| 301 | |
| 302 | return tot_frames; |
| 303 | } |
| 304 | |
| 305 | unsigned int |
| 306 | e1_tx_feed_data(unsigned int usb_addr, unsigned int frames) |
| 307 | { |
| 308 | unsigned int ofs; |
| 309 | int n_frames; |
| 310 | |
| 311 | while (frames) { |
| 312 | /* Get some space in FIFO */ |
| 313 | n_frames = e1f_frame_write(&g_e1.tx.fifo, &ofs, frames); |
| 314 | if (!n_frames) { |
| 315 | printf("[!] TX FIFO Overflow %d %d\n", frames, n_frames); |
| 316 | break; |
| 317 | } |
| 318 | |
| 319 | /* Copy from USB to FIFO */ |
| 320 | dma_exec(e1f_ofs_to_dma(ofs), usb_addr, n_frames * (32 / 4), true, NULL, NULL); |
| 321 | |
| 322 | /* Prepare next */ |
| 323 | usb_addr += n_frames * (32 / 4); |
| 324 | frames -= n_frames; |
| 325 | |
| 326 | /* Wait for DMA completion */ |
| 327 | while (dma_poll()); |
| 328 | } |
| 329 | |
| 330 | return frames; |
| 331 | } |
| 332 | |
| 333 | unsigned int |
| 334 | e1_tx_level(void) |
| 335 | { |
| 336 | return e1f_valid_frames(&g_e1.tx.fifo); |
| 337 | } |
| 338 | |
| 339 | unsigned int |
| 340 | e1_rx_level(void) |
| 341 | { |
| 342 | return e1f_valid_frames(&g_e1.rx.fifo); |
| 343 | } |
| 344 | |
| 345 | void |
| 346 | e1_poll(void) |
| 347 | { |
| 348 | uint32_t bd; |
| 349 | unsigned int ofs; |
| 350 | |
| 351 | /* Active ? */ |
| 352 | if ((g_e1.rx.state == IDLE) && (g_e1.tx.state == IDLE)) |
| 353 | return; |
| 354 | |
| 355 | /* HACK: LED link status */ |
Harald Welte | 5276567 | 2020-12-15 18:35:42 +0100 | [diff] [blame] | 356 | if (e1_regs->rx.csr & E1_RX_SR_ALIGNED) { |
| 357 | e1_platform_led_set(0, E1P_LED_GREEN, E1P_LED_ST_ON); |
Sylvain Munaut | bc9f5c4 | 2020-09-14 10:22:29 +0200 | [diff] [blame] | 358 | led_color(0, 48, 0); |
Harald Welte | 5276567 | 2020-12-15 18:35:42 +0100 | [diff] [blame] | 359 | } else { |
| 360 | e1_platform_led_set(0, E1P_LED_GREEN, E1P_LED_ST_BLINK); |
| 361 | /* TODO: completely off if rx tick counter not incrementing */ |
Sylvain Munaut | bc9f5c4 | 2020-09-14 10:22:29 +0200 | [diff] [blame] | 362 | led_color(48, 0, 0); |
Harald Welte | 5276567 | 2020-12-15 18:35:42 +0100 | [diff] [blame] | 363 | } |
Sylvain Munaut | bc9f5c4 | 2020-09-14 10:22:29 +0200 | [diff] [blame] | 364 | |
| 365 | /* Recover any done TX BD */ |
| 366 | while ( (bd = e1_regs->tx.bd) & E1_BD_VALID ) { |
| 367 | e1f_multiframe_read_discard(&g_e1.tx.fifo); |
| 368 | g_e1.tx.in_flight--; |
| 369 | } |
| 370 | |
| 371 | /* Recover any done RX BD */ |
| 372 | while ( (bd = e1_regs->rx.bd) & E1_BD_VALID ) { |
| 373 | /* FIXME: CRC status ? */ |
| 374 | e1f_multiframe_write_commit(&g_e1.rx.fifo); |
| 375 | if ((bd & (E1_BD_CRC0 | E1_BD_CRC1)) != (E1_BD_CRC0 | E1_BD_CRC1)) |
| 376 | printf("b: %03x\n", bd); |
| 377 | g_e1.rx.in_flight--; |
| 378 | } |
| 379 | |
| 380 | /* Boot procedure */ |
| 381 | if (g_e1.tx.state == BOOT) { |
| 382 | if (e1f_unseen_frames(&g_e1.tx.fifo) < (16 * 5)) |
| 383 | return; |
| 384 | /* HACK: LED flow status */ |
| 385 | led_blink(true, 200, 1000); |
| 386 | led_breathe(true, 100, 200); |
| 387 | } |
| 388 | |
| 389 | /* Handle RX */ |
| 390 | /* Misalign ? */ |
| 391 | if (g_e1.rx.state == RUN) { |
| 392 | if (!(e1_regs->rx.csr & E1_RX_SR_ALIGNED)) { |
| 393 | printf("[!] E1 rx misalign\n"); |
| 394 | g_e1.rx.state = RECOVER; |
| 395 | } |
| 396 | } |
| 397 | |
| 398 | /* Overflow ? */ |
| 399 | if (g_e1.rx.state == RUN) { |
| 400 | if (e1_regs->rx.csr & E1_RX_SR_OVFL) { |
| 401 | printf("[!] E1 overflow %d\n", g_e1.rx.in_flight); |
| 402 | g_e1.rx.state = RECOVER; |
| 403 | } |
| 404 | } |
| 405 | |
| 406 | /* Recover ready ? */ |
| 407 | if (g_e1.rx.state == RECOVER) { |
| 408 | if (g_e1.rx.in_flight != 0) |
| 409 | goto done_rx; |
| 410 | e1f_multiframe_empty(&g_e1.rx.fifo); |
| 411 | } |
| 412 | |
| 413 | /* Fill new RX BD */ |
| 414 | while (g_e1.rx.in_flight < 4) { |
| 415 | if (!e1f_multiframe_write_prepare(&g_e1.rx.fifo, &ofs)) |
| 416 | break; |
| 417 | e1_regs->rx.bd = e1f_ofs_to_mf(ofs); |
| 418 | g_e1.rx.in_flight++; |
| 419 | } |
| 420 | |
| 421 | /* Clear overflow if needed */ |
| 422 | if (g_e1.rx.state != RUN) { |
| 423 | e1_regs->rx.csr = g_e1.rx.cr | E1_RX_CR_OVFL_CLR; |
| 424 | g_e1.rx.state = RUN; |
| 425 | } |
| 426 | done_rx: |
| 427 | |
| 428 | /* Handle TX */ |
| 429 | /* Underflow ? */ |
| 430 | if (g_e1.tx.state == RUN) { |
| 431 | if (e1_regs->tx.csr & E1_TX_SR_UNFL) { |
| 432 | printf("[!] E1 underflow %d\n", g_e1.tx.in_flight); |
| 433 | g_e1.tx.state = RECOVER; |
| 434 | } |
| 435 | } |
| 436 | |
| 437 | /* Recover ready ? */ |
| 438 | if (g_e1.tx.state == RECOVER) { |
| 439 | if (e1f_unseen_frames(&g_e1.tx.fifo) < (16 * 5)) |
| 440 | return; |
| 441 | } |
| 442 | |
| 443 | /* Fill new TX BD */ |
| 444 | while (g_e1.tx.in_flight < 4) { |
| 445 | if (!e1f_multiframe_read_peek(&g_e1.tx.fifo, &ofs)) |
| 446 | break; |
| 447 | e1_regs->tx.bd = e1f_ofs_to_mf(ofs); |
| 448 | g_e1.tx.in_flight++; |
| 449 | } |
| 450 | |
| 451 | /* Clear underflow if needed */ |
| 452 | if (g_e1.tx.state != RUN) { |
| 453 | e1_regs->tx.csr = g_e1.tx.cr | E1_TX_CR_UNFL_CLR; |
| 454 | g_e1.tx.state = RUN; |
| 455 | } |
| 456 | } |
| 457 | |
| 458 | void |
| 459 | e1_debug_print(bool data) |
| 460 | { |
| 461 | volatile uint8_t *p; |
| 462 | |
| 463 | puts("E1\n"); |
| 464 | printf("CSR: Rx %04x / Tx %04x\n", e1_regs->rx.csr, e1_regs->tx.csr); |
| 465 | printf("InF: Rx %d / Tx %d\n", g_e1.rx.in_flight, g_e1.tx.in_flight); |
| 466 | printf("Sta: Rx %d / Tx %d\n", g_e1.rx.state, g_e1.tx.state); |
| 467 | |
| 468 | e1f_debug(&g_e1.rx.fifo, "Rx FIFO"); |
| 469 | e1f_debug(&g_e1.tx.fifo, "Tx FIFO"); |
| 470 | |
| 471 | if (data) { |
| 472 | puts("\nE1 Data\n"); |
| 473 | for (int f=0; f<16; f++) { |
| 474 | p = e1_data_ptr(0, f, 0); |
| 475 | for (int ts=0; ts<32; ts++) |
| 476 | printf(" %02x", p[ts]); |
| 477 | printf("\n"); |
| 478 | } |
| 479 | } |
| 480 | } |