Sylvain Munaut | bd83e53 | 2020-09-15 22:11:29 +0200 | [diff] [blame] | 1 | /* |
| 2 | * i2c_master_wb.v |
| 3 | * |
| 4 | * vim: ts=4 sw=4 |
| 5 | * |
| 6 | * Wishbone wrapper with optional buffering for i2c_master core |
| 7 | * |
| 8 | * Copyright (C) 2019-2020 Sylvain Munaut <tnt@246tNt.com> |
| 9 | * SPDX-License-Identifier: CERN-OHL-P-2.0 |
| 10 | */ |
| 11 | |
| 12 | `default_nettype none |
| 13 | |
| 14 | module i2c_master_wb #( |
| 15 | parameter integer DW = 3, |
| 16 | parameter integer FIFO_DEPTH = 0 |
| 17 | )( |
| 18 | // IOs |
| 19 | output wire scl_oe, |
| 20 | output wire sda_oe, |
| 21 | input wire sda_i, |
| 22 | |
| 23 | // Wishbone |
| 24 | output wire [31:0] wb_rdata, |
| 25 | input wire [31:0] wb_wdata, |
| 26 | input wire wb_we, |
| 27 | input wire wb_cyc, |
| 28 | output wire wb_ack, |
| 29 | |
| 30 | output wire ready, |
| 31 | |
| 32 | // Clock / Reset |
| 33 | input wire clk, |
| 34 | input wire rst |
| 35 | ); |
| 36 | |
| 37 | // Signals |
| 38 | // ------- |
| 39 | |
| 40 | wire [7:0] data_in; |
| 41 | wire ack_in; |
| 42 | wire [1:0] cmd; |
| 43 | wire stb; |
| 44 | wire [7:0] data_out; |
| 45 | wire ack_out; |
| 46 | |
| 47 | |
| 48 | // Core |
| 49 | // ---- |
| 50 | |
| 51 | i2c_master #( |
| 52 | .DW(DW) |
| 53 | ) core_I ( |
| 54 | .scl_oe (scl_oe), |
| 55 | .sda_oe (sda_oe), |
| 56 | .sda_i (sda_i), |
| 57 | .data_in (data_in), |
| 58 | .ack_in (ack_in), |
| 59 | .cmd (cmd), |
| 60 | .stb (stb), |
| 61 | .data_out(data_out), |
| 62 | .ack_out (ack_out), |
| 63 | .ready (ready), |
| 64 | .clk (clk), |
| 65 | .rst (rst) |
| 66 | ); |
| 67 | |
| 68 | |
| 69 | // Bus interface (no buffer) |
| 70 | // ------------- |
| 71 | |
| 72 | if (FIFO_DEPTH == 0) begin |
| 73 | // No buffer |
| 74 | assign wb_rdata = wb_cyc ? { ready, 22'd0, ack_out, data_out } : 32'h00000000; |
| 75 | |
| 76 | assign cmd = wb_wdata[13:12]; |
| 77 | assign ack_in = wb_wdata[8]; |
| 78 | assign data_in = wb_wdata[7:0]; |
| 79 | |
| 80 | assign stb = wb_cyc & wb_we; |
| 81 | |
| 82 | assign wb_ack = wb_cyc; |
| 83 | end |
| 84 | |
| 85 | |
| 86 | // Bus interface (FIFO) |
| 87 | // ------------- |
| 88 | |
| 89 | if (FIFO_DEPTH > 0) begin |
| 90 | |
| 91 | // Signals |
| 92 | // ------- |
| 93 | |
| 94 | |
| 95 | // FIFOs |
| 96 | // ----- |
| 97 | |
| 98 | |
| 99 | |
| 100 | end |
| 101 | |
| 102 | endmodule |