| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief Instance description for EVSYS |
| 5 | * |
| Harald Welte | 9bb8bfe | 2019-05-17 16:10:00 +0200 | [diff] [blame] | 6 | * Copyright (c) 2019 Microchip Technology Inc.
|
| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * SPDX-License-Identifier: Apache-2.0 |
| 13 | * |
| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may |
| 15 | * not use this file except in compliance with the License. |
| 16 | * You may obtain a copy of the Licence at |
| 17 | * |
| 18 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 19 | * |
| 20 | * Unless required by applicable law or agreed to in writing, software |
| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 23 | * See the License for the specific language governing permissions and |
| 24 | * limitations under the License. |
| 25 | * |
| 26 | * \asf_license_stop |
| 27 | * |
| 28 | */ |
| 29 | |
| 30 | #ifndef _SAME54_EVSYS_INSTANCE_ |
| 31 | #define _SAME54_EVSYS_INSTANCE_ |
| 32 | |
| 33 | /* ========== Register definition for EVSYS peripheral ========== */ |
| 34 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 35 | #define REG_EVSYS_CTRLA (0x4100E000) /**< \brief (EVSYS) Control */ |
| 36 | #define REG_EVSYS_SWEVT (0x4100E004) /**< \brief (EVSYS) Software Event */ |
| 37 | #define REG_EVSYS_PRICTRL (0x4100E008) /**< \brief (EVSYS) Priority Control */ |
| 38 | #define REG_EVSYS_INTPEND (0x4100E010) /**< \brief (EVSYS) Channel Pending Interrupt */ |
| 39 | #define REG_EVSYS_INTSTATUS (0x4100E014) /**< \brief (EVSYS) Interrupt Status */ |
| 40 | #define REG_EVSYS_BUSYCH (0x4100E018) /**< \brief (EVSYS) Busy Channels */ |
| 41 | #define REG_EVSYS_READYUSR (0x4100E01C) /**< \brief (EVSYS) Ready Users */ |
| 42 | #define REG_EVSYS_CHANNEL0 (0x4100E020) /**< \brief (EVSYS) Channel 0 Control */ |
| 43 | #define REG_EVSYS_CHINTENCLR0 (0x4100E024) /**< \brief (EVSYS) Channel 0 Interrupt Enable Clear */ |
| 44 | #define REG_EVSYS_CHINTENSET0 (0x4100E025) /**< \brief (EVSYS) Channel 0 Interrupt Enable Set */ |
| 45 | #define REG_EVSYS_CHINTFLAG0 (0x4100E026) /**< \brief (EVSYS) Channel 0 Interrupt Flag Status and Clear */ |
| 46 | #define REG_EVSYS_CHSTATUS0 (0x4100E027) /**< \brief (EVSYS) Channel 0 Status */ |
| 47 | #define REG_EVSYS_CHANNEL1 (0x4100E028) /**< \brief (EVSYS) Channel 1 Control */ |
| 48 | #define REG_EVSYS_CHINTENCLR1 (0x4100E02C) /**< \brief (EVSYS) Channel 1 Interrupt Enable Clear */ |
| 49 | #define REG_EVSYS_CHINTENSET1 (0x4100E02D) /**< \brief (EVSYS) Channel 1 Interrupt Enable Set */ |
| 50 | #define REG_EVSYS_CHINTFLAG1 (0x4100E02E) /**< \brief (EVSYS) Channel 1 Interrupt Flag Status and Clear */ |
| 51 | #define REG_EVSYS_CHSTATUS1 (0x4100E02F) /**< \brief (EVSYS) Channel 1 Status */ |
| 52 | #define REG_EVSYS_CHANNEL2 (0x4100E030) /**< \brief (EVSYS) Channel 2 Control */ |
| 53 | #define REG_EVSYS_CHINTENCLR2 (0x4100E034) /**< \brief (EVSYS) Channel 2 Interrupt Enable Clear */ |
| 54 | #define REG_EVSYS_CHINTENSET2 (0x4100E035) /**< \brief (EVSYS) Channel 2 Interrupt Enable Set */ |
| 55 | #define REG_EVSYS_CHINTFLAG2 (0x4100E036) /**< \brief (EVSYS) Channel 2 Interrupt Flag Status and Clear */ |
| 56 | #define REG_EVSYS_CHSTATUS2 (0x4100E037) /**< \brief (EVSYS) Channel 2 Status */ |
| 57 | #define REG_EVSYS_CHANNEL3 (0x4100E038) /**< \brief (EVSYS) Channel 3 Control */ |
| 58 | #define REG_EVSYS_CHINTENCLR3 (0x4100E03C) /**< \brief (EVSYS) Channel 3 Interrupt Enable Clear */ |
| 59 | #define REG_EVSYS_CHINTENSET3 (0x4100E03D) /**< \brief (EVSYS) Channel 3 Interrupt Enable Set */ |
| 60 | #define REG_EVSYS_CHINTFLAG3 (0x4100E03E) /**< \brief (EVSYS) Channel 3 Interrupt Flag Status and Clear */ |
| 61 | #define REG_EVSYS_CHSTATUS3 (0x4100E03F) /**< \brief (EVSYS) Channel 3 Status */ |
| 62 | #define REG_EVSYS_CHANNEL4 (0x4100E040) /**< \brief (EVSYS) Channel 4 Control */ |
| 63 | #define REG_EVSYS_CHINTENCLR4 (0x4100E044) /**< \brief (EVSYS) Channel 4 Interrupt Enable Clear */ |
| 64 | #define REG_EVSYS_CHINTENSET4 (0x4100E045) /**< \brief (EVSYS) Channel 4 Interrupt Enable Set */ |
| 65 | #define REG_EVSYS_CHINTFLAG4 (0x4100E046) /**< \brief (EVSYS) Channel 4 Interrupt Flag Status and Clear */ |
| 66 | #define REG_EVSYS_CHSTATUS4 (0x4100E047) /**< \brief (EVSYS) Channel 4 Status */ |
| 67 | #define REG_EVSYS_CHANNEL5 (0x4100E048) /**< \brief (EVSYS) Channel 5 Control */ |
| 68 | #define REG_EVSYS_CHINTENCLR5 (0x4100E04C) /**< \brief (EVSYS) Channel 5 Interrupt Enable Clear */ |
| 69 | #define REG_EVSYS_CHINTENSET5 (0x4100E04D) /**< \brief (EVSYS) Channel 5 Interrupt Enable Set */ |
| 70 | #define REG_EVSYS_CHINTFLAG5 (0x4100E04E) /**< \brief (EVSYS) Channel 5 Interrupt Flag Status and Clear */ |
| 71 | #define REG_EVSYS_CHSTATUS5 (0x4100E04F) /**< \brief (EVSYS) Channel 5 Status */ |
| 72 | #define REG_EVSYS_CHANNEL6 (0x4100E050) /**< \brief (EVSYS) Channel 6 Control */ |
| 73 | #define REG_EVSYS_CHINTENCLR6 (0x4100E054) /**< \brief (EVSYS) Channel 6 Interrupt Enable Clear */ |
| 74 | #define REG_EVSYS_CHINTENSET6 (0x4100E055) /**< \brief (EVSYS) Channel 6 Interrupt Enable Set */ |
| 75 | #define REG_EVSYS_CHINTFLAG6 (0x4100E056) /**< \brief (EVSYS) Channel 6 Interrupt Flag Status and Clear */ |
| 76 | #define REG_EVSYS_CHSTATUS6 (0x4100E057) /**< \brief (EVSYS) Channel 6 Status */ |
| 77 | #define REG_EVSYS_CHANNEL7 (0x4100E058) /**< \brief (EVSYS) Channel 7 Control */ |
| 78 | #define REG_EVSYS_CHINTENCLR7 (0x4100E05C) /**< \brief (EVSYS) Channel 7 Interrupt Enable Clear */ |
| 79 | #define REG_EVSYS_CHINTENSET7 (0x4100E05D) /**< \brief (EVSYS) Channel 7 Interrupt Enable Set */ |
| 80 | #define REG_EVSYS_CHINTFLAG7 (0x4100E05E) /**< \brief (EVSYS) Channel 7 Interrupt Flag Status and Clear */ |
| 81 | #define REG_EVSYS_CHSTATUS7 (0x4100E05F) /**< \brief (EVSYS) Channel 7 Status */ |
| 82 | #define REG_EVSYS_CHANNEL8 (0x4100E060) /**< \brief (EVSYS) Channel 8 Control */ |
| 83 | #define REG_EVSYS_CHINTENCLR8 (0x4100E064) /**< \brief (EVSYS) Channel 8 Interrupt Enable Clear */ |
| 84 | #define REG_EVSYS_CHINTENSET8 (0x4100E065) /**< \brief (EVSYS) Channel 8 Interrupt Enable Set */ |
| 85 | #define REG_EVSYS_CHINTFLAG8 (0x4100E066) /**< \brief (EVSYS) Channel 8 Interrupt Flag Status and Clear */ |
| 86 | #define REG_EVSYS_CHSTATUS8 (0x4100E067) /**< \brief (EVSYS) Channel 8 Status */ |
| 87 | #define REG_EVSYS_CHANNEL9 (0x4100E068) /**< \brief (EVSYS) Channel 9 Control */ |
| 88 | #define REG_EVSYS_CHINTENCLR9 (0x4100E06C) /**< \brief (EVSYS) Channel 9 Interrupt Enable Clear */ |
| 89 | #define REG_EVSYS_CHINTENSET9 (0x4100E06D) /**< \brief (EVSYS) Channel 9 Interrupt Enable Set */ |
| 90 | #define REG_EVSYS_CHINTFLAG9 (0x4100E06E) /**< \brief (EVSYS) Channel 9 Interrupt Flag Status and Clear */ |
| 91 | #define REG_EVSYS_CHSTATUS9 (0x4100E06F) /**< \brief (EVSYS) Channel 9 Status */ |
| 92 | #define REG_EVSYS_CHANNEL10 (0x4100E070) /**< \brief (EVSYS) Channel 10 Control */ |
| 93 | #define REG_EVSYS_CHINTENCLR10 (0x4100E074) /**< \brief (EVSYS) Channel 10 Interrupt Enable Clear */ |
| 94 | #define REG_EVSYS_CHINTENSET10 (0x4100E075) /**< \brief (EVSYS) Channel 10 Interrupt Enable Set */ |
| 95 | #define REG_EVSYS_CHINTFLAG10 (0x4100E076) /**< \brief (EVSYS) Channel 10 Interrupt Flag Status and Clear */ |
| 96 | #define REG_EVSYS_CHSTATUS10 (0x4100E077) /**< \brief (EVSYS) Channel 10 Status */ |
| 97 | #define REG_EVSYS_CHANNEL11 (0x4100E078) /**< \brief (EVSYS) Channel 11 Control */ |
| 98 | #define REG_EVSYS_CHINTENCLR11 (0x4100E07C) /**< \brief (EVSYS) Channel 11 Interrupt Enable Clear */ |
| 99 | #define REG_EVSYS_CHINTENSET11 (0x4100E07D) /**< \brief (EVSYS) Channel 11 Interrupt Enable Set */ |
| 100 | #define REG_EVSYS_CHINTFLAG11 (0x4100E07E) /**< \brief (EVSYS) Channel 11 Interrupt Flag Status and Clear */ |
| 101 | #define REG_EVSYS_CHSTATUS11 (0x4100E07F) /**< \brief (EVSYS) Channel 11 Status */ |
| 102 | #define REG_EVSYS_CHANNEL12 (0x4100E080) /**< \brief (EVSYS) Channel 12 Control */ |
| 103 | #define REG_EVSYS_CHINTENCLR12 (0x4100E084) /**< \brief (EVSYS) Channel 12 Interrupt Enable Clear */ |
| 104 | #define REG_EVSYS_CHINTENSET12 (0x4100E085) /**< \brief (EVSYS) Channel 12 Interrupt Enable Set */ |
| 105 | #define REG_EVSYS_CHINTFLAG12 (0x4100E086) /**< \brief (EVSYS) Channel 12 Interrupt Flag Status and Clear */ |
| 106 | #define REG_EVSYS_CHSTATUS12 (0x4100E087) /**< \brief (EVSYS) Channel 12 Status */ |
| 107 | #define REG_EVSYS_CHANNEL13 (0x4100E088) /**< \brief (EVSYS) Channel 13 Control */ |
| 108 | #define REG_EVSYS_CHINTENCLR13 (0x4100E08C) /**< \brief (EVSYS) Channel 13 Interrupt Enable Clear */ |
| 109 | #define REG_EVSYS_CHINTENSET13 (0x4100E08D) /**< \brief (EVSYS) Channel 13 Interrupt Enable Set */ |
| 110 | #define REG_EVSYS_CHINTFLAG13 (0x4100E08E) /**< \brief (EVSYS) Channel 13 Interrupt Flag Status and Clear */ |
| 111 | #define REG_EVSYS_CHSTATUS13 (0x4100E08F) /**< \brief (EVSYS) Channel 13 Status */ |
| 112 | #define REG_EVSYS_CHANNEL14 (0x4100E090) /**< \brief (EVSYS) Channel 14 Control */ |
| 113 | #define REG_EVSYS_CHINTENCLR14 (0x4100E094) /**< \brief (EVSYS) Channel 14 Interrupt Enable Clear */ |
| 114 | #define REG_EVSYS_CHINTENSET14 (0x4100E095) /**< \brief (EVSYS) Channel 14 Interrupt Enable Set */ |
| 115 | #define REG_EVSYS_CHINTFLAG14 (0x4100E096) /**< \brief (EVSYS) Channel 14 Interrupt Flag Status and Clear */ |
| 116 | #define REG_EVSYS_CHSTATUS14 (0x4100E097) /**< \brief (EVSYS) Channel 14 Status */ |
| 117 | #define REG_EVSYS_CHANNEL15 (0x4100E098) /**< \brief (EVSYS) Channel 15 Control */ |
| 118 | #define REG_EVSYS_CHINTENCLR15 (0x4100E09C) /**< \brief (EVSYS) Channel 15 Interrupt Enable Clear */ |
| 119 | #define REG_EVSYS_CHINTENSET15 (0x4100E09D) /**< \brief (EVSYS) Channel 15 Interrupt Enable Set */ |
| 120 | #define REG_EVSYS_CHINTFLAG15 (0x4100E09E) /**< \brief (EVSYS) Channel 15 Interrupt Flag Status and Clear */ |
| 121 | #define REG_EVSYS_CHSTATUS15 (0x4100E09F) /**< \brief (EVSYS) Channel 15 Status */ |
| 122 | #define REG_EVSYS_CHANNEL16 (0x4100E0A0) /**< \brief (EVSYS) Channel 16 Control */ |
| 123 | #define REG_EVSYS_CHINTENCLR16 (0x4100E0A4) /**< \brief (EVSYS) Channel 16 Interrupt Enable Clear */ |
| 124 | #define REG_EVSYS_CHINTENSET16 (0x4100E0A5) /**< \brief (EVSYS) Channel 16 Interrupt Enable Set */ |
| 125 | #define REG_EVSYS_CHINTFLAG16 (0x4100E0A6) /**< \brief (EVSYS) Channel 16 Interrupt Flag Status and Clear */ |
| 126 | #define REG_EVSYS_CHSTATUS16 (0x4100E0A7) /**< \brief (EVSYS) Channel 16 Status */ |
| 127 | #define REG_EVSYS_CHANNEL17 (0x4100E0A8) /**< \brief (EVSYS) Channel 17 Control */ |
| 128 | #define REG_EVSYS_CHINTENCLR17 (0x4100E0AC) /**< \brief (EVSYS) Channel 17 Interrupt Enable Clear */ |
| 129 | #define REG_EVSYS_CHINTENSET17 (0x4100E0AD) /**< \brief (EVSYS) Channel 17 Interrupt Enable Set */ |
| 130 | #define REG_EVSYS_CHINTFLAG17 (0x4100E0AE) /**< \brief (EVSYS) Channel 17 Interrupt Flag Status and Clear */ |
| 131 | #define REG_EVSYS_CHSTATUS17 (0x4100E0AF) /**< \brief (EVSYS) Channel 17 Status */ |
| 132 | #define REG_EVSYS_CHANNEL18 (0x4100E0B0) /**< \brief (EVSYS) Channel 18 Control */ |
| 133 | #define REG_EVSYS_CHINTENCLR18 (0x4100E0B4) /**< \brief (EVSYS) Channel 18 Interrupt Enable Clear */ |
| 134 | #define REG_EVSYS_CHINTENSET18 (0x4100E0B5) /**< \brief (EVSYS) Channel 18 Interrupt Enable Set */ |
| 135 | #define REG_EVSYS_CHINTFLAG18 (0x4100E0B6) /**< \brief (EVSYS) Channel 18 Interrupt Flag Status and Clear */ |
| 136 | #define REG_EVSYS_CHSTATUS18 (0x4100E0B7) /**< \brief (EVSYS) Channel 18 Status */ |
| 137 | #define REG_EVSYS_CHANNEL19 (0x4100E0B8) /**< \brief (EVSYS) Channel 19 Control */ |
| 138 | #define REG_EVSYS_CHINTENCLR19 (0x4100E0BC) /**< \brief (EVSYS) Channel 19 Interrupt Enable Clear */ |
| 139 | #define REG_EVSYS_CHINTENSET19 (0x4100E0BD) /**< \brief (EVSYS) Channel 19 Interrupt Enable Set */ |
| 140 | #define REG_EVSYS_CHINTFLAG19 (0x4100E0BE) /**< \brief (EVSYS) Channel 19 Interrupt Flag Status and Clear */ |
| 141 | #define REG_EVSYS_CHSTATUS19 (0x4100E0BF) /**< \brief (EVSYS) Channel 19 Status */ |
| 142 | #define REG_EVSYS_CHANNEL20 (0x4100E0C0) /**< \brief (EVSYS) Channel 20 Control */ |
| 143 | #define REG_EVSYS_CHINTENCLR20 (0x4100E0C4) /**< \brief (EVSYS) Channel 20 Interrupt Enable Clear */ |
| 144 | #define REG_EVSYS_CHINTENSET20 (0x4100E0C5) /**< \brief (EVSYS) Channel 20 Interrupt Enable Set */ |
| 145 | #define REG_EVSYS_CHINTFLAG20 (0x4100E0C6) /**< \brief (EVSYS) Channel 20 Interrupt Flag Status and Clear */ |
| 146 | #define REG_EVSYS_CHSTATUS20 (0x4100E0C7) /**< \brief (EVSYS) Channel 20 Status */ |
| 147 | #define REG_EVSYS_CHANNEL21 (0x4100E0C8) /**< \brief (EVSYS) Channel 21 Control */ |
| 148 | #define REG_EVSYS_CHINTENCLR21 (0x4100E0CC) /**< \brief (EVSYS) Channel 21 Interrupt Enable Clear */ |
| 149 | #define REG_EVSYS_CHINTENSET21 (0x4100E0CD) /**< \brief (EVSYS) Channel 21 Interrupt Enable Set */ |
| 150 | #define REG_EVSYS_CHINTFLAG21 (0x4100E0CE) /**< \brief (EVSYS) Channel 21 Interrupt Flag Status and Clear */ |
| 151 | #define REG_EVSYS_CHSTATUS21 (0x4100E0CF) /**< \brief (EVSYS) Channel 21 Status */ |
| 152 | #define REG_EVSYS_CHANNEL22 (0x4100E0D0) /**< \brief (EVSYS) Channel 22 Control */ |
| 153 | #define REG_EVSYS_CHINTENCLR22 (0x4100E0D4) /**< \brief (EVSYS) Channel 22 Interrupt Enable Clear */ |
| 154 | #define REG_EVSYS_CHINTENSET22 (0x4100E0D5) /**< \brief (EVSYS) Channel 22 Interrupt Enable Set */ |
| 155 | #define REG_EVSYS_CHINTFLAG22 (0x4100E0D6) /**< \brief (EVSYS) Channel 22 Interrupt Flag Status and Clear */ |
| 156 | #define REG_EVSYS_CHSTATUS22 (0x4100E0D7) /**< \brief (EVSYS) Channel 22 Status */ |
| 157 | #define REG_EVSYS_CHANNEL23 (0x4100E0D8) /**< \brief (EVSYS) Channel 23 Control */ |
| 158 | #define REG_EVSYS_CHINTENCLR23 (0x4100E0DC) /**< \brief (EVSYS) Channel 23 Interrupt Enable Clear */ |
| 159 | #define REG_EVSYS_CHINTENSET23 (0x4100E0DD) /**< \brief (EVSYS) Channel 23 Interrupt Enable Set */ |
| 160 | #define REG_EVSYS_CHINTFLAG23 (0x4100E0DE) /**< \brief (EVSYS) Channel 23 Interrupt Flag Status and Clear */ |
| 161 | #define REG_EVSYS_CHSTATUS23 (0x4100E0DF) /**< \brief (EVSYS) Channel 23 Status */ |
| 162 | #define REG_EVSYS_CHANNEL24 (0x4100E0E0) /**< \brief (EVSYS) Channel 24 Control */ |
| 163 | #define REG_EVSYS_CHINTENCLR24 (0x4100E0E4) /**< \brief (EVSYS) Channel 24 Interrupt Enable Clear */ |
| 164 | #define REG_EVSYS_CHINTENSET24 (0x4100E0E5) /**< \brief (EVSYS) Channel 24 Interrupt Enable Set */ |
| 165 | #define REG_EVSYS_CHINTFLAG24 (0x4100E0E6) /**< \brief (EVSYS) Channel 24 Interrupt Flag Status and Clear */ |
| 166 | #define REG_EVSYS_CHSTATUS24 (0x4100E0E7) /**< \brief (EVSYS) Channel 24 Status */ |
| 167 | #define REG_EVSYS_CHANNEL25 (0x4100E0E8) /**< \brief (EVSYS) Channel 25 Control */ |
| 168 | #define REG_EVSYS_CHINTENCLR25 (0x4100E0EC) /**< \brief (EVSYS) Channel 25 Interrupt Enable Clear */ |
| 169 | #define REG_EVSYS_CHINTENSET25 (0x4100E0ED) /**< \brief (EVSYS) Channel 25 Interrupt Enable Set */ |
| 170 | #define REG_EVSYS_CHINTFLAG25 (0x4100E0EE) /**< \brief (EVSYS) Channel 25 Interrupt Flag Status and Clear */ |
| 171 | #define REG_EVSYS_CHSTATUS25 (0x4100E0EF) /**< \brief (EVSYS) Channel 25 Status */ |
| 172 | #define REG_EVSYS_CHANNEL26 (0x4100E0F0) /**< \brief (EVSYS) Channel 26 Control */ |
| 173 | #define REG_EVSYS_CHINTENCLR26 (0x4100E0F4) /**< \brief (EVSYS) Channel 26 Interrupt Enable Clear */ |
| 174 | #define REG_EVSYS_CHINTENSET26 (0x4100E0F5) /**< \brief (EVSYS) Channel 26 Interrupt Enable Set */ |
| 175 | #define REG_EVSYS_CHINTFLAG26 (0x4100E0F6) /**< \brief (EVSYS) Channel 26 Interrupt Flag Status and Clear */ |
| 176 | #define REG_EVSYS_CHSTATUS26 (0x4100E0F7) /**< \brief (EVSYS) Channel 26 Status */ |
| 177 | #define REG_EVSYS_CHANNEL27 (0x4100E0F8) /**< \brief (EVSYS) Channel 27 Control */ |
| 178 | #define REG_EVSYS_CHINTENCLR27 (0x4100E0FC) /**< \brief (EVSYS) Channel 27 Interrupt Enable Clear */ |
| 179 | #define REG_EVSYS_CHINTENSET27 (0x4100E0FD) /**< \brief (EVSYS) Channel 27 Interrupt Enable Set */ |
| 180 | #define REG_EVSYS_CHINTFLAG27 (0x4100E0FE) /**< \brief (EVSYS) Channel 27 Interrupt Flag Status and Clear */ |
| 181 | #define REG_EVSYS_CHSTATUS27 (0x4100E0FF) /**< \brief (EVSYS) Channel 27 Status */ |
| 182 | #define REG_EVSYS_CHANNEL28 (0x4100E100) /**< \brief (EVSYS) Channel 28 Control */ |
| 183 | #define REG_EVSYS_CHINTENCLR28 (0x4100E104) /**< \brief (EVSYS) Channel 28 Interrupt Enable Clear */ |
| 184 | #define REG_EVSYS_CHINTENSET28 (0x4100E105) /**< \brief (EVSYS) Channel 28 Interrupt Enable Set */ |
| 185 | #define REG_EVSYS_CHINTFLAG28 (0x4100E106) /**< \brief (EVSYS) Channel 28 Interrupt Flag Status and Clear */ |
| 186 | #define REG_EVSYS_CHSTATUS28 (0x4100E107) /**< \brief (EVSYS) Channel 28 Status */ |
| 187 | #define REG_EVSYS_CHANNEL29 (0x4100E108) /**< \brief (EVSYS) Channel 29 Control */ |
| 188 | #define REG_EVSYS_CHINTENCLR29 (0x4100E10C) /**< \brief (EVSYS) Channel 29 Interrupt Enable Clear */ |
| 189 | #define REG_EVSYS_CHINTENSET29 (0x4100E10D) /**< \brief (EVSYS) Channel 29 Interrupt Enable Set */ |
| 190 | #define REG_EVSYS_CHINTFLAG29 (0x4100E10E) /**< \brief (EVSYS) Channel 29 Interrupt Flag Status and Clear */ |
| 191 | #define REG_EVSYS_CHSTATUS29 (0x4100E10F) /**< \brief (EVSYS) Channel 29 Status */ |
| 192 | #define REG_EVSYS_CHANNEL30 (0x4100E110) /**< \brief (EVSYS) Channel 30 Control */ |
| 193 | #define REG_EVSYS_CHINTENCLR30 (0x4100E114) /**< \brief (EVSYS) Channel 30 Interrupt Enable Clear */ |
| 194 | #define REG_EVSYS_CHINTENSET30 (0x4100E115) /**< \brief (EVSYS) Channel 30 Interrupt Enable Set */ |
| 195 | #define REG_EVSYS_CHINTFLAG30 (0x4100E116) /**< \brief (EVSYS) Channel 30 Interrupt Flag Status and Clear */ |
| 196 | #define REG_EVSYS_CHSTATUS30 (0x4100E117) /**< \brief (EVSYS) Channel 30 Status */ |
| 197 | #define REG_EVSYS_CHANNEL31 (0x4100E118) /**< \brief (EVSYS) Channel 31 Control */ |
| 198 | #define REG_EVSYS_CHINTENCLR31 (0x4100E11C) /**< \brief (EVSYS) Channel 31 Interrupt Enable Clear */ |
| 199 | #define REG_EVSYS_CHINTENSET31 (0x4100E11D) /**< \brief (EVSYS) Channel 31 Interrupt Enable Set */ |
| 200 | #define REG_EVSYS_CHINTFLAG31 (0x4100E11E) /**< \brief (EVSYS) Channel 31 Interrupt Flag Status and Clear */ |
| 201 | #define REG_EVSYS_CHSTATUS31 (0x4100E11F) /**< \brief (EVSYS) Channel 31 Status */ |
| 202 | #define REG_EVSYS_USER0 (0x4100E120) /**< \brief (EVSYS) User Multiplexer 0 */ |
| 203 | #define REG_EVSYS_USER1 (0x4100E124) /**< \brief (EVSYS) User Multiplexer 1 */ |
| 204 | #define REG_EVSYS_USER2 (0x4100E128) /**< \brief (EVSYS) User Multiplexer 2 */ |
| 205 | #define REG_EVSYS_USER3 (0x4100E12C) /**< \brief (EVSYS) User Multiplexer 3 */ |
| 206 | #define REG_EVSYS_USER4 (0x4100E130) /**< \brief (EVSYS) User Multiplexer 4 */ |
| 207 | #define REG_EVSYS_USER5 (0x4100E134) /**< \brief (EVSYS) User Multiplexer 5 */ |
| 208 | #define REG_EVSYS_USER6 (0x4100E138) /**< \brief (EVSYS) User Multiplexer 6 */ |
| 209 | #define REG_EVSYS_USER7 (0x4100E13C) /**< \brief (EVSYS) User Multiplexer 7 */ |
| 210 | #define REG_EVSYS_USER8 (0x4100E140) /**< \brief (EVSYS) User Multiplexer 8 */ |
| 211 | #define REG_EVSYS_USER9 (0x4100E144) /**< \brief (EVSYS) User Multiplexer 9 */ |
| 212 | #define REG_EVSYS_USER10 (0x4100E148) /**< \brief (EVSYS) User Multiplexer 10 */ |
| 213 | #define REG_EVSYS_USER11 (0x4100E14C) /**< \brief (EVSYS) User Multiplexer 11 */ |
| 214 | #define REG_EVSYS_USER12 (0x4100E150) /**< \brief (EVSYS) User Multiplexer 12 */ |
| 215 | #define REG_EVSYS_USER13 (0x4100E154) /**< \brief (EVSYS) User Multiplexer 13 */ |
| 216 | #define REG_EVSYS_USER14 (0x4100E158) /**< \brief (EVSYS) User Multiplexer 14 */ |
| 217 | #define REG_EVSYS_USER15 (0x4100E15C) /**< \brief (EVSYS) User Multiplexer 15 */ |
| 218 | #define REG_EVSYS_USER16 (0x4100E160) /**< \brief (EVSYS) User Multiplexer 16 */ |
| 219 | #define REG_EVSYS_USER17 (0x4100E164) /**< \brief (EVSYS) User Multiplexer 17 */ |
| 220 | #define REG_EVSYS_USER18 (0x4100E168) /**< \brief (EVSYS) User Multiplexer 18 */ |
| 221 | #define REG_EVSYS_USER19 (0x4100E16C) /**< \brief (EVSYS) User Multiplexer 19 */ |
| 222 | #define REG_EVSYS_USER20 (0x4100E170) /**< \brief (EVSYS) User Multiplexer 20 */ |
| 223 | #define REG_EVSYS_USER21 (0x4100E174) /**< \brief (EVSYS) User Multiplexer 21 */ |
| 224 | #define REG_EVSYS_USER22 (0x4100E178) /**< \brief (EVSYS) User Multiplexer 22 */ |
| 225 | #define REG_EVSYS_USER23 (0x4100E17C) /**< \brief (EVSYS) User Multiplexer 23 */ |
| 226 | #define REG_EVSYS_USER24 (0x4100E180) /**< \brief (EVSYS) User Multiplexer 24 */ |
| 227 | #define REG_EVSYS_USER25 (0x4100E184) /**< \brief (EVSYS) User Multiplexer 25 */ |
| 228 | #define REG_EVSYS_USER26 (0x4100E188) /**< \brief (EVSYS) User Multiplexer 26 */ |
| 229 | #define REG_EVSYS_USER27 (0x4100E18C) /**< \brief (EVSYS) User Multiplexer 27 */ |
| 230 | #define REG_EVSYS_USER28 (0x4100E190) /**< \brief (EVSYS) User Multiplexer 28 */ |
| 231 | #define REG_EVSYS_USER29 (0x4100E194) /**< \brief (EVSYS) User Multiplexer 29 */ |
| 232 | #define REG_EVSYS_USER30 (0x4100E198) /**< \brief (EVSYS) User Multiplexer 30 */ |
| 233 | #define REG_EVSYS_USER31 (0x4100E19C) /**< \brief (EVSYS) User Multiplexer 31 */ |
| 234 | #define REG_EVSYS_USER32 (0x4100E1A0) /**< \brief (EVSYS) User Multiplexer 32 */ |
| 235 | #define REG_EVSYS_USER33 (0x4100E1A4) /**< \brief (EVSYS) User Multiplexer 33 */ |
| 236 | #define REG_EVSYS_USER34 (0x4100E1A8) /**< \brief (EVSYS) User Multiplexer 34 */ |
| 237 | #define REG_EVSYS_USER35 (0x4100E1AC) /**< \brief (EVSYS) User Multiplexer 35 */ |
| 238 | #define REG_EVSYS_USER36 (0x4100E1B0) /**< \brief (EVSYS) User Multiplexer 36 */ |
| 239 | #define REG_EVSYS_USER37 (0x4100E1B4) /**< \brief (EVSYS) User Multiplexer 37 */ |
| 240 | #define REG_EVSYS_USER38 (0x4100E1B8) /**< \brief (EVSYS) User Multiplexer 38 */ |
| 241 | #define REG_EVSYS_USER39 (0x4100E1BC) /**< \brief (EVSYS) User Multiplexer 39 */ |
| 242 | #define REG_EVSYS_USER40 (0x4100E1C0) /**< \brief (EVSYS) User Multiplexer 40 */ |
| 243 | #define REG_EVSYS_USER41 (0x4100E1C4) /**< \brief (EVSYS) User Multiplexer 41 */ |
| 244 | #define REG_EVSYS_USER42 (0x4100E1C8) /**< \brief (EVSYS) User Multiplexer 42 */ |
| 245 | #define REG_EVSYS_USER43 (0x4100E1CC) /**< \brief (EVSYS) User Multiplexer 43 */ |
| 246 | #define REG_EVSYS_USER44 (0x4100E1D0) /**< \brief (EVSYS) User Multiplexer 44 */ |
| 247 | #define REG_EVSYS_USER45 (0x4100E1D4) /**< \brief (EVSYS) User Multiplexer 45 */ |
| 248 | #define REG_EVSYS_USER46 (0x4100E1D8) /**< \brief (EVSYS) User Multiplexer 46 */ |
| 249 | #define REG_EVSYS_USER47 (0x4100E1DC) /**< \brief (EVSYS) User Multiplexer 47 */ |
| 250 | #define REG_EVSYS_USER48 (0x4100E1E0) /**< \brief (EVSYS) User Multiplexer 48 */ |
| 251 | #define REG_EVSYS_USER49 (0x4100E1E4) /**< \brief (EVSYS) User Multiplexer 49 */ |
| 252 | #define REG_EVSYS_USER50 (0x4100E1E8) /**< \brief (EVSYS) User Multiplexer 50 */ |
| 253 | #define REG_EVSYS_USER51 (0x4100E1EC) /**< \brief (EVSYS) User Multiplexer 51 */ |
| 254 | #define REG_EVSYS_USER52 (0x4100E1F0) /**< \brief (EVSYS) User Multiplexer 52 */ |
| 255 | #define REG_EVSYS_USER53 (0x4100E1F4) /**< \brief (EVSYS) User Multiplexer 53 */ |
| 256 | #define REG_EVSYS_USER54 (0x4100E1F8) /**< \brief (EVSYS) User Multiplexer 54 */ |
| 257 | #define REG_EVSYS_USER55 (0x4100E1FC) /**< \brief (EVSYS) User Multiplexer 55 */ |
| 258 | #define REG_EVSYS_USER56 (0x4100E200) /**< \brief (EVSYS) User Multiplexer 56 */ |
| 259 | #define REG_EVSYS_USER57 (0x4100E204) /**< \brief (EVSYS) User Multiplexer 57 */ |
| 260 | #define REG_EVSYS_USER58 (0x4100E208) /**< \brief (EVSYS) User Multiplexer 58 */ |
| 261 | #define REG_EVSYS_USER59 (0x4100E20C) /**< \brief (EVSYS) User Multiplexer 59 */ |
| 262 | #define REG_EVSYS_USER60 (0x4100E210) /**< \brief (EVSYS) User Multiplexer 60 */ |
| 263 | #define REG_EVSYS_USER61 (0x4100E214) /**< \brief (EVSYS) User Multiplexer 61 */ |
| 264 | #define REG_EVSYS_USER62 (0x4100E218) /**< \brief (EVSYS) User Multiplexer 62 */ |
| 265 | #define REG_EVSYS_USER63 (0x4100E21C) /**< \brief (EVSYS) User Multiplexer 63 */ |
| 266 | #define REG_EVSYS_USER64 (0x4100E220) /**< \brief (EVSYS) User Multiplexer 64 */ |
| 267 | #define REG_EVSYS_USER65 (0x4100E224) /**< \brief (EVSYS) User Multiplexer 65 */ |
| 268 | #define REG_EVSYS_USER66 (0x4100E228) /**< \brief (EVSYS) User Multiplexer 66 */ |
| 269 | #else |
| 270 | #define REG_EVSYS_CTRLA (*(RwReg8 *)0x4100E000UL) /**< \brief (EVSYS) Control */ |
| 271 | #define REG_EVSYS_SWEVT (*(WoReg *)0x4100E004UL) /**< \brief (EVSYS) Software Event */ |
| 272 | #define REG_EVSYS_PRICTRL (*(RwReg8 *)0x4100E008UL) /**< \brief (EVSYS) Priority Control */ |
| 273 | #define REG_EVSYS_INTPEND (*(RwReg16*)0x4100E010UL) /**< \brief (EVSYS) Channel Pending Interrupt */ |
| 274 | #define REG_EVSYS_INTSTATUS (*(RoReg *)0x4100E014UL) /**< \brief (EVSYS) Interrupt Status */ |
| 275 | #define REG_EVSYS_BUSYCH (*(RoReg *)0x4100E018UL) /**< \brief (EVSYS) Busy Channels */ |
| 276 | #define REG_EVSYS_READYUSR (*(RoReg *)0x4100E01CUL) /**< \brief (EVSYS) Ready Users */ |
| 277 | #define REG_EVSYS_CHANNEL0 (*(RwReg *)0x4100E020UL) /**< \brief (EVSYS) Channel 0 Control */ |
| 278 | #define REG_EVSYS_CHINTENCLR0 (*(RwReg8 *)0x4100E024UL) /**< \brief (EVSYS) Channel 0 Interrupt Enable Clear */ |
| 279 | #define REG_EVSYS_CHINTENSET0 (*(RwReg8 *)0x4100E025UL) /**< \brief (EVSYS) Channel 0 Interrupt Enable Set */ |
| 280 | #define REG_EVSYS_CHINTFLAG0 (*(RwReg8 *)0x4100E026UL) /**< \brief (EVSYS) Channel 0 Interrupt Flag Status and Clear */ |
| 281 | #define REG_EVSYS_CHSTATUS0 (*(RoReg8 *)0x4100E027UL) /**< \brief (EVSYS) Channel 0 Status */ |
| 282 | #define REG_EVSYS_CHANNEL1 (*(RwReg *)0x4100E028UL) /**< \brief (EVSYS) Channel 1 Control */ |
| 283 | #define REG_EVSYS_CHINTENCLR1 (*(RwReg8 *)0x4100E02CUL) /**< \brief (EVSYS) Channel 1 Interrupt Enable Clear */ |
| 284 | #define REG_EVSYS_CHINTENSET1 (*(RwReg8 *)0x4100E02DUL) /**< \brief (EVSYS) Channel 1 Interrupt Enable Set */ |
| 285 | #define REG_EVSYS_CHINTFLAG1 (*(RwReg8 *)0x4100E02EUL) /**< \brief (EVSYS) Channel 1 Interrupt Flag Status and Clear */ |
| 286 | #define REG_EVSYS_CHSTATUS1 (*(RoReg8 *)0x4100E02FUL) /**< \brief (EVSYS) Channel 1 Status */ |
| 287 | #define REG_EVSYS_CHANNEL2 (*(RwReg *)0x4100E030UL) /**< \brief (EVSYS) Channel 2 Control */ |
| 288 | #define REG_EVSYS_CHINTENCLR2 (*(RwReg8 *)0x4100E034UL) /**< \brief (EVSYS) Channel 2 Interrupt Enable Clear */ |
| 289 | #define REG_EVSYS_CHINTENSET2 (*(RwReg8 *)0x4100E035UL) /**< \brief (EVSYS) Channel 2 Interrupt Enable Set */ |
| 290 | #define REG_EVSYS_CHINTFLAG2 (*(RwReg8 *)0x4100E036UL) /**< \brief (EVSYS) Channel 2 Interrupt Flag Status and Clear */ |
| 291 | #define REG_EVSYS_CHSTATUS2 (*(RoReg8 *)0x4100E037UL) /**< \brief (EVSYS) Channel 2 Status */ |
| 292 | #define REG_EVSYS_CHANNEL3 (*(RwReg *)0x4100E038UL) /**< \brief (EVSYS) Channel 3 Control */ |
| 293 | #define REG_EVSYS_CHINTENCLR3 (*(RwReg8 *)0x4100E03CUL) /**< \brief (EVSYS) Channel 3 Interrupt Enable Clear */ |
| 294 | #define REG_EVSYS_CHINTENSET3 (*(RwReg8 *)0x4100E03DUL) /**< \brief (EVSYS) Channel 3 Interrupt Enable Set */ |
| 295 | #define REG_EVSYS_CHINTFLAG3 (*(RwReg8 *)0x4100E03EUL) /**< \brief (EVSYS) Channel 3 Interrupt Flag Status and Clear */ |
| 296 | #define REG_EVSYS_CHSTATUS3 (*(RoReg8 *)0x4100E03FUL) /**< \brief (EVSYS) Channel 3 Status */ |
| 297 | #define REG_EVSYS_CHANNEL4 (*(RwReg *)0x4100E040UL) /**< \brief (EVSYS) Channel 4 Control */ |
| 298 | #define REG_EVSYS_CHINTENCLR4 (*(RwReg8 *)0x4100E044UL) /**< \brief (EVSYS) Channel 4 Interrupt Enable Clear */ |
| 299 | #define REG_EVSYS_CHINTENSET4 (*(RwReg8 *)0x4100E045UL) /**< \brief (EVSYS) Channel 4 Interrupt Enable Set */ |
| 300 | #define REG_EVSYS_CHINTFLAG4 (*(RwReg8 *)0x4100E046UL) /**< \brief (EVSYS) Channel 4 Interrupt Flag Status and Clear */ |
| 301 | #define REG_EVSYS_CHSTATUS4 (*(RoReg8 *)0x4100E047UL) /**< \brief (EVSYS) Channel 4 Status */ |
| 302 | #define REG_EVSYS_CHANNEL5 (*(RwReg *)0x4100E048UL) /**< \brief (EVSYS) Channel 5 Control */ |
| 303 | #define REG_EVSYS_CHINTENCLR5 (*(RwReg8 *)0x4100E04CUL) /**< \brief (EVSYS) Channel 5 Interrupt Enable Clear */ |
| 304 | #define REG_EVSYS_CHINTENSET5 (*(RwReg8 *)0x4100E04DUL) /**< \brief (EVSYS) Channel 5 Interrupt Enable Set */ |
| 305 | #define REG_EVSYS_CHINTFLAG5 (*(RwReg8 *)0x4100E04EUL) /**< \brief (EVSYS) Channel 5 Interrupt Flag Status and Clear */ |
| 306 | #define REG_EVSYS_CHSTATUS5 (*(RoReg8 *)0x4100E04FUL) /**< \brief (EVSYS) Channel 5 Status */ |
| 307 | #define REG_EVSYS_CHANNEL6 (*(RwReg *)0x4100E050UL) /**< \brief (EVSYS) Channel 6 Control */ |
| 308 | #define REG_EVSYS_CHINTENCLR6 (*(RwReg8 *)0x4100E054UL) /**< \brief (EVSYS) Channel 6 Interrupt Enable Clear */ |
| 309 | #define REG_EVSYS_CHINTENSET6 (*(RwReg8 *)0x4100E055UL) /**< \brief (EVSYS) Channel 6 Interrupt Enable Set */ |
| 310 | #define REG_EVSYS_CHINTFLAG6 (*(RwReg8 *)0x4100E056UL) /**< \brief (EVSYS) Channel 6 Interrupt Flag Status and Clear */ |
| 311 | #define REG_EVSYS_CHSTATUS6 (*(RoReg8 *)0x4100E057UL) /**< \brief (EVSYS) Channel 6 Status */ |
| 312 | #define REG_EVSYS_CHANNEL7 (*(RwReg *)0x4100E058UL) /**< \brief (EVSYS) Channel 7 Control */ |
| 313 | #define REG_EVSYS_CHINTENCLR7 (*(RwReg8 *)0x4100E05CUL) /**< \brief (EVSYS) Channel 7 Interrupt Enable Clear */ |
| 314 | #define REG_EVSYS_CHINTENSET7 (*(RwReg8 *)0x4100E05DUL) /**< \brief (EVSYS) Channel 7 Interrupt Enable Set */ |
| 315 | #define REG_EVSYS_CHINTFLAG7 (*(RwReg8 *)0x4100E05EUL) /**< \brief (EVSYS) Channel 7 Interrupt Flag Status and Clear */ |
| 316 | #define REG_EVSYS_CHSTATUS7 (*(RoReg8 *)0x4100E05FUL) /**< \brief (EVSYS) Channel 7 Status */ |
| 317 | #define REG_EVSYS_CHANNEL8 (*(RwReg *)0x4100E060UL) /**< \brief (EVSYS) Channel 8 Control */ |
| 318 | #define REG_EVSYS_CHINTENCLR8 (*(RwReg8 *)0x4100E064UL) /**< \brief (EVSYS) Channel 8 Interrupt Enable Clear */ |
| 319 | #define REG_EVSYS_CHINTENSET8 (*(RwReg8 *)0x4100E065UL) /**< \brief (EVSYS) Channel 8 Interrupt Enable Set */ |
| 320 | #define REG_EVSYS_CHINTFLAG8 (*(RwReg8 *)0x4100E066UL) /**< \brief (EVSYS) Channel 8 Interrupt Flag Status and Clear */ |
| 321 | #define REG_EVSYS_CHSTATUS8 (*(RoReg8 *)0x4100E067UL) /**< \brief (EVSYS) Channel 8 Status */ |
| 322 | #define REG_EVSYS_CHANNEL9 (*(RwReg *)0x4100E068UL) /**< \brief (EVSYS) Channel 9 Control */ |
| 323 | #define REG_EVSYS_CHINTENCLR9 (*(RwReg8 *)0x4100E06CUL) /**< \brief (EVSYS) Channel 9 Interrupt Enable Clear */ |
| 324 | #define REG_EVSYS_CHINTENSET9 (*(RwReg8 *)0x4100E06DUL) /**< \brief (EVSYS) Channel 9 Interrupt Enable Set */ |
| 325 | #define REG_EVSYS_CHINTFLAG9 (*(RwReg8 *)0x4100E06EUL) /**< \brief (EVSYS) Channel 9 Interrupt Flag Status and Clear */ |
| 326 | #define REG_EVSYS_CHSTATUS9 (*(RoReg8 *)0x4100E06FUL) /**< \brief (EVSYS) Channel 9 Status */ |
| 327 | #define REG_EVSYS_CHANNEL10 (*(RwReg *)0x4100E070UL) /**< \brief (EVSYS) Channel 10 Control */ |
| 328 | #define REG_EVSYS_CHINTENCLR10 (*(RwReg8 *)0x4100E074UL) /**< \brief (EVSYS) Channel 10 Interrupt Enable Clear */ |
| 329 | #define REG_EVSYS_CHINTENSET10 (*(RwReg8 *)0x4100E075UL) /**< \brief (EVSYS) Channel 10 Interrupt Enable Set */ |
| 330 | #define REG_EVSYS_CHINTFLAG10 (*(RwReg8 *)0x4100E076UL) /**< \brief (EVSYS) Channel 10 Interrupt Flag Status and Clear */ |
| 331 | #define REG_EVSYS_CHSTATUS10 (*(RoReg8 *)0x4100E077UL) /**< \brief (EVSYS) Channel 10 Status */ |
| 332 | #define REG_EVSYS_CHANNEL11 (*(RwReg *)0x4100E078UL) /**< \brief (EVSYS) Channel 11 Control */ |
| 333 | #define REG_EVSYS_CHINTENCLR11 (*(RwReg8 *)0x4100E07CUL) /**< \brief (EVSYS) Channel 11 Interrupt Enable Clear */ |
| 334 | #define REG_EVSYS_CHINTENSET11 (*(RwReg8 *)0x4100E07DUL) /**< \brief (EVSYS) Channel 11 Interrupt Enable Set */ |
| 335 | #define REG_EVSYS_CHINTFLAG11 (*(RwReg8 *)0x4100E07EUL) /**< \brief (EVSYS) Channel 11 Interrupt Flag Status and Clear */ |
| 336 | #define REG_EVSYS_CHSTATUS11 (*(RoReg8 *)0x4100E07FUL) /**< \brief (EVSYS) Channel 11 Status */ |
| 337 | #define REG_EVSYS_CHANNEL12 (*(RwReg *)0x4100E080UL) /**< \brief (EVSYS) Channel 12 Control */ |
| 338 | #define REG_EVSYS_CHINTENCLR12 (*(RwReg8 *)0x4100E084UL) /**< \brief (EVSYS) Channel 12 Interrupt Enable Clear */ |
| 339 | #define REG_EVSYS_CHINTENSET12 (*(RwReg8 *)0x4100E085UL) /**< \brief (EVSYS) Channel 12 Interrupt Enable Set */ |
| 340 | #define REG_EVSYS_CHINTFLAG12 (*(RwReg8 *)0x4100E086UL) /**< \brief (EVSYS) Channel 12 Interrupt Flag Status and Clear */ |
| 341 | #define REG_EVSYS_CHSTATUS12 (*(RoReg8 *)0x4100E087UL) /**< \brief (EVSYS) Channel 12 Status */ |
| 342 | #define REG_EVSYS_CHANNEL13 (*(RwReg *)0x4100E088UL) /**< \brief (EVSYS) Channel 13 Control */ |
| 343 | #define REG_EVSYS_CHINTENCLR13 (*(RwReg8 *)0x4100E08CUL) /**< \brief (EVSYS) Channel 13 Interrupt Enable Clear */ |
| 344 | #define REG_EVSYS_CHINTENSET13 (*(RwReg8 *)0x4100E08DUL) /**< \brief (EVSYS) Channel 13 Interrupt Enable Set */ |
| 345 | #define REG_EVSYS_CHINTFLAG13 (*(RwReg8 *)0x4100E08EUL) /**< \brief (EVSYS) Channel 13 Interrupt Flag Status and Clear */ |
| 346 | #define REG_EVSYS_CHSTATUS13 (*(RoReg8 *)0x4100E08FUL) /**< \brief (EVSYS) Channel 13 Status */ |
| 347 | #define REG_EVSYS_CHANNEL14 (*(RwReg *)0x4100E090UL) /**< \brief (EVSYS) Channel 14 Control */ |
| 348 | #define REG_EVSYS_CHINTENCLR14 (*(RwReg8 *)0x4100E094UL) /**< \brief (EVSYS) Channel 14 Interrupt Enable Clear */ |
| 349 | #define REG_EVSYS_CHINTENSET14 (*(RwReg8 *)0x4100E095UL) /**< \brief (EVSYS) Channel 14 Interrupt Enable Set */ |
| 350 | #define REG_EVSYS_CHINTFLAG14 (*(RwReg8 *)0x4100E096UL) /**< \brief (EVSYS) Channel 14 Interrupt Flag Status and Clear */ |
| 351 | #define REG_EVSYS_CHSTATUS14 (*(RoReg8 *)0x4100E097UL) /**< \brief (EVSYS) Channel 14 Status */ |
| 352 | #define REG_EVSYS_CHANNEL15 (*(RwReg *)0x4100E098UL) /**< \brief (EVSYS) Channel 15 Control */ |
| 353 | #define REG_EVSYS_CHINTENCLR15 (*(RwReg8 *)0x4100E09CUL) /**< \brief (EVSYS) Channel 15 Interrupt Enable Clear */ |
| 354 | #define REG_EVSYS_CHINTENSET15 (*(RwReg8 *)0x4100E09DUL) /**< \brief (EVSYS) Channel 15 Interrupt Enable Set */ |
| 355 | #define REG_EVSYS_CHINTFLAG15 (*(RwReg8 *)0x4100E09EUL) /**< \brief (EVSYS) Channel 15 Interrupt Flag Status and Clear */ |
| 356 | #define REG_EVSYS_CHSTATUS15 (*(RoReg8 *)0x4100E09FUL) /**< \brief (EVSYS) Channel 15 Status */ |
| 357 | #define REG_EVSYS_CHANNEL16 (*(RwReg *)0x4100E0A0UL) /**< \brief (EVSYS) Channel 16 Control */ |
| 358 | #define REG_EVSYS_CHINTENCLR16 (*(RwReg8 *)0x4100E0A4UL) /**< \brief (EVSYS) Channel 16 Interrupt Enable Clear */ |
| 359 | #define REG_EVSYS_CHINTENSET16 (*(RwReg8 *)0x4100E0A5UL) /**< \brief (EVSYS) Channel 16 Interrupt Enable Set */ |
| 360 | #define REG_EVSYS_CHINTFLAG16 (*(RwReg8 *)0x4100E0A6UL) /**< \brief (EVSYS) Channel 16 Interrupt Flag Status and Clear */ |
| 361 | #define REG_EVSYS_CHSTATUS16 (*(RoReg8 *)0x4100E0A7UL) /**< \brief (EVSYS) Channel 16 Status */ |
| 362 | #define REG_EVSYS_CHANNEL17 (*(RwReg *)0x4100E0A8UL) /**< \brief (EVSYS) Channel 17 Control */ |
| 363 | #define REG_EVSYS_CHINTENCLR17 (*(RwReg8 *)0x4100E0ACUL) /**< \brief (EVSYS) Channel 17 Interrupt Enable Clear */ |
| 364 | #define REG_EVSYS_CHINTENSET17 (*(RwReg8 *)0x4100E0ADUL) /**< \brief (EVSYS) Channel 17 Interrupt Enable Set */ |
| 365 | #define REG_EVSYS_CHINTFLAG17 (*(RwReg8 *)0x4100E0AEUL) /**< \brief (EVSYS) Channel 17 Interrupt Flag Status and Clear */ |
| 366 | #define REG_EVSYS_CHSTATUS17 (*(RoReg8 *)0x4100E0AFUL) /**< \brief (EVSYS) Channel 17 Status */ |
| 367 | #define REG_EVSYS_CHANNEL18 (*(RwReg *)0x4100E0B0UL) /**< \brief (EVSYS) Channel 18 Control */ |
| 368 | #define REG_EVSYS_CHINTENCLR18 (*(RwReg8 *)0x4100E0B4UL) /**< \brief (EVSYS) Channel 18 Interrupt Enable Clear */ |
| 369 | #define REG_EVSYS_CHINTENSET18 (*(RwReg8 *)0x4100E0B5UL) /**< \brief (EVSYS) Channel 18 Interrupt Enable Set */ |
| 370 | #define REG_EVSYS_CHINTFLAG18 (*(RwReg8 *)0x4100E0B6UL) /**< \brief (EVSYS) Channel 18 Interrupt Flag Status and Clear */ |
| 371 | #define REG_EVSYS_CHSTATUS18 (*(RoReg8 *)0x4100E0B7UL) /**< \brief (EVSYS) Channel 18 Status */ |
| 372 | #define REG_EVSYS_CHANNEL19 (*(RwReg *)0x4100E0B8UL) /**< \brief (EVSYS) Channel 19 Control */ |
| 373 | #define REG_EVSYS_CHINTENCLR19 (*(RwReg8 *)0x4100E0BCUL) /**< \brief (EVSYS) Channel 19 Interrupt Enable Clear */ |
| 374 | #define REG_EVSYS_CHINTENSET19 (*(RwReg8 *)0x4100E0BDUL) /**< \brief (EVSYS) Channel 19 Interrupt Enable Set */ |
| 375 | #define REG_EVSYS_CHINTFLAG19 (*(RwReg8 *)0x4100E0BEUL) /**< \brief (EVSYS) Channel 19 Interrupt Flag Status and Clear */ |
| 376 | #define REG_EVSYS_CHSTATUS19 (*(RoReg8 *)0x4100E0BFUL) /**< \brief (EVSYS) Channel 19 Status */ |
| 377 | #define REG_EVSYS_CHANNEL20 (*(RwReg *)0x4100E0C0UL) /**< \brief (EVSYS) Channel 20 Control */ |
| 378 | #define REG_EVSYS_CHINTENCLR20 (*(RwReg8 *)0x4100E0C4UL) /**< \brief (EVSYS) Channel 20 Interrupt Enable Clear */ |
| 379 | #define REG_EVSYS_CHINTENSET20 (*(RwReg8 *)0x4100E0C5UL) /**< \brief (EVSYS) Channel 20 Interrupt Enable Set */ |
| 380 | #define REG_EVSYS_CHINTFLAG20 (*(RwReg8 *)0x4100E0C6UL) /**< \brief (EVSYS) Channel 20 Interrupt Flag Status and Clear */ |
| 381 | #define REG_EVSYS_CHSTATUS20 (*(RoReg8 *)0x4100E0C7UL) /**< \brief (EVSYS) Channel 20 Status */ |
| 382 | #define REG_EVSYS_CHANNEL21 (*(RwReg *)0x4100E0C8UL) /**< \brief (EVSYS) Channel 21 Control */ |
| 383 | #define REG_EVSYS_CHINTENCLR21 (*(RwReg8 *)0x4100E0CCUL) /**< \brief (EVSYS) Channel 21 Interrupt Enable Clear */ |
| 384 | #define REG_EVSYS_CHINTENSET21 (*(RwReg8 *)0x4100E0CDUL) /**< \brief (EVSYS) Channel 21 Interrupt Enable Set */ |
| 385 | #define REG_EVSYS_CHINTFLAG21 (*(RwReg8 *)0x4100E0CEUL) /**< \brief (EVSYS) Channel 21 Interrupt Flag Status and Clear */ |
| 386 | #define REG_EVSYS_CHSTATUS21 (*(RoReg8 *)0x4100E0CFUL) /**< \brief (EVSYS) Channel 21 Status */ |
| 387 | #define REG_EVSYS_CHANNEL22 (*(RwReg *)0x4100E0D0UL) /**< \brief (EVSYS) Channel 22 Control */ |
| 388 | #define REG_EVSYS_CHINTENCLR22 (*(RwReg8 *)0x4100E0D4UL) /**< \brief (EVSYS) Channel 22 Interrupt Enable Clear */ |
| 389 | #define REG_EVSYS_CHINTENSET22 (*(RwReg8 *)0x4100E0D5UL) /**< \brief (EVSYS) Channel 22 Interrupt Enable Set */ |
| 390 | #define REG_EVSYS_CHINTFLAG22 (*(RwReg8 *)0x4100E0D6UL) /**< \brief (EVSYS) Channel 22 Interrupt Flag Status and Clear */ |
| 391 | #define REG_EVSYS_CHSTATUS22 (*(RoReg8 *)0x4100E0D7UL) /**< \brief (EVSYS) Channel 22 Status */ |
| 392 | #define REG_EVSYS_CHANNEL23 (*(RwReg *)0x4100E0D8UL) /**< \brief (EVSYS) Channel 23 Control */ |
| 393 | #define REG_EVSYS_CHINTENCLR23 (*(RwReg8 *)0x4100E0DCUL) /**< \brief (EVSYS) Channel 23 Interrupt Enable Clear */ |
| 394 | #define REG_EVSYS_CHINTENSET23 (*(RwReg8 *)0x4100E0DDUL) /**< \brief (EVSYS) Channel 23 Interrupt Enable Set */ |
| 395 | #define REG_EVSYS_CHINTFLAG23 (*(RwReg8 *)0x4100E0DEUL) /**< \brief (EVSYS) Channel 23 Interrupt Flag Status and Clear */ |
| 396 | #define REG_EVSYS_CHSTATUS23 (*(RoReg8 *)0x4100E0DFUL) /**< \brief (EVSYS) Channel 23 Status */ |
| 397 | #define REG_EVSYS_CHANNEL24 (*(RwReg *)0x4100E0E0UL) /**< \brief (EVSYS) Channel 24 Control */ |
| 398 | #define REG_EVSYS_CHINTENCLR24 (*(RwReg8 *)0x4100E0E4UL) /**< \brief (EVSYS) Channel 24 Interrupt Enable Clear */ |
| 399 | #define REG_EVSYS_CHINTENSET24 (*(RwReg8 *)0x4100E0E5UL) /**< \brief (EVSYS) Channel 24 Interrupt Enable Set */ |
| 400 | #define REG_EVSYS_CHINTFLAG24 (*(RwReg8 *)0x4100E0E6UL) /**< \brief (EVSYS) Channel 24 Interrupt Flag Status and Clear */ |
| 401 | #define REG_EVSYS_CHSTATUS24 (*(RoReg8 *)0x4100E0E7UL) /**< \brief (EVSYS) Channel 24 Status */ |
| 402 | #define REG_EVSYS_CHANNEL25 (*(RwReg *)0x4100E0E8UL) /**< \brief (EVSYS) Channel 25 Control */ |
| 403 | #define REG_EVSYS_CHINTENCLR25 (*(RwReg8 *)0x4100E0ECUL) /**< \brief (EVSYS) Channel 25 Interrupt Enable Clear */ |
| 404 | #define REG_EVSYS_CHINTENSET25 (*(RwReg8 *)0x4100E0EDUL) /**< \brief (EVSYS) Channel 25 Interrupt Enable Set */ |
| 405 | #define REG_EVSYS_CHINTFLAG25 (*(RwReg8 *)0x4100E0EEUL) /**< \brief (EVSYS) Channel 25 Interrupt Flag Status and Clear */ |
| 406 | #define REG_EVSYS_CHSTATUS25 (*(RoReg8 *)0x4100E0EFUL) /**< \brief (EVSYS) Channel 25 Status */ |
| 407 | #define REG_EVSYS_CHANNEL26 (*(RwReg *)0x4100E0F0UL) /**< \brief (EVSYS) Channel 26 Control */ |
| 408 | #define REG_EVSYS_CHINTENCLR26 (*(RwReg8 *)0x4100E0F4UL) /**< \brief (EVSYS) Channel 26 Interrupt Enable Clear */ |
| 409 | #define REG_EVSYS_CHINTENSET26 (*(RwReg8 *)0x4100E0F5UL) /**< \brief (EVSYS) Channel 26 Interrupt Enable Set */ |
| 410 | #define REG_EVSYS_CHINTFLAG26 (*(RwReg8 *)0x4100E0F6UL) /**< \brief (EVSYS) Channel 26 Interrupt Flag Status and Clear */ |
| 411 | #define REG_EVSYS_CHSTATUS26 (*(RoReg8 *)0x4100E0F7UL) /**< \brief (EVSYS) Channel 26 Status */ |
| 412 | #define REG_EVSYS_CHANNEL27 (*(RwReg *)0x4100E0F8UL) /**< \brief (EVSYS) Channel 27 Control */ |
| 413 | #define REG_EVSYS_CHINTENCLR27 (*(RwReg8 *)0x4100E0FCUL) /**< \brief (EVSYS) Channel 27 Interrupt Enable Clear */ |
| 414 | #define REG_EVSYS_CHINTENSET27 (*(RwReg8 *)0x4100E0FDUL) /**< \brief (EVSYS) Channel 27 Interrupt Enable Set */ |
| 415 | #define REG_EVSYS_CHINTFLAG27 (*(RwReg8 *)0x4100E0FEUL) /**< \brief (EVSYS) Channel 27 Interrupt Flag Status and Clear */ |
| 416 | #define REG_EVSYS_CHSTATUS27 (*(RoReg8 *)0x4100E0FFUL) /**< \brief (EVSYS) Channel 27 Status */ |
| 417 | #define REG_EVSYS_CHANNEL28 (*(RwReg *)0x4100E100UL) /**< \brief (EVSYS) Channel 28 Control */ |
| 418 | #define REG_EVSYS_CHINTENCLR28 (*(RwReg8 *)0x4100E104UL) /**< \brief (EVSYS) Channel 28 Interrupt Enable Clear */ |
| 419 | #define REG_EVSYS_CHINTENSET28 (*(RwReg8 *)0x4100E105UL) /**< \brief (EVSYS) Channel 28 Interrupt Enable Set */ |
| 420 | #define REG_EVSYS_CHINTFLAG28 (*(RwReg8 *)0x4100E106UL) /**< \brief (EVSYS) Channel 28 Interrupt Flag Status and Clear */ |
| 421 | #define REG_EVSYS_CHSTATUS28 (*(RoReg8 *)0x4100E107UL) /**< \brief (EVSYS) Channel 28 Status */ |
| 422 | #define REG_EVSYS_CHANNEL29 (*(RwReg *)0x4100E108UL) /**< \brief (EVSYS) Channel 29 Control */ |
| 423 | #define REG_EVSYS_CHINTENCLR29 (*(RwReg8 *)0x4100E10CUL) /**< \brief (EVSYS) Channel 29 Interrupt Enable Clear */ |
| 424 | #define REG_EVSYS_CHINTENSET29 (*(RwReg8 *)0x4100E10DUL) /**< \brief (EVSYS) Channel 29 Interrupt Enable Set */ |
| 425 | #define REG_EVSYS_CHINTFLAG29 (*(RwReg8 *)0x4100E10EUL) /**< \brief (EVSYS) Channel 29 Interrupt Flag Status and Clear */ |
| 426 | #define REG_EVSYS_CHSTATUS29 (*(RoReg8 *)0x4100E10FUL) /**< \brief (EVSYS) Channel 29 Status */ |
| 427 | #define REG_EVSYS_CHANNEL30 (*(RwReg *)0x4100E110UL) /**< \brief (EVSYS) Channel 30 Control */ |
| 428 | #define REG_EVSYS_CHINTENCLR30 (*(RwReg8 *)0x4100E114UL) /**< \brief (EVSYS) Channel 30 Interrupt Enable Clear */ |
| 429 | #define REG_EVSYS_CHINTENSET30 (*(RwReg8 *)0x4100E115UL) /**< \brief (EVSYS) Channel 30 Interrupt Enable Set */ |
| 430 | #define REG_EVSYS_CHINTFLAG30 (*(RwReg8 *)0x4100E116UL) /**< \brief (EVSYS) Channel 30 Interrupt Flag Status and Clear */ |
| 431 | #define REG_EVSYS_CHSTATUS30 (*(RoReg8 *)0x4100E117UL) /**< \brief (EVSYS) Channel 30 Status */ |
| 432 | #define REG_EVSYS_CHANNEL31 (*(RwReg *)0x4100E118UL) /**< \brief (EVSYS) Channel 31 Control */ |
| 433 | #define REG_EVSYS_CHINTENCLR31 (*(RwReg8 *)0x4100E11CUL) /**< \brief (EVSYS) Channel 31 Interrupt Enable Clear */ |
| 434 | #define REG_EVSYS_CHINTENSET31 (*(RwReg8 *)0x4100E11DUL) /**< \brief (EVSYS) Channel 31 Interrupt Enable Set */ |
| 435 | #define REG_EVSYS_CHINTFLAG31 (*(RwReg8 *)0x4100E11EUL) /**< \brief (EVSYS) Channel 31 Interrupt Flag Status and Clear */ |
| 436 | #define REG_EVSYS_CHSTATUS31 (*(RoReg8 *)0x4100E11FUL) /**< \brief (EVSYS) Channel 31 Status */ |
| 437 | #define REG_EVSYS_USER0 (*(RwReg *)0x4100E120UL) /**< \brief (EVSYS) User Multiplexer 0 */ |
| 438 | #define REG_EVSYS_USER1 (*(RwReg *)0x4100E124UL) /**< \brief (EVSYS) User Multiplexer 1 */ |
| 439 | #define REG_EVSYS_USER2 (*(RwReg *)0x4100E128UL) /**< \brief (EVSYS) User Multiplexer 2 */ |
| 440 | #define REG_EVSYS_USER3 (*(RwReg *)0x4100E12CUL) /**< \brief (EVSYS) User Multiplexer 3 */ |
| 441 | #define REG_EVSYS_USER4 (*(RwReg *)0x4100E130UL) /**< \brief (EVSYS) User Multiplexer 4 */ |
| 442 | #define REG_EVSYS_USER5 (*(RwReg *)0x4100E134UL) /**< \brief (EVSYS) User Multiplexer 5 */ |
| 443 | #define REG_EVSYS_USER6 (*(RwReg *)0x4100E138UL) /**< \brief (EVSYS) User Multiplexer 6 */ |
| 444 | #define REG_EVSYS_USER7 (*(RwReg *)0x4100E13CUL) /**< \brief (EVSYS) User Multiplexer 7 */ |
| 445 | #define REG_EVSYS_USER8 (*(RwReg *)0x4100E140UL) /**< \brief (EVSYS) User Multiplexer 8 */ |
| 446 | #define REG_EVSYS_USER9 (*(RwReg *)0x4100E144UL) /**< \brief (EVSYS) User Multiplexer 9 */ |
| 447 | #define REG_EVSYS_USER10 (*(RwReg *)0x4100E148UL) /**< \brief (EVSYS) User Multiplexer 10 */ |
| 448 | #define REG_EVSYS_USER11 (*(RwReg *)0x4100E14CUL) /**< \brief (EVSYS) User Multiplexer 11 */ |
| 449 | #define REG_EVSYS_USER12 (*(RwReg *)0x4100E150UL) /**< \brief (EVSYS) User Multiplexer 12 */ |
| 450 | #define REG_EVSYS_USER13 (*(RwReg *)0x4100E154UL) /**< \brief (EVSYS) User Multiplexer 13 */ |
| 451 | #define REG_EVSYS_USER14 (*(RwReg *)0x4100E158UL) /**< \brief (EVSYS) User Multiplexer 14 */ |
| 452 | #define REG_EVSYS_USER15 (*(RwReg *)0x4100E15CUL) /**< \brief (EVSYS) User Multiplexer 15 */ |
| 453 | #define REG_EVSYS_USER16 (*(RwReg *)0x4100E160UL) /**< \brief (EVSYS) User Multiplexer 16 */ |
| 454 | #define REG_EVSYS_USER17 (*(RwReg *)0x4100E164UL) /**< \brief (EVSYS) User Multiplexer 17 */ |
| 455 | #define REG_EVSYS_USER18 (*(RwReg *)0x4100E168UL) /**< \brief (EVSYS) User Multiplexer 18 */ |
| 456 | #define REG_EVSYS_USER19 (*(RwReg *)0x4100E16CUL) /**< \brief (EVSYS) User Multiplexer 19 */ |
| 457 | #define REG_EVSYS_USER20 (*(RwReg *)0x4100E170UL) /**< \brief (EVSYS) User Multiplexer 20 */ |
| 458 | #define REG_EVSYS_USER21 (*(RwReg *)0x4100E174UL) /**< \brief (EVSYS) User Multiplexer 21 */ |
| 459 | #define REG_EVSYS_USER22 (*(RwReg *)0x4100E178UL) /**< \brief (EVSYS) User Multiplexer 22 */ |
| 460 | #define REG_EVSYS_USER23 (*(RwReg *)0x4100E17CUL) /**< \brief (EVSYS) User Multiplexer 23 */ |
| 461 | #define REG_EVSYS_USER24 (*(RwReg *)0x4100E180UL) /**< \brief (EVSYS) User Multiplexer 24 */ |
| 462 | #define REG_EVSYS_USER25 (*(RwReg *)0x4100E184UL) /**< \brief (EVSYS) User Multiplexer 25 */ |
| 463 | #define REG_EVSYS_USER26 (*(RwReg *)0x4100E188UL) /**< \brief (EVSYS) User Multiplexer 26 */ |
| 464 | #define REG_EVSYS_USER27 (*(RwReg *)0x4100E18CUL) /**< \brief (EVSYS) User Multiplexer 27 */ |
| 465 | #define REG_EVSYS_USER28 (*(RwReg *)0x4100E190UL) /**< \brief (EVSYS) User Multiplexer 28 */ |
| 466 | #define REG_EVSYS_USER29 (*(RwReg *)0x4100E194UL) /**< \brief (EVSYS) User Multiplexer 29 */ |
| 467 | #define REG_EVSYS_USER30 (*(RwReg *)0x4100E198UL) /**< \brief (EVSYS) User Multiplexer 30 */ |
| 468 | #define REG_EVSYS_USER31 (*(RwReg *)0x4100E19CUL) /**< \brief (EVSYS) User Multiplexer 31 */ |
| 469 | #define REG_EVSYS_USER32 (*(RwReg *)0x4100E1A0UL) /**< \brief (EVSYS) User Multiplexer 32 */ |
| 470 | #define REG_EVSYS_USER33 (*(RwReg *)0x4100E1A4UL) /**< \brief (EVSYS) User Multiplexer 33 */ |
| 471 | #define REG_EVSYS_USER34 (*(RwReg *)0x4100E1A8UL) /**< \brief (EVSYS) User Multiplexer 34 */ |
| 472 | #define REG_EVSYS_USER35 (*(RwReg *)0x4100E1ACUL) /**< \brief (EVSYS) User Multiplexer 35 */ |
| 473 | #define REG_EVSYS_USER36 (*(RwReg *)0x4100E1B0UL) /**< \brief (EVSYS) User Multiplexer 36 */ |
| 474 | #define REG_EVSYS_USER37 (*(RwReg *)0x4100E1B4UL) /**< \brief (EVSYS) User Multiplexer 37 */ |
| 475 | #define REG_EVSYS_USER38 (*(RwReg *)0x4100E1B8UL) /**< \brief (EVSYS) User Multiplexer 38 */ |
| 476 | #define REG_EVSYS_USER39 (*(RwReg *)0x4100E1BCUL) /**< \brief (EVSYS) User Multiplexer 39 */ |
| 477 | #define REG_EVSYS_USER40 (*(RwReg *)0x4100E1C0UL) /**< \brief (EVSYS) User Multiplexer 40 */ |
| 478 | #define REG_EVSYS_USER41 (*(RwReg *)0x4100E1C4UL) /**< \brief (EVSYS) User Multiplexer 41 */ |
| 479 | #define REG_EVSYS_USER42 (*(RwReg *)0x4100E1C8UL) /**< \brief (EVSYS) User Multiplexer 42 */ |
| 480 | #define REG_EVSYS_USER43 (*(RwReg *)0x4100E1CCUL) /**< \brief (EVSYS) User Multiplexer 43 */ |
| 481 | #define REG_EVSYS_USER44 (*(RwReg *)0x4100E1D0UL) /**< \brief (EVSYS) User Multiplexer 44 */ |
| 482 | #define REG_EVSYS_USER45 (*(RwReg *)0x4100E1D4UL) /**< \brief (EVSYS) User Multiplexer 45 */ |
| 483 | #define REG_EVSYS_USER46 (*(RwReg *)0x4100E1D8UL) /**< \brief (EVSYS) User Multiplexer 46 */ |
| 484 | #define REG_EVSYS_USER47 (*(RwReg *)0x4100E1DCUL) /**< \brief (EVSYS) User Multiplexer 47 */ |
| 485 | #define REG_EVSYS_USER48 (*(RwReg *)0x4100E1E0UL) /**< \brief (EVSYS) User Multiplexer 48 */ |
| 486 | #define REG_EVSYS_USER49 (*(RwReg *)0x4100E1E4UL) /**< \brief (EVSYS) User Multiplexer 49 */ |
| 487 | #define REG_EVSYS_USER50 (*(RwReg *)0x4100E1E8UL) /**< \brief (EVSYS) User Multiplexer 50 */ |
| 488 | #define REG_EVSYS_USER51 (*(RwReg *)0x4100E1ECUL) /**< \brief (EVSYS) User Multiplexer 51 */ |
| 489 | #define REG_EVSYS_USER52 (*(RwReg *)0x4100E1F0UL) /**< \brief (EVSYS) User Multiplexer 52 */ |
| 490 | #define REG_EVSYS_USER53 (*(RwReg *)0x4100E1F4UL) /**< \brief (EVSYS) User Multiplexer 53 */ |
| 491 | #define REG_EVSYS_USER54 (*(RwReg *)0x4100E1F8UL) /**< \brief (EVSYS) User Multiplexer 54 */ |
| 492 | #define REG_EVSYS_USER55 (*(RwReg *)0x4100E1FCUL) /**< \brief (EVSYS) User Multiplexer 55 */ |
| 493 | #define REG_EVSYS_USER56 (*(RwReg *)0x4100E200UL) /**< \brief (EVSYS) User Multiplexer 56 */ |
| 494 | #define REG_EVSYS_USER57 (*(RwReg *)0x4100E204UL) /**< \brief (EVSYS) User Multiplexer 57 */ |
| 495 | #define REG_EVSYS_USER58 (*(RwReg *)0x4100E208UL) /**< \brief (EVSYS) User Multiplexer 58 */ |
| 496 | #define REG_EVSYS_USER59 (*(RwReg *)0x4100E20CUL) /**< \brief (EVSYS) User Multiplexer 59 */ |
| 497 | #define REG_EVSYS_USER60 (*(RwReg *)0x4100E210UL) /**< \brief (EVSYS) User Multiplexer 60 */ |
| 498 | #define REG_EVSYS_USER61 (*(RwReg *)0x4100E214UL) /**< \brief (EVSYS) User Multiplexer 61 */ |
| 499 | #define REG_EVSYS_USER62 (*(RwReg *)0x4100E218UL) /**< \brief (EVSYS) User Multiplexer 62 */ |
| 500 | #define REG_EVSYS_USER63 (*(RwReg *)0x4100E21CUL) /**< \brief (EVSYS) User Multiplexer 63 */ |
| 501 | #define REG_EVSYS_USER64 (*(RwReg *)0x4100E220UL) /**< \brief (EVSYS) User Multiplexer 64 */ |
| 502 | #define REG_EVSYS_USER65 (*(RwReg *)0x4100E224UL) /**< \brief (EVSYS) User Multiplexer 65 */ |
| 503 | #define REG_EVSYS_USER66 (*(RwReg *)0x4100E228UL) /**< \brief (EVSYS) User Multiplexer 66 */ |
| 504 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 505 | |
| 506 | /* ========== Instance parameters for EVSYS peripheral ========== */ |
| 507 | #define EVSYS_ASYNCHRONOUS_CHANNELS 0xFFFFF000 // Mask of Only Asynchronous Channels |
| 508 | #define EVSYS_CHANNELS 32 // Total Number of Channels |
| 509 | #define EVSYS_CHANNELS_BITS 5 // Number of bits to select Channel |
| 510 | #define EVSYS_EXTEVT_NUM 0 // Number of External Event Generators |
| 511 | #define EVSYS_GCLK_ID_0 11 |
| 512 | #define EVSYS_GCLK_ID_1 12 |
| 513 | #define EVSYS_GCLK_ID_2 13 |
| 514 | #define EVSYS_GCLK_ID_3 14 |
| 515 | #define EVSYS_GCLK_ID_4 15 |
| 516 | #define EVSYS_GCLK_ID_5 16 |
| 517 | #define EVSYS_GCLK_ID_6 17 |
| 518 | #define EVSYS_GCLK_ID_7 18 |
| 519 | #define EVSYS_GCLK_ID_8 19 |
| 520 | #define EVSYS_GCLK_ID_9 20 |
| 521 | #define EVSYS_GCLK_ID_10 21 |
| 522 | #define EVSYS_GCLK_ID_11 22 |
| 523 | #define EVSYS_GCLK_ID_LSB 11 |
| 524 | #define EVSYS_GCLK_ID_MSB 22 |
| 525 | #define EVSYS_GCLK_ID_SIZE 12 |
| 526 | #define EVSYS_GENERATORS 119 // Total Number of Event Generators |
| 527 | #define EVSYS_GENERATORS_BITS 7 // Number of bits to select Event Generator |
| 528 | #define EVSYS_SYNCH_NUM 12 // Number of Synchronous Channels |
| 529 | #define EVSYS_SYNCH_NUM_BITS 4 // Number of bits to select Synchronous Channels |
| 530 | #define EVSYS_USERS 67 // Total Number of Event Users |
| 531 | #define EVSYS_USERS_BITS 7 // Number of bits to select Event User |
| 532 | |
| 533 | // GENERATORS |
| 534 | #define EVSYS_ID_GEN_OSCCTRL_XOSC_FAIL_0 1 |
| 535 | #define EVSYS_ID_GEN_OSCCTRL_XOSC_FAIL_1 2 |
| 536 | #define EVSYS_ID_GEN_OSC32KCTRL_XOSC32K_FAIL 3 |
| 537 | #define EVSYS_ID_GEN_RTC_PER_0 4 |
| 538 | #define EVSYS_ID_GEN_RTC_PER_1 5 |
| 539 | #define EVSYS_ID_GEN_RTC_PER_2 6 |
| 540 | #define EVSYS_ID_GEN_RTC_PER_3 7 |
| 541 | #define EVSYS_ID_GEN_RTC_PER_4 8 |
| 542 | #define EVSYS_ID_GEN_RTC_PER_5 9 |
| 543 | #define EVSYS_ID_GEN_RTC_PER_6 10 |
| 544 | #define EVSYS_ID_GEN_RTC_PER_7 11 |
| 545 | #define EVSYS_ID_GEN_RTC_CMP_0 12 |
| 546 | #define EVSYS_ID_GEN_RTC_CMP_1 13 |
| 547 | #define EVSYS_ID_GEN_RTC_CMP_2 14 |
| 548 | #define EVSYS_ID_GEN_RTC_CMP_3 15 |
| 549 | #define EVSYS_ID_GEN_RTC_TAMPER 16 |
| 550 | #define EVSYS_ID_GEN_RTC_OVF 17 |
| 551 | #define EVSYS_ID_GEN_EIC_EXTINT_0 18 |
| 552 | #define EVSYS_ID_GEN_EIC_EXTINT_1 19 |
| 553 | #define EVSYS_ID_GEN_EIC_EXTINT_2 20 |
| 554 | #define EVSYS_ID_GEN_EIC_EXTINT_3 21 |
| 555 | #define EVSYS_ID_GEN_EIC_EXTINT_4 22 |
| 556 | #define EVSYS_ID_GEN_EIC_EXTINT_5 23 |
| 557 | #define EVSYS_ID_GEN_EIC_EXTINT_6 24 |
| 558 | #define EVSYS_ID_GEN_EIC_EXTINT_7 25 |
| 559 | #define EVSYS_ID_GEN_EIC_EXTINT_8 26 |
| 560 | #define EVSYS_ID_GEN_EIC_EXTINT_9 27 |
| 561 | #define EVSYS_ID_GEN_EIC_EXTINT_10 28 |
| 562 | #define EVSYS_ID_GEN_EIC_EXTINT_11 29 |
| 563 | #define EVSYS_ID_GEN_EIC_EXTINT_12 30 |
| 564 | #define EVSYS_ID_GEN_EIC_EXTINT_13 31 |
| 565 | #define EVSYS_ID_GEN_EIC_EXTINT_14 32 |
| 566 | #define EVSYS_ID_GEN_EIC_EXTINT_15 33 |
| 567 | #define EVSYS_ID_GEN_DMAC_CH_0 34 |
| 568 | #define EVSYS_ID_GEN_DMAC_CH_1 35 |
| 569 | #define EVSYS_ID_GEN_DMAC_CH_2 36 |
| 570 | #define EVSYS_ID_GEN_DMAC_CH_3 37 |
| 571 | #define EVSYS_ID_GEN_PAC_ACCERR 38 |
| 572 | #define EVSYS_ID_GEN_TCC0_OVF 41 |
| 573 | #define EVSYS_ID_GEN_TCC0_TRG 42 |
| 574 | #define EVSYS_ID_GEN_TCC0_CNT 43 |
| Harald Welte | 9bb8bfe | 2019-05-17 16:10:00 +0200 | [diff] [blame] | 575 | #define EVSYS_ID_GEN_TCC0_MC_0 44
|
| 576 | #define EVSYS_ID_GEN_TCC0_MC_1 45
|
| 577 | #define EVSYS_ID_GEN_TCC0_MC_2 46
|
| 578 | #define EVSYS_ID_GEN_TCC0_MC_3 47
|
| 579 | #define EVSYS_ID_GEN_TCC0_MC_4 48
|
| 580 | #define EVSYS_ID_GEN_TCC0_MC_5 49
|
| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 581 | #define EVSYS_ID_GEN_TCC1_OVF 50 |
| 582 | #define EVSYS_ID_GEN_TCC1_TRG 51 |
| 583 | #define EVSYS_ID_GEN_TCC1_CNT 52 |
| Harald Welte | 9bb8bfe | 2019-05-17 16:10:00 +0200 | [diff] [blame] | 584 | #define EVSYS_ID_GEN_TCC1_MC_0 53
|
| 585 | #define EVSYS_ID_GEN_TCC1_MC_1 54
|
| 586 | #define EVSYS_ID_GEN_TCC1_MC_2 55
|
| 587 | #define EVSYS_ID_GEN_TCC1_MC_3 56
|
| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 588 | #define EVSYS_ID_GEN_TCC2_OVF 57 |
| 589 | #define EVSYS_ID_GEN_TCC2_TRG 58 |
| 590 | #define EVSYS_ID_GEN_TCC2_CNT 59 |
| Harald Welte | 9bb8bfe | 2019-05-17 16:10:00 +0200 | [diff] [blame] | 591 | #define EVSYS_ID_GEN_TCC2_MC_0 60
|
| 592 | #define EVSYS_ID_GEN_TCC2_MC_1 61
|
| 593 | #define EVSYS_ID_GEN_TCC2_MC_2 62
|
| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 594 | #define EVSYS_ID_GEN_TCC3_OVF 63 |
| 595 | #define EVSYS_ID_GEN_TCC3_TRG 64 |
| 596 | #define EVSYS_ID_GEN_TCC3_CNT 65 |
| Harald Welte | 9bb8bfe | 2019-05-17 16:10:00 +0200 | [diff] [blame] | 597 | #define EVSYS_ID_GEN_TCC3_MC_0 66
|
| 598 | #define EVSYS_ID_GEN_TCC3_MC_1 67
|
| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 599 | #define EVSYS_ID_GEN_TCC4_OVF 68 |
| 600 | #define EVSYS_ID_GEN_TCC4_TRG 69 |
| 601 | #define EVSYS_ID_GEN_TCC4_CNT 70 |
| Harald Welte | 9bb8bfe | 2019-05-17 16:10:00 +0200 | [diff] [blame] | 602 | #define EVSYS_ID_GEN_TCC4_MC_0 71
|
| 603 | #define EVSYS_ID_GEN_TCC4_MC_1 72
|
| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 604 | #define EVSYS_ID_GEN_TC0_OVF 73 |
| Harald Welte | 9bb8bfe | 2019-05-17 16:10:00 +0200 | [diff] [blame] | 605 | #define EVSYS_ID_GEN_TC0_MC_0 74
|
| 606 | #define EVSYS_ID_GEN_TC0_MC_1 75
|
| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 607 | #define EVSYS_ID_GEN_TC1_OVF 76 |
| Harald Welte | 9bb8bfe | 2019-05-17 16:10:00 +0200 | [diff] [blame] | 608 | #define EVSYS_ID_GEN_TC1_MC_0 77
|
| 609 | #define EVSYS_ID_GEN_TC1_MC_1 78
|
| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 610 | #define EVSYS_ID_GEN_TC2_OVF 79 |
| Harald Welte | 9bb8bfe | 2019-05-17 16:10:00 +0200 | [diff] [blame] | 611 | #define EVSYS_ID_GEN_TC2_MC_0 80
|
| 612 | #define EVSYS_ID_GEN_TC2_MC_1 81
|
| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 613 | #define EVSYS_ID_GEN_TC3_OVF 82 |
| Harald Welte | 9bb8bfe | 2019-05-17 16:10:00 +0200 | [diff] [blame] | 614 | #define EVSYS_ID_GEN_TC3_MC_0 83
|
| 615 | #define EVSYS_ID_GEN_TC3_MC_1 84
|
| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 616 | #define EVSYS_ID_GEN_TC4_OVF 85 |
| Harald Welte | 9bb8bfe | 2019-05-17 16:10:00 +0200 | [diff] [blame] | 617 | #define EVSYS_ID_GEN_TC4_MC_0 86
|
| 618 | #define EVSYS_ID_GEN_TC4_MC_1 87
|
| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 619 | #define EVSYS_ID_GEN_TC5_OVF 88 |
| Harald Welte | 9bb8bfe | 2019-05-17 16:10:00 +0200 | [diff] [blame] | 620 | #define EVSYS_ID_GEN_TC5_MC_0 89
|
| 621 | #define EVSYS_ID_GEN_TC5_MC_1 90
|
| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 622 | #define EVSYS_ID_GEN_TC6_OVF 91 |
| Harald Welte | 9bb8bfe | 2019-05-17 16:10:00 +0200 | [diff] [blame] | 623 | #define EVSYS_ID_GEN_TC6_MC_0 92
|
| 624 | #define EVSYS_ID_GEN_TC6_MC_1 93
|
| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 625 | #define EVSYS_ID_GEN_TC7_OVF 94 |
| Harald Welte | 9bb8bfe | 2019-05-17 16:10:00 +0200 | [diff] [blame] | 626 | #define EVSYS_ID_GEN_TC7_MC_0 95
|
| 627 | #define EVSYS_ID_GEN_TC7_MC_1 96
|
| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 628 | #define EVSYS_ID_GEN_PDEC_OVF 97 |
| 629 | #define EVSYS_ID_GEN_PDEC_ERR 98 |
| 630 | #define EVSYS_ID_GEN_PDEC_DIR 99 |
| 631 | #define EVSYS_ID_GEN_PDEC_VLC 100 |
| Harald Welte | 9bb8bfe | 2019-05-17 16:10:00 +0200 | [diff] [blame] | 632 | #define EVSYS_ID_GEN_PDEC_MC_0 101
|
| 633 | #define EVSYS_ID_GEN_PDEC_MC_1 102
|
| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 634 | #define EVSYS_ID_GEN_ADC0_RESRDY 103 |
| 635 | #define EVSYS_ID_GEN_ADC0_WINMON 104 |
| 636 | #define EVSYS_ID_GEN_ADC1_RESRDY 105 |
| 637 | #define EVSYS_ID_GEN_ADC1_WINMON 106 |
| 638 | #define EVSYS_ID_GEN_AC_COMP_0 107 |
| 639 | #define EVSYS_ID_GEN_AC_COMP_1 108 |
| 640 | #define EVSYS_ID_GEN_AC_WIN_0 109 |
| 641 | #define EVSYS_ID_GEN_DAC_EMPTY_0 110 |
| 642 | #define EVSYS_ID_GEN_DAC_EMPTY_1 111 |
| 643 | #define EVSYS_ID_GEN_DAC_RESRDY_0 112 |
| 644 | #define EVSYS_ID_GEN_DAC_RESRDY_1 113 |
| 645 | #define EVSYS_ID_GEN_GMAC_TSU_CMP 114 |
| 646 | #define EVSYS_ID_GEN_TRNG_READY 115 |
| 647 | #define EVSYS_ID_GEN_CCL_LUTOUT_0 116 |
| 648 | #define EVSYS_ID_GEN_CCL_LUTOUT_1 117 |
| 649 | #define EVSYS_ID_GEN_CCL_LUTOUT_2 118 |
| 650 | #define EVSYS_ID_GEN_CCL_LUTOUT_3 119 |
| 651 | |
| 652 | // USERS |
| 653 | #define EVSYS_ID_USER_RTC_TAMPER 0 |
| 654 | #define EVSYS_ID_USER_PORT_EV_0 1 |
| 655 | #define EVSYS_ID_USER_PORT_EV_1 2 |
| 656 | #define EVSYS_ID_USER_PORT_EV_2 3 |
| 657 | #define EVSYS_ID_USER_PORT_EV_3 4 |
| 658 | #define EVSYS_ID_USER_DMAC_CH_0 5 |
| 659 | #define EVSYS_ID_USER_DMAC_CH_1 6 |
| 660 | #define EVSYS_ID_USER_DMAC_CH_2 7 |
| 661 | #define EVSYS_ID_USER_DMAC_CH_3 8 |
| 662 | #define EVSYS_ID_USER_DMAC_CH_4 9 |
| 663 | #define EVSYS_ID_USER_DMAC_CH_5 10 |
| 664 | #define EVSYS_ID_USER_DMAC_CH_6 11 |
| 665 | #define EVSYS_ID_USER_DMAC_CH_7 12 |
| 666 | #define EVSYS_ID_USER_CM4_TRACE_START 14 |
| 667 | #define EVSYS_ID_USER_CM4_TRACE_STOP 15 |
| 668 | #define EVSYS_ID_USER_CM4_TRACE_TRIG 16 |
| 669 | #define EVSYS_ID_USER_TCC0_EV_0 17 |
| 670 | #define EVSYS_ID_USER_TCC0_EV_1 18 |
| 671 | #define EVSYS_ID_USER_TCC0_MC_0 19 |
| 672 | #define EVSYS_ID_USER_TCC0_MC_1 20 |
| 673 | #define EVSYS_ID_USER_TCC0_MC_2 21 |
| 674 | #define EVSYS_ID_USER_TCC0_MC_3 22 |
| 675 | #define EVSYS_ID_USER_TCC0_MC_4 23 |
| 676 | #define EVSYS_ID_USER_TCC0_MC_5 24 |
| 677 | #define EVSYS_ID_USER_TCC1_EV_0 25 |
| 678 | #define EVSYS_ID_USER_TCC1_EV_1 26 |
| 679 | #define EVSYS_ID_USER_TCC1_MC_0 27 |
| 680 | #define EVSYS_ID_USER_TCC1_MC_1 28 |
| 681 | #define EVSYS_ID_USER_TCC1_MC_2 29 |
| 682 | #define EVSYS_ID_USER_TCC1_MC_3 30 |
| 683 | #define EVSYS_ID_USER_TCC2_EV_0 31 |
| 684 | #define EVSYS_ID_USER_TCC2_EV_1 32 |
| 685 | #define EVSYS_ID_USER_TCC2_MC_0 33 |
| 686 | #define EVSYS_ID_USER_TCC2_MC_1 34 |
| 687 | #define EVSYS_ID_USER_TCC2_MC_2 35 |
| 688 | #define EVSYS_ID_USER_TCC3_EV_0 36 |
| 689 | #define EVSYS_ID_USER_TCC3_EV_1 37 |
| 690 | #define EVSYS_ID_USER_TCC3_MC_0 38 |
| 691 | #define EVSYS_ID_USER_TCC3_MC_1 39 |
| 692 | #define EVSYS_ID_USER_TCC4_EV_0 40 |
| 693 | #define EVSYS_ID_USER_TCC4_EV_1 41 |
| 694 | #define EVSYS_ID_USER_TCC4_MC_0 42 |
| 695 | #define EVSYS_ID_USER_TCC4_MC_1 43 |
| 696 | #define EVSYS_ID_USER_TC0_EVU 44 |
| 697 | #define EVSYS_ID_USER_TC1_EVU 45 |
| 698 | #define EVSYS_ID_USER_TC2_EVU 46 |
| 699 | #define EVSYS_ID_USER_TC3_EVU 47 |
| 700 | #define EVSYS_ID_USER_TC4_EVU 48 |
| 701 | #define EVSYS_ID_USER_TC5_EVU 49 |
| 702 | #define EVSYS_ID_USER_TC6_EVU 50 |
| 703 | #define EVSYS_ID_USER_TC7_EVU 51 |
| 704 | #define EVSYS_ID_USER_PDEC_EVU_0 52 |
| 705 | #define EVSYS_ID_USER_PDEC_EVU_1 53 |
| 706 | #define EVSYS_ID_USER_PDEC_EVU_2 54 |
| 707 | #define EVSYS_ID_USER_ADC0_START 55 |
| 708 | #define EVSYS_ID_USER_ADC0_SYNC 56 |
| 709 | #define EVSYS_ID_USER_ADC1_START 57 |
| 710 | #define EVSYS_ID_USER_ADC1_SYNC 58 |
| 711 | #define EVSYS_ID_USER_AC_SOC_0 59 |
| 712 | #define EVSYS_ID_USER_AC_SOC_1 60 |
| 713 | #define EVSYS_ID_USER_DAC_START_0 61 |
| 714 | #define EVSYS_ID_USER_DAC_START_1 62 |
| 715 | #define EVSYS_ID_USER_CCL_LUTIN_0 63 |
| 716 | #define EVSYS_ID_USER_CCL_LUTIN_1 64 |
| 717 | #define EVSYS_ID_USER_CCL_LUTIN_2 65 |
| 718 | #define EVSYS_ID_USER_CCL_LUTIN_3 66 |
| 719 | |
| 720 | #endif /* _SAME54_EVSYS_INSTANCE_ */ |