| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /* Auto-generated config file hpl_mclk_config.h */ |
| 2 | #ifndef HPL_MCLK_CONFIG_H |
| 3 | #define HPL_MCLK_CONFIG_H |
| 4 | |
| 5 | // <<< Use Configuration Wizard in Context Menu >>> |
| 6 | |
| 7 | #include <peripheral_clk_config.h> |
| 8 | |
| 9 | // <e> System Configuration |
| 10 | // <i> Indicates whether configuration for system is enabled or not |
| 11 | // <id> enable_cpu_clock |
| 12 | #ifndef CONF_SYSTEM_CONFIG |
| 13 | #define CONF_SYSTEM_CONFIG 1 |
| 14 | #endif |
| 15 | |
| 16 | // <h> Basic settings |
| 17 | // <y> CPU Clock source |
| 18 | // <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 |
| 19 | // <i> This defines the clock source for the CPU |
| 20 | // <id> cpu_clock_source |
| 21 | #ifndef CONF_CPU_SRC |
| 22 | #define CONF_CPU_SRC GCLK_PCHCTRL_GEN_GCLK0_Val |
| 23 | #endif |
| 24 | |
| 25 | // <y> CPU Clock Division Factor |
| 26 | // <MCLK_CPUDIV_DIV_DIV1_Val"> 1 |
| 27 | // <MCLK_CPUDIV_DIV_DIV2_Val"> 2 |
| 28 | // <MCLK_CPUDIV_DIV_DIV4_Val"> 4 |
| 29 | // <MCLK_CPUDIV_DIV_DIV8_Val"> 8 |
| 30 | // <MCLK_CPUDIV_DIV_DIV16_Val"> 16 |
| 31 | // <MCLK_CPUDIV_DIV_DIV32_Val"> 32 |
| 32 | // <MCLK_CPUDIV_DIV_DIV64_Val"> 64 |
| 33 | // <MCLK_CPUDIV_DIV_DIV128_Val"> 128 |
| 34 | // <i> Prescalar for CPU clock |
| 35 | // <id> cpu_div |
| 36 | #ifndef CONF_MCLK_CPUDIV |
| 37 | #define CONF_MCLK_CPUDIV MCLK_CPUDIV_DIV_DIV1_Val |
| 38 | #endif |
| 39 | // <y> Low Power Clock Division |
| 40 | // <MCLK_LPDIV_LPDIV_DIV1_Val"> Divide by 1 |
| 41 | // <MCLK_LPDIV_LPDIV_DIV2_Val"> Divide by 2 |
| 42 | // <MCLK_LPDIV_LPDIV_DIV4_Val"> Divide by 4 |
| 43 | // <MCLK_LPDIV_LPDIV_DIV8_Val"> Divide by 8 |
| 44 | // <MCLK_LPDIV_LPDIV_DIV16_Val"> Divide by 16 |
| 45 | // <MCLK_LPDIV_LPDIV_DIV32_Val"> Divide by 32 |
| 46 | // <MCLK_LPDIV_LPDIV_DIV64_Val"> Divide by 64 |
| 47 | // <MCLK_LPDIV_LPDIV_DIV128_Val"> Divide by 128 |
| 48 | // <id> mclk_arch_lpdiv |
| 49 | #ifndef CONF_MCLK_LPDIV |
| 50 | #define CONF_MCLK_LPDIV MCLK_LPDIV_LPDIV_DIV4_Val |
| 51 | #endif |
| 52 | |
| 53 | // <y> Backup Clock Division |
| 54 | // <MCLK_BUPDIV_BUPDIV_DIV1_Val"> Divide by 1 |
| 55 | // <MCLK_BUPDIV_BUPDIV_DIV2_Val"> Divide by 2 |
| 56 | // <MCLK_BUPDIV_BUPDIV_DIV4_Val"> Divide by 4 |
| 57 | // <MCLK_BUPDIV_BUPDIV_DIV8_Val"> Divide by 8 |
| 58 | // <MCLK_BUPDIV_BUPDIV_DIV16_Val"> Divide by 16 |
| 59 | // <MCLK_BUPDIV_BUPDIV_DIV32_Val"> Divide by 32 |
| 60 | // <MCLK_BUPDIV_BUPDIV_DIV64_Val"> Divide by 64 |
| 61 | // <MCLK_BUPDIV_BUPDIV_DIV128_Val"> Divide by 128 |
| 62 | // <id> mclk_arch_bupdiv |
| 63 | #ifndef CONF_MCLK_BUPDIV |
| 64 | #define CONF_MCLK_BUPDIV MCLK_BUPDIV_BUPDIV_DIV8_Val |
| 65 | #endif |
| 66 | // <y> High-Speed Clock Division |
| 67 | // <MCLK_HSDIV_DIV_DIV1_Val"> Divide by 1 |
| 68 | // <id> mclk_arch_hsdiv |
| 69 | #ifndef CONF_MCLK_HSDIV |
| 70 | #define CONF_MCLK_HSDIV MCLK_HSDIV_DIV_DIV1_Val |
| 71 | #endif |
| 72 | // </h> |
| 73 | |
| 74 | // <h> NVM Settings |
| 75 | // <o> NVM Wait States |
| 76 | // <i> These bits select the number of wait states for a read operation. |
| 77 | // <0=> 0 |
| 78 | // <1=> 1 |
| 79 | // <2=> 2 |
| 80 | // <3=> 3 |
| 81 | // <4=> 4 |
| 82 | // <5=> 5 |
| 83 | // <6=> 6 |
| 84 | // <7=> 7 |
| 85 | // <8=> 8 |
| 86 | // <9=> 9 |
| 87 | // <10=> 10 |
| 88 | // <11=> 11 |
| 89 | // <12=> 12 |
| 90 | // <13=> 13 |
| 91 | // <14=> 14 |
| 92 | // <15=> 15 |
| 93 | // <id> nvm_wait_states |
| 94 | #ifndef CONF_NVM_WAIT_STATE |
| 95 | #define CONF_NVM_WAIT_STATE 0 |
| 96 | #endif |
| 97 | |
| 98 | // </h> |
| 99 | |
| 100 | // </e> |
| 101 | |
| 102 | // <<< end of configuration section >>> |
| 103 | |
| 104 | #endif // HPL_MCLK_CONFIG_H |