blob: 7b513a5659b8154bf5d08d877fa7750114ea7240 [file] [log] [blame]
Harald Welte727d6752019-09-30 21:46:44 +02001/* Code providing a ccid_slot_ops implementation based on iso7716_fsm,
2 * (which in turn sits on top of card_uart) */
3
4#include <unistd.h>
5#include <errno.h>
Harald Welte6def1cf2019-10-10 15:40:02 +02006#include <string.h>
Harald Welte727d6752019-09-30 21:46:44 +02007
8#include <osmocom/core/msgb.h>
9#include <osmocom/core/timer.h>
10#include <osmocom/core/logging.h>
11#include <osmocom/core/fsm.h>
12
13#include "ccid_device.h"
14#include "cuart.h"
15#include "iso7816_fsm.h"
16
17struct iso_fsm_slot {
18 /* CCID slot above us */
19 struct ccid_slot *cs;
20 /* main ISO7816-3 FSM instance beneath us */
21 struct osmo_fsm_inst *fi;
22 /* UART beneath the ISO7816-3 FSM */
23 struct card_uart *cuart;
24 /* bSeq of the operation currently in progress */
25 uint8_t seq;
26};
27
28struct iso_fsm_slot_instance {
29 struct iso_fsm_slot slot[NR_SLOTS];
30};
31
32static struct iso_fsm_slot_instance g_si;
33
34struct iso_fsm_slot *ccid_slot2iso_fsm_slot(struct ccid_slot *cs)
35{
36 OSMO_ASSERT(cs->slot_nr < ARRAY_SIZE(g_si.slot));
37 return &g_si.slot[cs->slot_nr];
38}
39
40static const uint8_t sysmousim_sjs1_atr[] = {
41 0x3B, 0x9F, 0x96, 0x80, 0x1F, 0xC7, 0x80, 0x31,
42 0xA0, 0x73, 0xBE, 0x21, 0x13, 0x67, 0x43, 0x20,
43 0x07, 0x18, 0x00, 0x00, 0x01, 0xA5 };
44
45static const struct ccid_pars_decoded iso_fsm_def_pars = {
46 .fi = 372,
47 .di = 1,
48 .clock_stop = CCID_CLOCK_STOP_NOTALLOWED,
49 .inverse_convention = false,
50 .t0 = {
51 .guard_time_etu = 0,
52 .waiting_integer = 0,
53 },
54 /* FIXME: T=1 */
55};
56
57static void iso_fsm_slot_pre_proc_cb(struct ccid_slot *cs, struct msgb *msg)
58{
59 /* do nothing; real hardware would update the slot related state here */
60}
61
62static void iso_fsm_slot_icc_power_on_async(struct ccid_slot *cs, struct msgb *msg,
63 const struct ccid_pc_to_rdr_icc_power_on *ipo)
64{
65 struct iso_fsm_slot *ss = ccid_slot2iso_fsm_slot(cs);
66
67 ss->seq = ipo->hdr.bSeq;
68 LOGPCS(cs, LOGL_DEBUG, "scheduling power-up\n");
69
70 /* FIXME: do this via a FSM? */
71 card_uart_ctrl(ss->cuart, CUART_CTL_RST, true);
Harald Weltef54a6b22019-10-10 13:30:24 +020072 osmo_fsm_inst_dispatch(ss->fi, ISO7816_E_RESET_ACT_IND, NULL);
Harald Welte727d6752019-09-30 21:46:44 +020073 card_uart_ctrl(ss->cuart, CUART_CTL_POWER, true);
74 osmo_fsm_inst_dispatch(ss->fi, ISO7816_E_POWER_UP_IND, NULL);
75 cs->icc_powered = true;
76 card_uart_ctrl(ss->cuart, CUART_CTL_CLOCK, true);
77 usleep(10000);
78 card_uart_ctrl(ss->cuart, CUART_CTL_RST, false);
79 osmo_fsm_inst_dispatch(ss->fi, ISO7816_E_RESET_REL_IND, NULL);
80
81 msgb_free(msg);
82 /* continues in iso_fsm_clot_user_cb once ATR is received */
83}
84static void iso_fsm_clot_user_cb(struct osmo_fsm_inst *fi, int event, int cause, void *data)
85{
86 struct iso_fsm_slot *ss = iso7816_fsm_get_user_priv(fi);
87 struct ccid_slot *cs = ss->cs;
88 struct msgb *tpdu, *resp;
89
90 LOGPCS(cs, LOGL_DEBUG, "%s(event=%d, cause=%d, data=%p)\n", __func__, event, cause, data);
91
92 switch (event) {
93 case ISO7816_E_ATR_DONE_IND:
94 tpdu = data;
95 /* FIXME: copy response data over */
96 resp = ccid_gen_data_block(cs, ss->seq, CCID_CMD_STATUS_OK, 0,
97 msgb_data(tpdu), msgb_length(tpdu));
98 ccid_slot_send_unbusy(cs, resp);
Harald Weltebbb50092019-10-10 14:55:25 +020099 /* Don't free "TPDU" here, as the ATR should survive */
Harald Welte727d6752019-09-30 21:46:44 +0200100 break;
101 case ISO7816_E_TPDU_DONE_IND:
102 tpdu = data;
103 /* FIXME: copy response data over */
104 resp = ccid_gen_data_block(cs, ss->seq, CCID_CMD_STATUS_OK, 0, msgb_l2(tpdu), msgb_l2len(tpdu));
105 ccid_slot_send_unbusy(cs, resp);
106 msgb_free(tpdu);
107 break;
108 }
109}
110
111static void iso_fsm_slot_xfr_block_async(struct ccid_slot *cs, struct msgb *msg,
112 const struct ccid_pc_to_rdr_xfr_block *xfb)
113{
114 struct iso_fsm_slot *ss = ccid_slot2iso_fsm_slot(cs);
Harald Welte6def1cf2019-10-10 15:40:02 +0200115 struct msgb *tpdu;
Harald Welte727d6752019-09-30 21:46:44 +0200116
Harald Welte727d6752019-09-30 21:46:44 +0200117 ss->seq = xfb->hdr.bSeq;
Harald Welte6def1cf2019-10-10 15:40:02 +0200118
119 /* must be '0' for TPDU level exchanges or for short APDU */
120 OSMO_ASSERT(xfb->wLevelParameter == 0x0000);
121 OSMO_ASSERT(msgb_length(msg) > xfb->hdr.dwLength);
122
123 /* 'msg' contains the raw CCID message as received from USB. We could create
124 * a new message buffer for the ISO7816 side here or we could 'strip the CCID
125 * header off the start of the message. Let's KISS and do a copy here */
126 tpdu = msgb_alloc(512, "TPDU");
127 OSMO_ASSERT(tpdu);
128 memcpy(msgb_data(tpdu), xfb->abData, xfb->hdr.dwLength);
129 msgb_put(tpdu, xfb->hdr.dwLength);
130 msgb_free(msg);
131
132 LOGPCS(cs, LOGL_DEBUG, "scheduling TPDU transfer: %s\n", msgb_hexdump(tpdu));
133 osmo_fsm_inst_dispatch(ss->fi, ISO7816_E_XCEIVE_TPDU_CMD, tpdu);
Harald Welte727d6752019-09-30 21:46:44 +0200134 /* continues in iso_fsm_clot_user_cb once response/error/timeout is received */
135}
136
137
138static void iso_fsm_slot_set_power(struct ccid_slot *cs, bool enable)
139{
140 struct iso_fsm_slot *ss = ccid_slot2iso_fsm_slot(cs);
141
142 if (enable) {
143 card_uart_ctrl(ss->cuart, CUART_CTL_POWER, true);
144 } else {
145 card_uart_ctrl(ss->cuart, CUART_CTL_POWER, false);
146 }
147}
148
149static void iso_fsm_slot_set_clock(struct ccid_slot *cs, enum ccid_clock_command cmd)
150{
151 struct iso_fsm_slot *ss = ccid_slot2iso_fsm_slot(cs);
152
153 switch (cmd) {
154 case CCID_CLOCK_CMD_STOP:
155 card_uart_ctrl(ss->cuart, CUART_CTL_CLOCK, false);
156 break;
157 case CCID_CLOCK_CMD_RESTART:
158 card_uart_ctrl(ss->cuart, CUART_CTL_CLOCK, true);
159 break;
160 default:
161 OSMO_ASSERT(0);
162 }
163}
164
165static int iso_fsm_slot_set_params(struct ccid_slot *cs, enum ccid_protocol_num proto,
166 const struct ccid_pars_decoded *pars_dec)
167{
168 /* we always acknowledge all parameters */
169 return 0;
170}
171
172static int iso_fsm_slot_set_rate_and_clock(struct ccid_slot *cs, uint32_t freq_hz, uint32_t rate_bps)
173{
174 /* we always acknowledge all rates/clocks */
175 return 0;
176}
177
178
179static int iso_fsm_slot_init(struct ccid_slot *cs)
180{
181 void *ctx = NULL; /* FIXME */
182 struct iso_fsm_slot *ss = ccid_slot2iso_fsm_slot(cs);
183 struct card_uart *cuart = talloc_zero(ctx, struct card_uart);
184 char id_buf[16];
Harald Welte515d5b22019-10-10 13:46:13 +0200185 char *devname = NULL;
Harald Welte727d6752019-09-30 21:46:44 +0200186 int rc;
187
188 LOGPCS(cs, LOGL_DEBUG, "%s\n", __func__);
189
Harald Welte515d5b22019-10-10 13:46:13 +0200190 /* HACK: make this in some way configurable so it works both in the firmware
191 * and on the host (functionfs) */
Harald Welte727d6752019-09-30 21:46:44 +0200192 if (cs->slot_nr == 0) {
193 cs->icc_present = true;
194 devname = "/dev/ttyUSB5";
195 }
196
197 if (!cuart)
198 return -ENOMEM;
199
200 snprintf(id_buf, sizeof(id_buf), "SIM%d", cs->slot_nr);
Harald Welte515d5b22019-10-10 13:46:13 +0200201 if (devname) {
202 rc = card_uart_open(cuart, "tty", devname);
203 if (rc < 0) {
204 LOGPCS(cs, LOGL_ERROR, "Cannot open UART %s: %d\n", devname, rc);
205 talloc_free(cuart);
206 return rc;
207 }
Harald Welte727d6752019-09-30 21:46:44 +0200208 }
209 ss->fi = iso7816_fsm_alloc(ctx, LOGL_DEBUG, id_buf, cuart, iso_fsm_clot_user_cb, ss);
210 if (!ss->fi) {
Harald Welte515d5b22019-10-10 13:46:13 +0200211 LOGPCS(cs, LOGL_ERROR, "Cannot allocate ISO FSM\n");
Harald Welte727d6752019-09-30 21:46:44 +0200212 talloc_free(cuart);
213 return -1;
214 }
215
216 cs->default_pars = &iso_fsm_def_pars;
217 ss->cuart = cuart;
218 ss->cs = cs;
219
220
221 return 0;
222}
223
224const struct ccid_slot_ops iso_fsm_slot_ops = {
225 .init = iso_fsm_slot_init,
226 .pre_proc_cb = iso_fsm_slot_pre_proc_cb,
227 .icc_power_on_async = iso_fsm_slot_icc_power_on_async,
228 .xfr_block_async = iso_fsm_slot_xfr_block_async,
229 .set_power = iso_fsm_slot_set_power,
230 .set_clock = iso_fsm_slot_set_clock,
231 .set_params = iso_fsm_slot_set_params,
232 .set_rate_and_clock = iso_fsm_slot_set_rate_and_clock,
233};