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gerrit.osmocom.org / osmo-ccid-firmware / 61dad9145f9c4ffae6de6e8c53b2a8168a3cbebe / . / sysmoOCTSIM / config / peripheral_clk_config.h
blob: 91c5c867024111929c9d5a82090fbf2b19644205 [file] [log] [blame]
Kévin Redon69b92d92019-01-24 16:39:20 +0100[diff] [blame]1/* Auto-generated config file peripheral_clk_config.h */
2#ifndef PERIPHERAL_CLK_CONFIG_H
3#define PERIPHERAL_CLK_CONFIG_H
4
5// <<< Use Configuration Wizard in Context Menu >>>
6
7/**
8 * \def CONF_CPU_FREQUENCY
9 * \brief CPU's Clock frequency
10 */
11#ifndef CONF_CPU_FREQUENCY
Kévin Redon4a2d8f42019-01-24 17:15:10 +0100[diff] [blame]12#define CONF_CPU_FREQUENCY 120000000
Kévin Redon69b92d92019-01-24 16:39:20 +0100[diff] [blame]13#endif
14
Kévin Redon4cd3f7d2019-01-24 17:57:13 +0100[diff] [blame]15// <y> Core Clock Source
16// <id> core_gclk_selection
17
18// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
19
20// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
21
22// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
23
24// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
25
26// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
27
28// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
29
30// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
31
32// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
33
34// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
35
36// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
37
38// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
39
40// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
41
42// <i> Select the clock source for CORE.
Kévin Redon1f8ecef2019-01-31 13:36:12 +0100[diff] [blame]43#ifndef CONF_GCLK_SERCOM0_CORE_SRC
44#define CONF_GCLK_SERCOM0_CORE_SRC GCLK_PCHCTRL_GEN_GCLK2_Val
45#endif
46
47// <y> Slow Clock Source
48// <id> slow_gclk_selection
49
50// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
51
52// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
53
54// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
55
56// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
57
58// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
59
60// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
61
62// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
63
64// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
65
66// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
67
68// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
69
70// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
71
72// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
73
74// <i> Select the slow clock source.
75#ifndef CONF_GCLK_SERCOM0_SLOW_SRC
76#define CONF_GCLK_SERCOM0_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
77#endif
78
79/**
80 * \def CONF_GCLK_SERCOM0_CORE_FREQUENCY
81 * \brief SERCOM0's Core Clock frequency
82 */
83#ifndef CONF_GCLK_SERCOM0_CORE_FREQUENCY
84#define CONF_GCLK_SERCOM0_CORE_FREQUENCY 100000000
85#endif
86
87/**
88 * \def CONF_GCLK_SERCOM0_SLOW_FREQUENCY
89 * \brief SERCOM0's Slow Clock frequency
90 */
91#ifndef CONF_GCLK_SERCOM0_SLOW_FREQUENCY
92#define CONF_GCLK_SERCOM0_SLOW_FREQUENCY 32768
93#endif
94
95// <y> Core Clock Source
96// <id> core_gclk_selection
97
98// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
99
100// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
101
102// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
103
104// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
105
106// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
107
108// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
109
110// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
111
112// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
113
114// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
115
116// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
117
118// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
119
120// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
121
122// <i> Select the clock source for CORE.
123#ifndef CONF_GCLK_SERCOM1_CORE_SRC
124#define CONF_GCLK_SERCOM1_CORE_SRC GCLK_PCHCTRL_GEN_GCLK2_Val
125#endif
126
127// <y> Slow Clock Source
128// <id> slow_gclk_selection
129
130// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
131
132// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
133
134// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
135
136// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
137
138// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
139
140// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
141
142// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
143
144// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
145
146// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
147
148// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
149
150// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
151
152// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
153
154// <i> Select the slow clock source.
155#ifndef CONF_GCLK_SERCOM1_SLOW_SRC
156#define CONF_GCLK_SERCOM1_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
157#endif
158
159/**
160 * \def CONF_GCLK_SERCOM1_CORE_FREQUENCY
161 * \brief SERCOM1's Core Clock frequency
162 */
163#ifndef CONF_GCLK_SERCOM1_CORE_FREQUENCY
164#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 100000000
165#endif
166
167/**
168 * \def CONF_GCLK_SERCOM1_SLOW_FREQUENCY
169 * \brief SERCOM1's Slow Clock frequency
170 */
171#ifndef CONF_GCLK_SERCOM1_SLOW_FREQUENCY
172#define CONF_GCLK_SERCOM1_SLOW_FREQUENCY 32768
173#endif
174
175// <y> Core Clock Source
176// <id> core_gclk_selection
177
178// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
179
180// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
181
182// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
183
184// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
185
186// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
187
188// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
189
190// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
191
192// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
193
194// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
195
196// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
197
198// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
199
200// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
201
202// <i> Select the clock source for CORE.
203#ifndef CONF_GCLK_SERCOM2_CORE_SRC
204#define CONF_GCLK_SERCOM2_CORE_SRC GCLK_PCHCTRL_GEN_GCLK2_Val
205#endif
206
207// <y> Slow Clock Source
208// <id> slow_gclk_selection
209
210// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
211
212// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
213
214// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
215
216// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
217
218// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
219
220// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
221
222// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
223
224// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
225
226// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
227
228// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
229
230// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
231
232// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
233
234// <i> Select the slow clock source.
235#ifndef CONF_GCLK_SERCOM2_SLOW_SRC
236#define CONF_GCLK_SERCOM2_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
237#endif
238
239/**
240 * \def CONF_GCLK_SERCOM2_CORE_FREQUENCY
241 * \brief SERCOM2's Core Clock frequency
242 */
243#ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY
244#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 100000000
245#endif
246
247/**
248 * \def CONF_GCLK_SERCOM2_SLOW_FREQUENCY
249 * \brief SERCOM2's Slow Clock frequency
250 */
251#ifndef CONF_GCLK_SERCOM2_SLOW_FREQUENCY
252#define CONF_GCLK_SERCOM2_SLOW_FREQUENCY 32768
253#endif
254
255// <y> Core Clock Source
256// <id> core_gclk_selection
257
258// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
259
260// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
261
262// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
263
264// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
265
266// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
267
268// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
269
270// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
271
272// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
273
274// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
275
276// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
277
278// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
279
280// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
281
282// <i> Select the clock source for CORE.
283#ifndef CONF_GCLK_SERCOM3_CORE_SRC
284#define CONF_GCLK_SERCOM3_CORE_SRC GCLK_PCHCTRL_GEN_GCLK2_Val
285#endif
286
287// <y> Slow Clock Source
288// <id> slow_gclk_selection
289
290// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
291
292// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
293
294// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
295
296// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
297
298// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
299
300// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
301
302// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
303
304// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
305
306// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
307
308// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
309
310// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
311
312// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
313
314// <i> Select the slow clock source.
315#ifndef CONF_GCLK_SERCOM3_SLOW_SRC
316#define CONF_GCLK_SERCOM3_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
317#endif
318
319/**
320 * \def CONF_GCLK_SERCOM3_CORE_FREQUENCY
321 * \brief SERCOM3's Core Clock frequency
322 */
323#ifndef CONF_GCLK_SERCOM3_CORE_FREQUENCY
324#define CONF_GCLK_SERCOM3_CORE_FREQUENCY 100000000
325#endif
326
327/**
328 * \def CONF_GCLK_SERCOM3_SLOW_FREQUENCY
329 * \brief SERCOM3's Slow Clock frequency
330 */
331#ifndef CONF_GCLK_SERCOM3_SLOW_FREQUENCY
332#define CONF_GCLK_SERCOM3_SLOW_FREQUENCY 32768
333#endif
334
335// <y> Core Clock Source
336// <id> core_gclk_selection
337
338// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
339
340// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
341
342// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
343
344// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
345
346// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
347
348// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
349
350// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
351
352// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
353
354// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
355
356// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
357
358// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
359
360// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
361
362// <i> Select the clock source for CORE.
363#ifndef CONF_GCLK_SERCOM4_CORE_SRC
364#define CONF_GCLK_SERCOM4_CORE_SRC GCLK_PCHCTRL_GEN_GCLK2_Val
365#endif
366
367// <y> Slow Clock Source
368// <id> slow_gclk_selection
369
370// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
371
372// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
373
374// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
375
376// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
377
378// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
379
380// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
381
382// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
383
384// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
385
386// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
387
388// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
389
390// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
391
392// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
393
394// <i> Select the slow clock source.
395#ifndef CONF_GCLK_SERCOM4_SLOW_SRC
396#define CONF_GCLK_SERCOM4_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
397#endif
398
399/**
400 * \def CONF_GCLK_SERCOM4_CORE_FREQUENCY
401 * \brief SERCOM4's Core Clock frequency
402 */
403#ifndef CONF_GCLK_SERCOM4_CORE_FREQUENCY
404#define CONF_GCLK_SERCOM4_CORE_FREQUENCY 100000000
405#endif
406
407/**
408 * \def CONF_GCLK_SERCOM4_SLOW_FREQUENCY
409 * \brief SERCOM4's Slow Clock frequency
410 */
411#ifndef CONF_GCLK_SERCOM4_SLOW_FREQUENCY
412#define CONF_GCLK_SERCOM4_SLOW_FREQUENCY 32768
413#endif
414
415// <y> Core Clock Source
416// <id> core_gclk_selection
417
418// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
419
420// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
421
422// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
423
424// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
425
426// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
427
428// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
429
430// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
431
432// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
433
434// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
435
436// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
437
438// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
439
440// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
441
442// <i> Select the clock source for CORE.
443#ifndef CONF_GCLK_SERCOM5_CORE_SRC
444#define CONF_GCLK_SERCOM5_CORE_SRC GCLK_PCHCTRL_GEN_GCLK2_Val
445#endif
446
447// <y> Slow Clock Source
448// <id> slow_gclk_selection
449
450// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
451
452// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
453
454// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
455
456// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
457
458// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
459
460// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
461
462// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
463
464// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
465
466// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
467
468// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
469
470// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
471
472// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
473
474// <i> Select the slow clock source.
475#ifndef CONF_GCLK_SERCOM5_SLOW_SRC
476#define CONF_GCLK_SERCOM5_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
477#endif
478
479/**
480 * \def CONF_GCLK_SERCOM5_CORE_FREQUENCY
481 * \brief SERCOM5's Core Clock frequency
482 */
483#ifndef CONF_GCLK_SERCOM5_CORE_FREQUENCY
484#define CONF_GCLK_SERCOM5_CORE_FREQUENCY 100000000
485#endif
486
487/**
488 * \def CONF_GCLK_SERCOM5_SLOW_FREQUENCY
489 * \brief SERCOM5's Slow Clock frequency
490 */
491#ifndef CONF_GCLK_SERCOM5_SLOW_FREQUENCY
492#define CONF_GCLK_SERCOM5_SLOW_FREQUENCY 32768
493#endif
494
495// <y> Core Clock Source
496// <id> core_gclk_selection
497
498// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
499
500// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
501
502// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
503
504// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
505
506// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
507
508// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
509
510// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
511
512// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
513
514// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
515
516// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
517
518// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
519
520// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
521
522// <i> Select the clock source for CORE.
523#ifndef CONF_GCLK_SERCOM6_CORE_SRC
524#define CONF_GCLK_SERCOM6_CORE_SRC GCLK_PCHCTRL_GEN_GCLK2_Val
525#endif
526
527// <y> Slow Clock Source
528// <id> slow_gclk_selection
529
530// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
531
532// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
533
534// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
535
536// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
537
538// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
539
540// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
541
542// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
543
544// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
545
546// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
547
548// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
549
550// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
551
552// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
553
554// <i> Select the slow clock source.
555#ifndef CONF_GCLK_SERCOM6_SLOW_SRC
556#define CONF_GCLK_SERCOM6_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
557#endif
558
559/**
560 * \def CONF_GCLK_SERCOM6_CORE_FREQUENCY
561 * \brief SERCOM6's Core Clock frequency
562 */
563#ifndef CONF_GCLK_SERCOM6_CORE_FREQUENCY
564#define CONF_GCLK_SERCOM6_CORE_FREQUENCY 100000000
565#endif
566
567/**
568 * \def CONF_GCLK_SERCOM6_SLOW_FREQUENCY
569 * \brief SERCOM6's Slow Clock frequency
570 */
571#ifndef CONF_GCLK_SERCOM6_SLOW_FREQUENCY
572#define CONF_GCLK_SERCOM6_SLOW_FREQUENCY 32768
573#endif
574
575// <y> Core Clock Source
576// <id> core_gclk_selection
577
578// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
579
580// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
581
582// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
583
584// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
585
586// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
587
588// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
589
590// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
591
592// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
593
594// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
595
596// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
597
598// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
599
600// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
601
602// <i> Select the clock source for CORE.
Kévin Redon4e39b012019-01-30 15:55:58 +0100[diff] [blame]603#ifndef CONF_GCLK_SERCOM7_CORE_SRC
604#define CONF_GCLK_SERCOM7_CORE_SRC GCLK_PCHCTRL_GEN_GCLK2_Val
Kévin Redon4cd3f7d2019-01-24 17:57:13 +0100[diff] [blame]605#endif
606
607// <y> Slow Clock Source
608// <id> slow_gclk_selection
609
610// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
611
612// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
613
614// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
615
616// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
617
618// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
619
620// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
621
622// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
623
624// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
625
626// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
627
628// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
629
630// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
631
632// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
633
634// <i> Select the slow clock source.
Kévin Redon4e39b012019-01-30 15:55:58 +0100[diff] [blame]635#ifndef CONF_GCLK_SERCOM7_SLOW_SRC
636#define CONF_GCLK_SERCOM7_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
Kévin Redon4cd3f7d2019-01-24 17:57:13 +0100[diff] [blame]637#endif
638
639/**
Kévin Redon4e39b012019-01-30 15:55:58 +0100[diff] [blame]640 * \def CONF_GCLK_SERCOM7_CORE_FREQUENCY
641 * \brief SERCOM7's Core Clock frequency
Kévin Redon4cd3f7d2019-01-24 17:57:13 +0100[diff] [blame]642 */
Kévin Redon4e39b012019-01-30 15:55:58 +0100[diff] [blame]643#ifndef CONF_GCLK_SERCOM7_CORE_FREQUENCY
644#define CONF_GCLK_SERCOM7_CORE_FREQUENCY 100000000
Kévin Redon4cd3f7d2019-01-24 17:57:13 +0100[diff] [blame]645#endif
646
647/**
Kévin Redon4e39b012019-01-30 15:55:58 +0100[diff] [blame]648 * \def CONF_GCLK_SERCOM7_SLOW_FREQUENCY
649 * \brief SERCOM7's Slow Clock frequency
Kévin Redon4cd3f7d2019-01-24 17:57:13 +0100[diff] [blame]650 */
Kévin Redon4e39b012019-01-30 15:55:58 +0100[diff] [blame]651#ifndef CONF_GCLK_SERCOM7_SLOW_FREQUENCY
652#define CONF_GCLK_SERCOM7_SLOW_FREQUENCY 32768
Kévin Redon4cd3f7d2019-01-24 17:57:13 +0100[diff] [blame]653#endif
654
Kévin Redon69b92d92019-01-24 16:39:20 +0100[diff] [blame]655// <y> USB Clock Source
656// <id> usb_gclk_selection
657
658// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
659
660// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
661
662// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
663
664// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
665
666// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
667
668// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
669
670// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
671
672// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
673
674// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
675
676// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
677
678// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
679
680// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
681
682// <i> Select the clock source for USB.
683#ifndef CONF_GCLK_USB_SRC
684#define CONF_GCLK_USB_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
685
686#endif
687
688/**
689 * \def CONF_GCLK_USB_FREQUENCY
690 * \brief USB's Clock frequency
691 */
692#ifndef CONF_GCLK_USB_FREQUENCY
693#define CONF_GCLK_USB_FREQUENCY 48000000
694#endif
695
696// <<< end of configuration section >>>
697
698#endif // PERIPHERAL_CLK_CONFIG_H