Kévin Redon | f041136 | 2019-06-06 17:42:44 +0200 | [diff] [blame] | 1 | /**
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| 2 | * \file
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| 3 | *
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| 4 | * \brief Component description for FREQM
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| 5 | *
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| 6 | * Copyright (c) 2019 Microchip Technology Inc.
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| 7 | *
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| 8 | * \asf_license_start
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| 9 | *
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| 10 | * \page License
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| 11 | *
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| 12 | * SPDX-License-Identifier: Apache-2.0
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| 13 | *
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| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may
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| 15 | * not use this file except in compliance with the License.
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| 16 | * You may obtain a copy of the Licence at
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| 17 | *
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| 18 | * http://www.apache.org/licenses/LICENSE-2.0
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| 19 | *
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| 20 | * Unless required by applicable law or agreed to in writing, software
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| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 23 | * See the License for the specific language governing permissions and
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| 24 | * limitations under the License.
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| 25 | *
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| 26 | * \asf_license_stop
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| 27 | *
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| 28 | */
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| 29 |
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| 30 | #ifndef _SAME54_FREQM_COMPONENT_
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| 31 | #define _SAME54_FREQM_COMPONENT_
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| 32 |
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| 33 | /* ========================================================================== */
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| 34 | /** SOFTWARE API DEFINITION FOR FREQM */
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| 35 | /* ========================================================================== */
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| 36 | /** \addtogroup SAME54_FREQM Frequency Meter */
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| 37 | /*@{*/
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| 38 |
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| 39 | #define FREQM_U2257
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| 40 | #define REV_FREQM 0x110
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| 41 |
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| 42 | /* -------- FREQM_CTRLA : (FREQM Offset: 0x00) (R/W 8) Control A Register -------- */
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| 43 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 44 | typedef union {
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| 45 | struct {
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| 46 | uint8_t SWRST:1; /*!< bit: 0 Software Reset */
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| 47 | uint8_t ENABLE:1; /*!< bit: 1 Enable */
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| 48 | uint8_t :6; /*!< bit: 2.. 7 Reserved */
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| 49 | } bit; /*!< Structure used for bit access */
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| 50 | uint8_t reg; /*!< Type used for register access */
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| 51 | } FREQM_CTRLA_Type;
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| 52 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 53 |
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| 54 | #define FREQM_CTRLA_OFFSET 0x00 /**< \brief (FREQM_CTRLA offset) Control A Register */
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| 55 | #define FREQM_CTRLA_RESETVALUE _U_(0x00) /**< \brief (FREQM_CTRLA reset_value) Control A Register */
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| 56 |
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| 57 | #define FREQM_CTRLA_SWRST_Pos 0 /**< \brief (FREQM_CTRLA) Software Reset */
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| 58 | #define FREQM_CTRLA_SWRST (_U_(0x1) << FREQM_CTRLA_SWRST_Pos)
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| 59 | #define FREQM_CTRLA_ENABLE_Pos 1 /**< \brief (FREQM_CTRLA) Enable */
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| 60 | #define FREQM_CTRLA_ENABLE (_U_(0x1) << FREQM_CTRLA_ENABLE_Pos)
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| 61 | #define FREQM_CTRLA_MASK _U_(0x03) /**< \brief (FREQM_CTRLA) MASK Register */
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| 62 |
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| 63 | /* -------- FREQM_CTRLB : (FREQM Offset: 0x01) ( /W 8) Control B Register -------- */
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| 64 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 65 | typedef union {
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| 66 | struct {
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| 67 | uint8_t START:1; /*!< bit: 0 Start Measurement */
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| 68 | uint8_t :7; /*!< bit: 1.. 7 Reserved */
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| 69 | } bit; /*!< Structure used for bit access */
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| 70 | uint8_t reg; /*!< Type used for register access */
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| 71 | } FREQM_CTRLB_Type;
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| 72 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 73 |
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| 74 | #define FREQM_CTRLB_OFFSET 0x01 /**< \brief (FREQM_CTRLB offset) Control B Register */
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| 75 | #define FREQM_CTRLB_RESETVALUE _U_(0x00) /**< \brief (FREQM_CTRLB reset_value) Control B Register */
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| 76 |
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| 77 | #define FREQM_CTRLB_START_Pos 0 /**< \brief (FREQM_CTRLB) Start Measurement */
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| 78 | #define FREQM_CTRLB_START (_U_(0x1) << FREQM_CTRLB_START_Pos)
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| 79 | #define FREQM_CTRLB_MASK _U_(0x01) /**< \brief (FREQM_CTRLB) MASK Register */
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| 80 |
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| 81 | /* -------- FREQM_CFGA : (FREQM Offset: 0x02) (R/W 16) Config A register -------- */
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| 82 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 83 | typedef union {
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| 84 | struct {
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| 85 | uint16_t REFNUM:8; /*!< bit: 0.. 7 Number of Reference Clock Cycles */
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| 86 | uint16_t :8; /*!< bit: 8..15 Reserved */
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| 87 | } bit; /*!< Structure used for bit access */
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| 88 | uint16_t reg; /*!< Type used for register access */
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| 89 | } FREQM_CFGA_Type;
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| 90 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 91 |
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| 92 | #define FREQM_CFGA_OFFSET 0x02 /**< \brief (FREQM_CFGA offset) Config A register */
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| 93 | #define FREQM_CFGA_RESETVALUE _U_(0x0000) /**< \brief (FREQM_CFGA reset_value) Config A register */
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| 94 |
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| 95 | #define FREQM_CFGA_REFNUM_Pos 0 /**< \brief (FREQM_CFGA) Number of Reference Clock Cycles */
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| 96 | #define FREQM_CFGA_REFNUM_Msk (_U_(0xFF) << FREQM_CFGA_REFNUM_Pos)
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| 97 | #define FREQM_CFGA_REFNUM(value) (FREQM_CFGA_REFNUM_Msk & ((value) << FREQM_CFGA_REFNUM_Pos))
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| 98 | #define FREQM_CFGA_MASK _U_(0x00FF) /**< \brief (FREQM_CFGA) MASK Register */
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| 99 |
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| 100 | /* -------- FREQM_INTENCLR : (FREQM Offset: 0x08) (R/W 8) Interrupt Enable Clear Register -------- */
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| 101 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 102 | typedef union {
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| 103 | struct {
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| 104 | uint8_t DONE:1; /*!< bit: 0 Measurement Done Interrupt Enable */
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| 105 | uint8_t :7; /*!< bit: 1.. 7 Reserved */
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| 106 | } bit; /*!< Structure used for bit access */
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| 107 | uint8_t reg; /*!< Type used for register access */
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| 108 | } FREQM_INTENCLR_Type;
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| 109 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 110 |
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| 111 | #define FREQM_INTENCLR_OFFSET 0x08 /**< \brief (FREQM_INTENCLR offset) Interrupt Enable Clear Register */
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| 112 | #define FREQM_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (FREQM_INTENCLR reset_value) Interrupt Enable Clear Register */
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| 113 |
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| 114 | #define FREQM_INTENCLR_DONE_Pos 0 /**< \brief (FREQM_INTENCLR) Measurement Done Interrupt Enable */
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| 115 | #define FREQM_INTENCLR_DONE (_U_(0x1) << FREQM_INTENCLR_DONE_Pos)
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| 116 | #define FREQM_INTENCLR_MASK _U_(0x01) /**< \brief (FREQM_INTENCLR) MASK Register */
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| 117 |
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| 118 | /* -------- FREQM_INTENSET : (FREQM Offset: 0x09) (R/W 8) Interrupt Enable Set Register -------- */
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| 119 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 120 | typedef union {
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| 121 | struct {
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| 122 | uint8_t DONE:1; /*!< bit: 0 Measurement Done Interrupt Enable */
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| 123 | uint8_t :7; /*!< bit: 1.. 7 Reserved */
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| 124 | } bit; /*!< Structure used for bit access */
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| 125 | uint8_t reg; /*!< Type used for register access */
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| 126 | } FREQM_INTENSET_Type;
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| 127 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 128 |
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| 129 | #define FREQM_INTENSET_OFFSET 0x09 /**< \brief (FREQM_INTENSET offset) Interrupt Enable Set Register */
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| 130 | #define FREQM_INTENSET_RESETVALUE _U_(0x00) /**< \brief (FREQM_INTENSET reset_value) Interrupt Enable Set Register */
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| 131 |
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| 132 | #define FREQM_INTENSET_DONE_Pos 0 /**< \brief (FREQM_INTENSET) Measurement Done Interrupt Enable */
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| 133 | #define FREQM_INTENSET_DONE (_U_(0x1) << FREQM_INTENSET_DONE_Pos)
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| 134 | #define FREQM_INTENSET_MASK _U_(0x01) /**< \brief (FREQM_INTENSET) MASK Register */
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| 135 |
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| 136 | /* -------- FREQM_INTFLAG : (FREQM Offset: 0x0A) (R/W 8) Interrupt Flag Register -------- */
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| 137 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 138 | typedef union { // __I to avoid read-modify-write on write-to-clear register
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| 139 | struct {
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| 140 | __I uint8_t DONE:1; /*!< bit: 0 Measurement Done */
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| 141 | __I uint8_t :7; /*!< bit: 1.. 7 Reserved */
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| 142 | } bit; /*!< Structure used for bit access */
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| 143 | uint8_t reg; /*!< Type used for register access */
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| 144 | } FREQM_INTFLAG_Type;
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| 145 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 146 |
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| 147 | #define FREQM_INTFLAG_OFFSET 0x0A /**< \brief (FREQM_INTFLAG offset) Interrupt Flag Register */
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| 148 | #define FREQM_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (FREQM_INTFLAG reset_value) Interrupt Flag Register */
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| 149 |
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| 150 | #define FREQM_INTFLAG_DONE_Pos 0 /**< \brief (FREQM_INTFLAG) Measurement Done */
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| 151 | #define FREQM_INTFLAG_DONE (_U_(0x1) << FREQM_INTFLAG_DONE_Pos)
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| 152 | #define FREQM_INTFLAG_MASK _U_(0x01) /**< \brief (FREQM_INTFLAG) MASK Register */
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| 153 |
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| 154 | /* -------- FREQM_STATUS : (FREQM Offset: 0x0B) (R/W 8) Status Register -------- */
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| 155 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 156 | typedef union {
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| 157 | struct {
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| 158 | uint8_t BUSY:1; /*!< bit: 0 FREQM Status */
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| 159 | uint8_t OVF:1; /*!< bit: 1 Sticky Count Value Overflow */
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| 160 | uint8_t :6; /*!< bit: 2.. 7 Reserved */
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| 161 | } bit; /*!< Structure used for bit access */
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| 162 | uint8_t reg; /*!< Type used for register access */
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| 163 | } FREQM_STATUS_Type;
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| 164 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 165 |
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| 166 | #define FREQM_STATUS_OFFSET 0x0B /**< \brief (FREQM_STATUS offset) Status Register */
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| 167 | #define FREQM_STATUS_RESETVALUE _U_(0x00) /**< \brief (FREQM_STATUS reset_value) Status Register */
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| 168 |
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| 169 | #define FREQM_STATUS_BUSY_Pos 0 /**< \brief (FREQM_STATUS) FREQM Status */
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| 170 | #define FREQM_STATUS_BUSY (_U_(0x1) << FREQM_STATUS_BUSY_Pos)
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| 171 | #define FREQM_STATUS_OVF_Pos 1 /**< \brief (FREQM_STATUS) Sticky Count Value Overflow */
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| 172 | #define FREQM_STATUS_OVF (_U_(0x1) << FREQM_STATUS_OVF_Pos)
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| 173 | #define FREQM_STATUS_MASK _U_(0x03) /**< \brief (FREQM_STATUS) MASK Register */
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| 174 |
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| 175 | /* -------- FREQM_SYNCBUSY : (FREQM Offset: 0x0C) (R/ 32) Synchronization Busy Register -------- */
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| 176 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 177 | typedef union {
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| 178 | struct {
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| 179 | uint32_t SWRST:1; /*!< bit: 0 Software Reset */
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| 180 | uint32_t ENABLE:1; /*!< bit: 1 Enable */
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| 181 | uint32_t :30; /*!< bit: 2..31 Reserved */
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| 182 | } bit; /*!< Structure used for bit access */
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| 183 | uint32_t reg; /*!< Type used for register access */
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| 184 | } FREQM_SYNCBUSY_Type;
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| 185 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 186 |
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| 187 | #define FREQM_SYNCBUSY_OFFSET 0x0C /**< \brief (FREQM_SYNCBUSY offset) Synchronization Busy Register */
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| 188 | #define FREQM_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (FREQM_SYNCBUSY reset_value) Synchronization Busy Register */
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| 189 |
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| 190 | #define FREQM_SYNCBUSY_SWRST_Pos 0 /**< \brief (FREQM_SYNCBUSY) Software Reset */
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| 191 | #define FREQM_SYNCBUSY_SWRST (_U_(0x1) << FREQM_SYNCBUSY_SWRST_Pos)
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| 192 | #define FREQM_SYNCBUSY_ENABLE_Pos 1 /**< \brief (FREQM_SYNCBUSY) Enable */
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| 193 | #define FREQM_SYNCBUSY_ENABLE (_U_(0x1) << FREQM_SYNCBUSY_ENABLE_Pos)
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| 194 | #define FREQM_SYNCBUSY_MASK _U_(0x00000003) /**< \brief (FREQM_SYNCBUSY) MASK Register */
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| 195 |
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| 196 | /* -------- FREQM_VALUE : (FREQM Offset: 0x10) (R/ 32) Count Value Register -------- */
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| 197 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 198 | typedef union {
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| 199 | struct {
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| 200 | uint32_t VALUE:24; /*!< bit: 0..23 Measurement Value */
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| 201 | uint32_t :8; /*!< bit: 24..31 Reserved */
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| 202 | } bit; /*!< Structure used for bit access */
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| 203 | uint32_t reg; /*!< Type used for register access */
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| 204 | } FREQM_VALUE_Type;
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| 205 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 206 |
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| 207 | #define FREQM_VALUE_OFFSET 0x10 /**< \brief (FREQM_VALUE offset) Count Value Register */
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| 208 | #define FREQM_VALUE_RESETVALUE _U_(0x00000000) /**< \brief (FREQM_VALUE reset_value) Count Value Register */
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| 209 |
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| 210 | #define FREQM_VALUE_VALUE_Pos 0 /**< \brief (FREQM_VALUE) Measurement Value */
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| 211 | #define FREQM_VALUE_VALUE_Msk (_U_(0xFFFFFF) << FREQM_VALUE_VALUE_Pos)
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| 212 | #define FREQM_VALUE_VALUE(value) (FREQM_VALUE_VALUE_Msk & ((value) << FREQM_VALUE_VALUE_Pos))
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| 213 | #define FREQM_VALUE_MASK _U_(0x00FFFFFF) /**< \brief (FREQM_VALUE) MASK Register */
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| 214 |
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| 215 | /** \brief FREQM hardware registers */
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| 216 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 217 | typedef struct {
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| 218 | __IO FREQM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A Register */
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| 219 | __O FREQM_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B Register */
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| 220 | __IO FREQM_CFGA_Type CFGA; /**< \brief Offset: 0x02 (R/W 16) Config A register */
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| 221 | RoReg8 Reserved1[0x4];
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| 222 | __IO FREQM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear Register */
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| 223 | __IO FREQM_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set Register */
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| 224 | __IO FREQM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Register */
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| 225 | __IO FREQM_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status Register */
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| 226 | __I FREQM_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x0C (R/ 32) Synchronization Busy Register */
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| 227 | __I FREQM_VALUE_Type VALUE; /**< \brief Offset: 0x10 (R/ 32) Count Value Register */
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| 228 | } Freqm;
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| 229 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 230 |
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| 231 | /*@}*/
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| 232 |
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| 233 | #endif /* _SAME54_FREQM_COMPONENT_ */
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