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gerrit.osmocom.org / osmo-ccid-firmware / f041136fb21445d77dfc8093fd2c4d15f216ff43 / . / sysmoOCTSIM / include / component / freqm.h
blob: 34e62f927c8ecc1ef2ceeb194461a9f0fa72cecd [file] [log] [blame]
Kévin Redonf0411362019-06-06 17:42:44 +0200[diff] [blame^]1/**
2 * \file
3 *
4 * \brief Component description for FREQM
5 *
6 * Copyright (c) 2019 Microchip Technology Inc.
7 *
8 * \asf_license_start
9 *
10 * \page License
11 *
12 * SPDX-License-Identifier: Apache-2.0
13 *
14 * Licensed under the Apache License, Version 2.0 (the "License"); you may
15 * not use this file except in compliance with the License.
16 * You may obtain a copy of the Licence at
17 *
18 * http://www.apache.org/licenses/LICENSE-2.0
19 *
20 * Unless required by applicable law or agreed to in writing, software
21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 * See the License for the specific language governing permissions and
24 * limitations under the License.
25 *
26 * \asf_license_stop
27 *
28 */
29
30#ifndef _SAME54_FREQM_COMPONENT_
31#define _SAME54_FREQM_COMPONENT_
32
33/* ========================================================================== */
34/** SOFTWARE API DEFINITION FOR FREQM */
35/* ========================================================================== */
36/** \addtogroup SAME54_FREQM Frequency Meter */
37/*@{*/
38
39#define FREQM_U2257
40#define REV_FREQM 0x110
41
42/* -------- FREQM_CTRLA : (FREQM Offset: 0x00) (R/W 8) Control A Register -------- */
43#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
44typedef union {
45 struct {
46 uint8_t SWRST:1; /*!< bit: 0 Software Reset */
47 uint8_t ENABLE:1; /*!< bit: 1 Enable */
48 uint8_t :6; /*!< bit: 2.. 7 Reserved */
49 } bit; /*!< Structure used for bit access */
50 uint8_t reg; /*!< Type used for register access */
51} FREQM_CTRLA_Type;
52#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
53
54#define FREQM_CTRLA_OFFSET 0x00 /**< \brief (FREQM_CTRLA offset) Control A Register */
55#define FREQM_CTRLA_RESETVALUE _U_(0x00) /**< \brief (FREQM_CTRLA reset_value) Control A Register */
56
57#define FREQM_CTRLA_SWRST_Pos 0 /**< \brief (FREQM_CTRLA) Software Reset */
58#define FREQM_CTRLA_SWRST (_U_(0x1) << FREQM_CTRLA_SWRST_Pos)
59#define FREQM_CTRLA_ENABLE_Pos 1 /**< \brief (FREQM_CTRLA) Enable */
60#define FREQM_CTRLA_ENABLE (_U_(0x1) << FREQM_CTRLA_ENABLE_Pos)
61#define FREQM_CTRLA_MASK _U_(0x03) /**< \brief (FREQM_CTRLA) MASK Register */
62
63/* -------- FREQM_CTRLB : (FREQM Offset: 0x01) ( /W 8) Control B Register -------- */
64#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
65typedef union {
66 struct {
67 uint8_t START:1; /*!< bit: 0 Start Measurement */
68 uint8_t :7; /*!< bit: 1.. 7 Reserved */
69 } bit; /*!< Structure used for bit access */
70 uint8_t reg; /*!< Type used for register access */
71} FREQM_CTRLB_Type;
72#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
73
74#define FREQM_CTRLB_OFFSET 0x01 /**< \brief (FREQM_CTRLB offset) Control B Register */
75#define FREQM_CTRLB_RESETVALUE _U_(0x00) /**< \brief (FREQM_CTRLB reset_value) Control B Register */
76
77#define FREQM_CTRLB_START_Pos 0 /**< \brief (FREQM_CTRLB) Start Measurement */
78#define FREQM_CTRLB_START (_U_(0x1) << FREQM_CTRLB_START_Pos)
79#define FREQM_CTRLB_MASK _U_(0x01) /**< \brief (FREQM_CTRLB) MASK Register */
80
81/* -------- FREQM_CFGA : (FREQM Offset: 0x02) (R/W 16) Config A register -------- */
82#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
83typedef union {
84 struct {
85 uint16_t REFNUM:8; /*!< bit: 0.. 7 Number of Reference Clock Cycles */
86 uint16_t :8; /*!< bit: 8..15 Reserved */
87 } bit; /*!< Structure used for bit access */
88 uint16_t reg; /*!< Type used for register access */
89} FREQM_CFGA_Type;
90#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
91
92#define FREQM_CFGA_OFFSET 0x02 /**< \brief (FREQM_CFGA offset) Config A register */
93#define FREQM_CFGA_RESETVALUE _U_(0x0000) /**< \brief (FREQM_CFGA reset_value) Config A register */
94
95#define FREQM_CFGA_REFNUM_Pos 0 /**< \brief (FREQM_CFGA) Number of Reference Clock Cycles */
96#define FREQM_CFGA_REFNUM_Msk (_U_(0xFF) << FREQM_CFGA_REFNUM_Pos)
97#define FREQM_CFGA_REFNUM(value) (FREQM_CFGA_REFNUM_Msk & ((value) << FREQM_CFGA_REFNUM_Pos))
98#define FREQM_CFGA_MASK _U_(0x00FF) /**< \brief (FREQM_CFGA) MASK Register */
99
100/* -------- FREQM_INTENCLR : (FREQM Offset: 0x08) (R/W 8) Interrupt Enable Clear Register -------- */
101#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
102typedef union {
103 struct {
104 uint8_t DONE:1; /*!< bit: 0 Measurement Done Interrupt Enable */
105 uint8_t :7; /*!< bit: 1.. 7 Reserved */
106 } bit; /*!< Structure used for bit access */
107 uint8_t reg; /*!< Type used for register access */
108} FREQM_INTENCLR_Type;
109#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
110
111#define FREQM_INTENCLR_OFFSET 0x08 /**< \brief (FREQM_INTENCLR offset) Interrupt Enable Clear Register */
112#define FREQM_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (FREQM_INTENCLR reset_value) Interrupt Enable Clear Register */
113
114#define FREQM_INTENCLR_DONE_Pos 0 /**< \brief (FREQM_INTENCLR) Measurement Done Interrupt Enable */
115#define FREQM_INTENCLR_DONE (_U_(0x1) << FREQM_INTENCLR_DONE_Pos)
116#define FREQM_INTENCLR_MASK _U_(0x01) /**< \brief (FREQM_INTENCLR) MASK Register */
117
118/* -------- FREQM_INTENSET : (FREQM Offset: 0x09) (R/W 8) Interrupt Enable Set Register -------- */
119#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
120typedef union {
121 struct {
122 uint8_t DONE:1; /*!< bit: 0 Measurement Done Interrupt Enable */
123 uint8_t :7; /*!< bit: 1.. 7 Reserved */
124 } bit; /*!< Structure used for bit access */
125 uint8_t reg; /*!< Type used for register access */
126} FREQM_INTENSET_Type;
127#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
128
129#define FREQM_INTENSET_OFFSET 0x09 /**< \brief (FREQM_INTENSET offset) Interrupt Enable Set Register */
130#define FREQM_INTENSET_RESETVALUE _U_(0x00) /**< \brief (FREQM_INTENSET reset_value) Interrupt Enable Set Register */
131
132#define FREQM_INTENSET_DONE_Pos 0 /**< \brief (FREQM_INTENSET) Measurement Done Interrupt Enable */
133#define FREQM_INTENSET_DONE (_U_(0x1) << FREQM_INTENSET_DONE_Pos)
134#define FREQM_INTENSET_MASK _U_(0x01) /**< \brief (FREQM_INTENSET) MASK Register */
135
136/* -------- FREQM_INTFLAG : (FREQM Offset: 0x0A) (R/W 8) Interrupt Flag Register -------- */
137#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
138typedef union { // __I to avoid read-modify-write on write-to-clear register
139 struct {
140 __I uint8_t DONE:1; /*!< bit: 0 Measurement Done */
141 __I uint8_t :7; /*!< bit: 1.. 7 Reserved */
142 } bit; /*!< Structure used for bit access */
143 uint8_t reg; /*!< Type used for register access */
144} FREQM_INTFLAG_Type;
145#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
146
147#define FREQM_INTFLAG_OFFSET 0x0A /**< \brief (FREQM_INTFLAG offset) Interrupt Flag Register */
148#define FREQM_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (FREQM_INTFLAG reset_value) Interrupt Flag Register */
149
150#define FREQM_INTFLAG_DONE_Pos 0 /**< \brief (FREQM_INTFLAG) Measurement Done */
151#define FREQM_INTFLAG_DONE (_U_(0x1) << FREQM_INTFLAG_DONE_Pos)
152#define FREQM_INTFLAG_MASK _U_(0x01) /**< \brief (FREQM_INTFLAG) MASK Register */
153
154/* -------- FREQM_STATUS : (FREQM Offset: 0x0B) (R/W 8) Status Register -------- */
155#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
156typedef union {
157 struct {
158 uint8_t BUSY:1; /*!< bit: 0 FREQM Status */
159 uint8_t OVF:1; /*!< bit: 1 Sticky Count Value Overflow */
160 uint8_t :6; /*!< bit: 2.. 7 Reserved */
161 } bit; /*!< Structure used for bit access */
162 uint8_t reg; /*!< Type used for register access */
163} FREQM_STATUS_Type;
164#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
165
166#define FREQM_STATUS_OFFSET 0x0B /**< \brief (FREQM_STATUS offset) Status Register */
167#define FREQM_STATUS_RESETVALUE _U_(0x00) /**< \brief (FREQM_STATUS reset_value) Status Register */
168
169#define FREQM_STATUS_BUSY_Pos 0 /**< \brief (FREQM_STATUS) FREQM Status */
170#define FREQM_STATUS_BUSY (_U_(0x1) << FREQM_STATUS_BUSY_Pos)
171#define FREQM_STATUS_OVF_Pos 1 /**< \brief (FREQM_STATUS) Sticky Count Value Overflow */
172#define FREQM_STATUS_OVF (_U_(0x1) << FREQM_STATUS_OVF_Pos)
173#define FREQM_STATUS_MASK _U_(0x03) /**< \brief (FREQM_STATUS) MASK Register */
174
175/* -------- FREQM_SYNCBUSY : (FREQM Offset: 0x0C) (R/ 32) Synchronization Busy Register -------- */
176#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
177typedef union {
178 struct {
179 uint32_t SWRST:1; /*!< bit: 0 Software Reset */
180 uint32_t ENABLE:1; /*!< bit: 1 Enable */
181 uint32_t :30; /*!< bit: 2..31 Reserved */
182 } bit; /*!< Structure used for bit access */
183 uint32_t reg; /*!< Type used for register access */
184} FREQM_SYNCBUSY_Type;
185#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
186
187#define FREQM_SYNCBUSY_OFFSET 0x0C /**< \brief (FREQM_SYNCBUSY offset) Synchronization Busy Register */
188#define FREQM_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (FREQM_SYNCBUSY reset_value) Synchronization Busy Register */
189
190#define FREQM_SYNCBUSY_SWRST_Pos 0 /**< \brief (FREQM_SYNCBUSY) Software Reset */
191#define FREQM_SYNCBUSY_SWRST (_U_(0x1) << FREQM_SYNCBUSY_SWRST_Pos)
192#define FREQM_SYNCBUSY_ENABLE_Pos 1 /**< \brief (FREQM_SYNCBUSY) Enable */
193#define FREQM_SYNCBUSY_ENABLE (_U_(0x1) << FREQM_SYNCBUSY_ENABLE_Pos)
194#define FREQM_SYNCBUSY_MASK _U_(0x00000003) /**< \brief (FREQM_SYNCBUSY) MASK Register */
195
196/* -------- FREQM_VALUE : (FREQM Offset: 0x10) (R/ 32) Count Value Register -------- */
197#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
198typedef union {
199 struct {
200 uint32_t VALUE:24; /*!< bit: 0..23 Measurement Value */
201 uint32_t :8; /*!< bit: 24..31 Reserved */
202 } bit; /*!< Structure used for bit access */
203 uint32_t reg; /*!< Type used for register access */
204} FREQM_VALUE_Type;
205#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
206
207#define FREQM_VALUE_OFFSET 0x10 /**< \brief (FREQM_VALUE offset) Count Value Register */
208#define FREQM_VALUE_RESETVALUE _U_(0x00000000) /**< \brief (FREQM_VALUE reset_value) Count Value Register */
209
210#define FREQM_VALUE_VALUE_Pos 0 /**< \brief (FREQM_VALUE) Measurement Value */
211#define FREQM_VALUE_VALUE_Msk (_U_(0xFFFFFF) << FREQM_VALUE_VALUE_Pos)
212#define FREQM_VALUE_VALUE(value) (FREQM_VALUE_VALUE_Msk & ((value) << FREQM_VALUE_VALUE_Pos))
213#define FREQM_VALUE_MASK _U_(0x00FFFFFF) /**< \brief (FREQM_VALUE) MASK Register */
214
215/** \brief FREQM hardware registers */
216#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
217typedef struct {
218 __IO FREQM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A Register */
219 __O FREQM_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B Register */
220 __IO FREQM_CFGA_Type CFGA; /**< \brief Offset: 0x02 (R/W 16) Config A register */
221 RoReg8 Reserved1[0x4];
222 __IO FREQM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear Register */
223 __IO FREQM_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set Register */
224 __IO FREQM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Register */
225 __IO FREQM_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status Register */
226 __I FREQM_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x0C (R/ 32) Synchronization Busy Register */
227 __I FREQM_VALUE_Type VALUE; /**< \brief Offset: 0x10 (R/ 32) Count Value Register */
228} Freqm;
229#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
230
231/*@}*/
232
233#endif /* _SAME54_FREQM_COMPONENT_ */