| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief Instance description for ADC0 |
| 5 | * |
| 6 | * Copyright (c) 2018 Microchip Technology Inc. |
| 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * SPDX-License-Identifier: Apache-2.0 |
| 13 | * |
| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may |
| 15 | * not use this file except in compliance with the License. |
| 16 | * You may obtain a copy of the Licence at |
| 17 | * |
| 18 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 19 | * |
| 20 | * Unless required by applicable law or agreed to in writing, software |
| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 23 | * See the License for the specific language governing permissions and |
| 24 | * limitations under the License. |
| 25 | * |
| 26 | * \asf_license_stop |
| 27 | * |
| 28 | */ |
| 29 | |
| 30 | #ifndef _SAME54_ADC0_INSTANCE_ |
| 31 | #define _SAME54_ADC0_INSTANCE_ |
| 32 | |
| 33 | /* ========== Register definition for ADC0 peripheral ========== */ |
| 34 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 35 | #define REG_ADC0_CTRLA (0x43001C00) /**< \brief (ADC0) Control A */ |
| 36 | #define REG_ADC0_EVCTRL (0x43001C02) /**< \brief (ADC0) Event Control */ |
| 37 | #define REG_ADC0_DBGCTRL (0x43001C03) /**< \brief (ADC0) Debug Control */ |
| 38 | #define REG_ADC0_INPUTCTRL (0x43001C04) /**< \brief (ADC0) Input Control */ |
| 39 | #define REG_ADC0_CTRLB (0x43001C06) /**< \brief (ADC0) Control B */ |
| 40 | #define REG_ADC0_REFCTRL (0x43001C08) /**< \brief (ADC0) Reference Control */ |
| 41 | #define REG_ADC0_AVGCTRL (0x43001C0A) /**< \brief (ADC0) Average Control */ |
| 42 | #define REG_ADC0_SAMPCTRL (0x43001C0B) /**< \brief (ADC0) Sample Time Control */ |
| 43 | #define REG_ADC0_WINLT (0x43001C0C) /**< \brief (ADC0) Window Monitor Lower Threshold */ |
| 44 | #define REG_ADC0_WINUT (0x43001C0E) /**< \brief (ADC0) Window Monitor Upper Threshold */ |
| 45 | #define REG_ADC0_GAINCORR (0x43001C10) /**< \brief (ADC0) Gain Correction */ |
| 46 | #define REG_ADC0_OFFSETCORR (0x43001C12) /**< \brief (ADC0) Offset Correction */ |
| 47 | #define REG_ADC0_SWTRIG (0x43001C14) /**< \brief (ADC0) Software Trigger */ |
| 48 | #define REG_ADC0_INTENCLR (0x43001C2C) /**< \brief (ADC0) Interrupt Enable Clear */ |
| 49 | #define REG_ADC0_INTENSET (0x43001C2D) /**< \brief (ADC0) Interrupt Enable Set */ |
| 50 | #define REG_ADC0_INTFLAG (0x43001C2E) /**< \brief (ADC0) Interrupt Flag Status and Clear */ |
| 51 | #define REG_ADC0_STATUS (0x43001C2F) /**< \brief (ADC0) Status */ |
| 52 | #define REG_ADC0_SYNCBUSY (0x43001C30) /**< \brief (ADC0) Synchronization Busy */ |
| 53 | #define REG_ADC0_DSEQDATA (0x43001C34) /**< \brief (ADC0) DMA Sequencial Data */ |
| 54 | #define REG_ADC0_DSEQCTRL (0x43001C38) /**< \brief (ADC0) DMA Sequential Control */ |
| 55 | #define REG_ADC0_DSEQSTAT (0x43001C3C) /**< \brief (ADC0) DMA Sequencial Status */ |
| 56 | #define REG_ADC0_RESULT (0x43001C40) /**< \brief (ADC0) Result Conversion Value */ |
| 57 | #define REG_ADC0_RESS (0x43001C44) /**< \brief (ADC0) Last Sample Result */ |
| 58 | #define REG_ADC0_CALIB (0x43001C48) /**< \brief (ADC0) Calibration */ |
| 59 | #else |
| 60 | #define REG_ADC0_CTRLA (*(RwReg16*)0x43001C00UL) /**< \brief (ADC0) Control A */ |
| 61 | #define REG_ADC0_EVCTRL (*(RwReg8 *)0x43001C02UL) /**< \brief (ADC0) Event Control */ |
| 62 | #define REG_ADC0_DBGCTRL (*(RwReg8 *)0x43001C03UL) /**< \brief (ADC0) Debug Control */ |
| 63 | #define REG_ADC0_INPUTCTRL (*(RwReg16*)0x43001C04UL) /**< \brief (ADC0) Input Control */ |
| 64 | #define REG_ADC0_CTRLB (*(RwReg16*)0x43001C06UL) /**< \brief (ADC0) Control B */ |
| 65 | #define REG_ADC0_REFCTRL (*(RwReg8 *)0x43001C08UL) /**< \brief (ADC0) Reference Control */ |
| 66 | #define REG_ADC0_AVGCTRL (*(RwReg8 *)0x43001C0AUL) /**< \brief (ADC0) Average Control */ |
| 67 | #define REG_ADC0_SAMPCTRL (*(RwReg8 *)0x43001C0BUL) /**< \brief (ADC0) Sample Time Control */ |
| 68 | #define REG_ADC0_WINLT (*(RwReg16*)0x43001C0CUL) /**< \brief (ADC0) Window Monitor Lower Threshold */ |
| 69 | #define REG_ADC0_WINUT (*(RwReg16*)0x43001C0EUL) /**< \brief (ADC0) Window Monitor Upper Threshold */ |
| 70 | #define REG_ADC0_GAINCORR (*(RwReg16*)0x43001C10UL) /**< \brief (ADC0) Gain Correction */ |
| 71 | #define REG_ADC0_OFFSETCORR (*(RwReg16*)0x43001C12UL) /**< \brief (ADC0) Offset Correction */ |
| 72 | #define REG_ADC0_SWTRIG (*(RwReg8 *)0x43001C14UL) /**< \brief (ADC0) Software Trigger */ |
| 73 | #define REG_ADC0_INTENCLR (*(RwReg8 *)0x43001C2CUL) /**< \brief (ADC0) Interrupt Enable Clear */ |
| 74 | #define REG_ADC0_INTENSET (*(RwReg8 *)0x43001C2DUL) /**< \brief (ADC0) Interrupt Enable Set */ |
| 75 | #define REG_ADC0_INTFLAG (*(RwReg8 *)0x43001C2EUL) /**< \brief (ADC0) Interrupt Flag Status and Clear */ |
| 76 | #define REG_ADC0_STATUS (*(RoReg8 *)0x43001C2FUL) /**< \brief (ADC0) Status */ |
| 77 | #define REG_ADC0_SYNCBUSY (*(RoReg *)0x43001C30UL) /**< \brief (ADC0) Synchronization Busy */ |
| 78 | #define REG_ADC0_DSEQDATA (*(WoReg *)0x43001C34UL) /**< \brief (ADC0) DMA Sequencial Data */ |
| 79 | #define REG_ADC0_DSEQCTRL (*(RwReg *)0x43001C38UL) /**< \brief (ADC0) DMA Sequential Control */ |
| 80 | #define REG_ADC0_DSEQSTAT (*(RoReg *)0x43001C3CUL) /**< \brief (ADC0) DMA Sequencial Status */ |
| 81 | #define REG_ADC0_RESULT (*(RoReg16*)0x43001C40UL) /**< \brief (ADC0) Result Conversion Value */ |
| 82 | #define REG_ADC0_RESS (*(RoReg16*)0x43001C44UL) /**< \brief (ADC0) Last Sample Result */ |
| 83 | #define REG_ADC0_CALIB (*(RwReg16*)0x43001C48UL) /**< \brief (ADC0) Calibration */ |
| 84 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 85 | |
| 86 | /* ========== Instance parameters for ADC0 peripheral ========== */ |
| 87 | #define ADC0_BANDGAP 27 // MUXPOS value to select BANDGAP |
| 88 | #define ADC0_CTAT 29 // MUXPOS value to select CTAT |
| 89 | #define ADC0_DMAC_ID_RESRDY 68 // index of DMA RESRDY trigger |
| 90 | #define ADC0_DMAC_ID_SEQ 69 // Index of DMA SEQ trigger |
| 91 | #define ADC0_EXTCHANNEL_MSB 15 // Number of external channels |
| 92 | #define ADC0_GCLK_ID 40 // index of Generic Clock |
| 93 | #define ADC0_MASTER_SLAVE_MODE 1 // ADC Master/Slave Mode |
| 94 | #define ADC0_OPAMP2 0 // MUXPOS value to select OPAMP2 |
| 95 | #define ADC0_OPAMP01 0 // MUXPOS value to select OPAMP01 |
| 96 | #define ADC0_PTAT 28 // MUXPOS value to select PTAT |
| 97 | #define ADC0_TOUCH_IMPLEMENTED 1 // TOUCH implemented or not |
| 98 | |
| 99 | #endif /* _SAME54_ADC0_INSTANCE_ */ |