Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 1 | /* ----------------------------------------------------------------------------
|
| 2 | * ATMEL Microcontroller Software Support
|
| 3 | * ----------------------------------------------------------------------------
|
| 4 | * Copyright (c) 2009, Atmel Corporation
|
| 5 | *
|
| 6 | * All rights reserved.
|
| 7 | *
|
| 8 | * Redistribution and use in source and binary forms, with or without
|
| 9 | * modification, are permitted provided that the following conditions are met:
|
| 10 | *
|
| 11 | * - Redistributions of source code must retain the above copyright notice,
|
| 12 | * this list of conditions and the disclaimer below.
|
| 13 | *
|
| 14 | * Atmel's name may not be used to endorse or promote products derived from
|
| 15 | * this software without specific prior written permission.
|
| 16 | *
|
| 17 | * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
|
| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
| 19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
| 20 | * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
|
| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
| 22 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
| 23 | * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
| 24 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
| 25 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
| 26 | * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
| 27 | * ----------------------------------------------------------------------------
|
| 28 | */
|
| 29 |
|
| 30 | /**
|
| 31 | * \file
|
| 32 | *
|
| 33 | * Provides the low-level initialization function that called on chip startup.
|
| 34 | */
|
| 35 |
|
| 36 | /*----------------------------------------------------------------------------
|
| 37 | * Headers
|
| 38 | *----------------------------------------------------------------------------*/
|
| 39 |
|
| 40 | #include "board.h"
|
Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 41 |
|
| 42 | /*----------------------------------------------------------------------------
|
| 43 | * Local definitions
|
| 44 | *----------------------------------------------------------------------------*/
|
| 45 |
|
Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 46 | #define BOARD_OSCOUNT (CKGR_MOR_MOSCXTST(0x8))
|
Christina Quast | 530f208 | 2014-12-05 13:03:59 +0100 | [diff] [blame] | 47 | #define BOARD_MCKR (PMC_MCKR_PRES_CLK | PMC_MCKR_CSS_PLLA_CLK)
|
Harald Welte | fb3f308 | 2017-01-12 18:16:23 +0100 | [diff] [blame] | 48 |
|
| 49 | #if (BOARD_MCK == 48000000)
|
| 50 | #if (BOARD_MAINOSC == 18432000)
|
| 51 | /* Clock settings at 48MHz for 18 MHz crystal */
|
| 52 | #define BOARD_PLLAR (CKGR_PLLAR_STUCKTO1 \
|
| 53 | | CKGR_PLLAR_MULA(13-1) \
|
| 54 | | CKGR_PLLAR_PLLACOUNT(0x1) \
|
| 55 | | CKGR_PLLAR_DIVA(5))
|
| 56 | #elif (BOARD_MAINOSC == 12000000)
|
Harald Welte | 7861132 | 2017-01-12 11:07:04 +0100 | [diff] [blame] | 57 | /* QMod has 12 MHz clock, so multply by 8 (96 MHz) and divide by 2 */
|
Harald Welte | a02b641 | 2016-08-21 18:32:12 +0200 | [diff] [blame] | 58 | #define BOARD_PLLAR (CKGR_PLLAR_STUCKTO1 \
|
Harald Welte | 7861132 | 2017-01-12 11:07:04 +0100 | [diff] [blame] | 59 | | CKGR_PLLAR_MULA(8-1) \
|
Harald Welte | a02b641 | 2016-08-21 18:32:12 +0200 | [diff] [blame] | 60 | | CKGR_PLLAR_PLLACOUNT(0x1) \
|
Harald Welte | 7861132 | 2017-01-12 11:07:04 +0100 | [diff] [blame] | 61 | | CKGR_PLLAR_DIVA(2))
|
Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 62 | #else
|
Harald Welte | fb3f308 | 2017-01-12 18:16:23 +0100 | [diff] [blame] | 63 | #error "Please define PLLA config for your MAINOSC frequency"
|
| 64 | #endif /* MAINOSC */
|
| 65 | #elif (BOARD_MCK == 64000000)
|
| 66 | #if (BOARD_MAINOSC == 18432000)
|
| 67 | /* Clock settings at 64MHz for 18 MHz crystal: 64.512 MHz */
|
| 68 | #define BOARD_PLLAR (CKGR_PLLAR_STUCKTO1 \
|
| 69 | | CKGR_PLLAR_MULA(7-1) \
|
| 70 | | CKGR_PLLAR_PLLACOUNT(0x1) \
|
| 71 | | CKGR_PLLAR_DIVA(2))
|
| 72 | #elif (BOARD_MAINOSC == 12000000)
|
| 73 | /* QMod has 12 MHz clock, so multply by 10 / div by 2: 60 MHz */
|
| 74 | #define BOARD_PLLAR (CKGR_PLLAR_STUCKTO1 \
|
| 75 | | CKGR_PLLAR_MULA(10-1) \
|
| 76 | | CKGR_PLLAR_PLLACOUNT(0x1) \
|
| 77 | | CKGR_PLLAR_DIVA(2))
|
| 78 | #error "Please define PLLA config for your MAINOSC frequency"
|
| 79 | #endif /* MAINOSC */
|
| 80 | #else
|
| 81 | #error "No PLL settings for current BOARD_MCK."
|
Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 82 | #endif
|
| 83 |
|
| 84 | /* Define clock timeout */
|
| 85 | #define CLOCK_TIMEOUT 0xFFFFFFFF
|
| 86 |
|
| 87 | /*----------------------------------------------------------------------------
|
| 88 | * Exported functions
|
| 89 | *----------------------------------------------------------------------------*/
|
| 90 |
|
| 91 | /**
|
| 92 | * \brief Performs the low-level initialization of the chip.
|
| 93 | * This includes EFC and master clock configuration.
|
| 94 | * It also enable a low level on the pin NRST triggers a user reset.
|
| 95 | */
|
Christina Quast | 8be71e4 | 2014-12-02 13:06:01 +0100 | [diff] [blame] | 96 | extern WEAK void LowLevelInit( void )
|
Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 97 | {
|
| 98 | uint32_t timeout = 0;
|
| 99 |
|
Harald Welte | 372f4cc | 2016-03-16 22:17:39 +0100 | [diff] [blame] | 100 | /* enable both LED and green LED */
|
| 101 | PIOA->PIO_PER |= LED_RED | LED_GREEN;
|
| 102 | PIOA->PIO_OER |= LED_RED | LED_GREEN;
|
| 103 | PIOA->PIO_CODR |= LED_RED | LED_GREEN;
|
Harald Welte | 7abdb51 | 2016-03-03 17:48:32 +0100 | [diff] [blame] | 104 |
|
Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 105 | /* Set 3 FWS for Embedded Flash Access */
|
| 106 | EFC->EEFC_FMR = EEFC_FMR_FWS(3);
|
| 107 |
|
| 108 | /* Select external slow clock */
|
Christina Quast | 8be71e4 | 2014-12-02 13:06:01 +0100 | [diff] [blame] | 109 | /* if ((SUPC->SUPC_SR & SUPC_SR_OSCSEL) != SUPC_SR_OSCSEL_CRYST)
|
Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 110 | {
|
| 111 | SUPC->SUPC_CR = (uint32_t)(SUPC_CR_XTALSEL_CRYSTAL_SEL | SUPC_CR_KEY(0xA5));
|
| 112 | timeout = 0;
|
| 113 | while (!(SUPC->SUPC_SR & SUPC_SR_OSCSEL_CRYST) );
|
| 114 | }
|
Christina Quast | 8be71e4 | 2014-12-02 13:06:01 +0100 | [diff] [blame] | 115 | */
|
Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 116 |
|
Harald Welte | a02b641 | 2016-08-21 18:32:12 +0200 | [diff] [blame] | 117 | #ifndef qmod
|
Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 118 | /* Initialize main oscillator */
|
Harald Welte | 5e00400 | 2016-03-16 20:40:19 +0100 | [diff] [blame] | 119 | if ( !(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) )
|
Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 120 | {
|
| 121 | PMC->CKGR_MOR = CKGR_MOR_KEY(0x37) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;
|
| 122 | timeout = 0;
|
| 123 | while (!(PMC->PMC_SR & PMC_SR_MOSCXTS) && (timeout++ < CLOCK_TIMEOUT));
|
Harald Welte | 5e00400 | 2016-03-16 20:40:19 +0100 | [diff] [blame] | 124 | }
|
Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 125 |
|
| 126 | /* Switch to 3-20MHz Xtal oscillator */
|
Harald Welte | 5e00400 | 2016-03-16 20:40:19 +0100 | [diff] [blame] | 127 | PIOB->PIO_PDR = (1 << 8) | (1 << 9);
|
| 128 | PIOB->PIO_PUDR = (1 << 8) | (1 << 9);
|
| 129 | PIOB->PIO_PPDDR = (1 << 8) | (1 << 9);
|
Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 130 | PMC->CKGR_MOR = CKGR_MOR_KEY(0x37) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;
|
Harald Welte | 4678388 | 2016-02-29 19:45:59 +0100 | [diff] [blame] | 131 | /* wait for Main XTAL oscillator stabilization */
|
Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 132 | timeout = 0;
|
| 133 | while (!(PMC->PMC_SR & PMC_SR_MOSCSELS) && (timeout++ < CLOCK_TIMEOUT));
|
Harald Welte | a02b641 | 2016-08-21 18:32:12 +0200 | [diff] [blame] | 134 | #else
|
| 135 | /* QMOD has external 12MHz clock source */
|
| 136 | PIOB->PIO_PDR = (1 << 9);
|
| 137 | PIOB->PIO_PUDR = (1 << 9);
|
| 138 | PIOB->PIO_PPDDR = (1 << 9);
|
| 139 | PMC->CKGR_MOR = CKGR_MOR_KEY(0x37) | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTBY| CKGR_MOR_MOSCSEL;
|
| 140 | #endif
|
Harald Welte | 4678388 | 2016-02-29 19:45:59 +0100 | [diff] [blame] | 141 |
|
Harald Welte | 372f4cc | 2016-03-16 22:17:39 +0100 | [diff] [blame] | 142 | /* disable the red LED after main clock initialization */
|
| 143 | PIOA->PIO_SODR = LED_RED;
|
Harald Welte | 7abdb51 | 2016-03-03 17:48:32 +0100 | [diff] [blame] | 144 |
|
Harald Welte | 4678388 | 2016-02-29 19:45:59 +0100 | [diff] [blame] | 145 | /* "switch" to main clock as master clock source (should already be the case */
|
Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 146 | PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
|
Harald Welte | 4678388 | 2016-02-29 19:45:59 +0100 | [diff] [blame] | 147 | /* wait for master clock to be ready */
|
Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 148 | for ( timeout = 0; !(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT) ; );
|
| 149 |
|
| 150 | /* Initialize PLLA */
|
| 151 | PMC->CKGR_PLLAR = BOARD_PLLAR;
|
Harald Welte | 4678388 | 2016-02-29 19:45:59 +0100 | [diff] [blame] | 152 | /* Wait for PLLA to lock */
|
Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 153 | timeout = 0;
|
| 154 | while (!(PMC->PMC_SR & PMC_SR_LOCKA) && (timeout++ < CLOCK_TIMEOUT));
|
| 155 |
|
Harald Welte | 4678388 | 2016-02-29 19:45:59 +0100 | [diff] [blame] | 156 | /* Switch to main clock (again ?!?) */
|
Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 157 | PMC->PMC_MCKR = (BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
|
Harald Welte | 4678388 | 2016-02-29 19:45:59 +0100 | [diff] [blame] | 158 | /* wait for master clock to be ready */
|
Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 159 | for ( timeout = 0; !(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT) ; );
|
| 160 |
|
Harald Welte | 4678388 | 2016-02-29 19:45:59 +0100 | [diff] [blame] | 161 | /* switch to PLLA as master clock source */
|
Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 162 | PMC->PMC_MCKR = BOARD_MCKR ;
|
Harald Welte | 4678388 | 2016-02-29 19:45:59 +0100 | [diff] [blame] | 163 | /* wait for master clock to be ready */
|
Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 164 | for ( timeout = 0; !(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT) ; );
|
Harald Welte | 83207e0 | 2017-02-03 22:16:47 +0100 | [diff] [blame] | 165 |
|
| 166 | /* Configure SysTick for 1ms */
|
| 167 | SysTick_Config(BOARD_MCK/1000);
|
| 168 | }
|
| 169 |
|
| 170 | /* SysTick based delay function */
|
| 171 |
|
| 172 | volatile uint32_t jiffies;
|
| 173 |
|
| 174 | /* Interrupt handler for SysTick interrupt */
|
| 175 | void SysTick_Handler(void)
|
| 176 | {
|
| 177 | jiffies++;
|
| 178 | }
|
| 179 |
|
| 180 | void mdelay(unsigned int msecs)
|
| 181 | {
|
| 182 | uint32_t jiffies_start = jiffies;
|
| 183 | do {
|
| 184 | } while ((jiffies - jiffies_start) < msecs);
|
Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 185 | }
|