Christina Quast | 8be71e4 | 2014-12-02 13:06:01 +0100 | [diff] [blame] | 1 | /* ----------------------------------------------------------------------------
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| 2 | * ATMEL Microcontroller Software Support
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| 3 | * ----------------------------------------------------------------------------
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| 4 | * Copyright (c) 2008, Atmel Corporation
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| 5 | *
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| 6 | * All rights reserved.
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| 7 | *
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| 8 | * Redistribution and use in source and binary forms, with or without
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| 9 | * modification, are permitted provided that the following conditions are met:
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| 10 | *
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| 11 | * - Redistributions of source code must retain the above copyright notice,
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| 12 | * this list of conditions and the disclaimer below.
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| 13 | *
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| 14 | * Atmel's name may not be used to endorse or promote products derived from
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| 15 | * this software without specific prior written permission.
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| 16 | *
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| 17 | * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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| 19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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| 20 | * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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| 22 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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| 23 | * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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| 24 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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| 25 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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| 26 | * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | * ----------------------------------------------------------------------------
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| 28 | */
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| 29 |
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| 30 | /*
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| 31 | * \file
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| 32 | */
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| 33 |
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| 34 | /*----------------------------------------------------------------------------
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| 35 | * Headers
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| 36 | *----------------------------------------------------------------------------*/
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| 37 |
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| 38 | #include "chip.h"
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| 39 |
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| 40 | #include <assert.h>
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| 41 |
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| 42 | /*----------------------------------------------------------------------------
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| 43 | * Local definitions
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| 44 | *----------------------------------------------------------------------------*/
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| 45 |
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| 46 | /* Maximum number of interrupt sources that can be defined. This
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| 47 | * constant can be increased, but the current value is the smallest possible
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| 48 | * that will be compatible with all existing projects. */
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| 49 | #define MAX_INTERRUPT_SOURCES 7
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| 50 |
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| 51 | /*----------------------------------------------------------------------------
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| 52 | * Local types
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| 53 | *----------------------------------------------------------------------------*/
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| 54 |
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| 55 | /**
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| 56 | * Describes a PIO interrupt source, including the PIO instance triggering the
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| 57 | * interrupt and the associated interrupt handler.
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| 58 | */
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| 59 | typedef struct _InterruptSource
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| 60 | {
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| 61 | /* Pointer to the source pin instance. */
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| 62 | const Pin *pPin;
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| 63 |
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| 64 | /* Interrupt handler. */
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| 65 | void (*handler)( const Pin* ) ;
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| 66 | } InterruptSource ;
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| 67 |
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| 68 | /*----------------------------------------------------------------------------
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| 69 | * Local variables
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| 70 | *----------------------------------------------------------------------------*/
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| 71 |
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| 72 | /* List of interrupt sources. */
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| 73 | static InterruptSource _aIntSources[MAX_INTERRUPT_SOURCES] ;
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| 74 |
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| 75 | /* Number of currently defined interrupt sources. */
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| 76 | static uint32_t _dwNumSources = 0;
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| 77 |
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| 78 | /*----------------------------------------------------------------------------
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| 79 | * Local Functions
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| 80 | *----------------------------------------------------------------------------*/
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| 81 | /*----------------------------------------------------------------------------*/
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| 82 | /**
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| 83 | * \brief Stub, to handling all PIO Capture interrupts, if not defined.
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| 84 | */
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| 85 | /*----------------------------------------------------------------------------*/
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| 86 | //extern WEAK void PIO_CaptureHandler( void )
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| 87 | //{
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| 88 | //}
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| 89 |
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| 90 | /**
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| 91 | * \brief Handles all interrupts on the given PIO controller.
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| 92 | * \param id PIO controller ID.
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| 93 | * \param pPio PIO controller base address.
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| 94 | */
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| 95 | extern void PioInterruptHandler( uint32_t id, Pio *pPio )
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| 96 | {
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| 97 | uint32_t status;
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| 98 | uint32_t i;
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| 99 |
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| 100 | /* Read PIO controller status */
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| 101 | status = pPio->PIO_ISR;
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| 102 | status &= pPio->PIO_IMR;
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| 103 |
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| 104 | /* Check pending events */
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| 105 | if ( status != 0 )
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| 106 | {
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Christina Quast | 061fa6e | 2015-01-27 15:31:02 +0100 | [diff] [blame] | 107 | TRACE_DEBUG( "PIO interrupt on PIO controller #%" PRIu32 "\n\r", id ) ;
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Christina Quast | 8be71e4 | 2014-12-02 13:06:01 +0100 | [diff] [blame] | 108 |
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| 109 | /* Find triggering source */
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| 110 | i = 0;
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| 111 | while ( status != 0 )
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| 112 | {
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| 113 | /* There cannot be an unconfigured source enabled. */
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| 114 | assert(i < _dwNumSources);
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| 115 |
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| 116 | /* Source is configured on the same controller */
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| 117 | if (_aIntSources[i].pPin->id == id)
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| 118 | {
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| 119 | /* Source has PIOs whose statuses have changed */
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| 120 | if ( (status & _aIntSources[i].pPin->mask) != 0 )
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| 121 | {
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Christina Quast | 061fa6e | 2015-01-27 15:31:02 +0100 | [diff] [blame] | 122 | TRACE_DEBUG( "Interrupt source #%" PRIu32 " triggered\n\r", i ) ;
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Christina Quast | 8be71e4 | 2014-12-02 13:06:01 +0100 | [diff] [blame] | 123 |
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| 124 | _aIntSources[i].handler(_aIntSources[i].pPin);
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| 125 | status &= ~(_aIntSources[i].pPin->mask);
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| 126 | }
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| 127 | }
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| 128 | i++;
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| 129 | }
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| 130 | }
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| 131 | }
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| 132 |
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| 133 | /*----------------------------------------------------------------------------
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| 134 | * Global Functions
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| 135 | *----------------------------------------------------------------------------*/
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| 136 |
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| 137 | /**
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| 138 | * \brief Parallel IO Controller A interrupt handler
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| 139 | * \Redefined PIOA interrupt handler for NVIC interrupt table.
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| 140 | */
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| 141 | extern void PIOA_IrqHandler( void )
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| 142 | {
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| 143 | if ( PIOA->PIO_PCISR != 0 )
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| 144 | {
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| 145 | PIO_CaptureHandler() ;
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| 146 | }
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| 147 |
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| 148 | PioInterruptHandler( ID_PIOA, PIOA ) ;
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| 149 | }
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| 150 |
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| 151 | /**
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| 152 | * \brief Parallel IO Controller B interrupt handler
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| 153 | * \Redefined PIOB interrupt handler for NVIC interrupt table.
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| 154 | */
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| 155 | extern void PIOB_IrqHandler( void )
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| 156 | {
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| 157 | PioInterruptHandler( ID_PIOB, PIOB ) ;
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| 158 | }
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| 159 |
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| 160 | /**
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| 161 | * \brief Parallel IO Controller C interrupt handler
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| 162 | * \Redefined PIOC interrupt handler for NVIC interrupt table.
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| 163 | */
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| 164 | extern void PIOC_IrqHandler( void )
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| 165 | {
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| 166 | PioInterruptHandler( ID_PIOC, PIOC ) ;
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| 167 | }
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| 168 |
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| 169 | /**
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| 170 | * \brief Initializes the PIO interrupt management logic
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| 171 | *
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| 172 | * The desired priority of PIO interrupts must be provided.
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| 173 | * Calling this function multiple times result in the reset of currently
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| 174 | * configured interrupts.
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| 175 | *
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| 176 | * \param priority PIO controller interrupts priority.
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| 177 | */
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| 178 | extern void PIO_InitializeInterrupts( uint32_t dwPriority )
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| 179 | {
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| 180 | TRACE_DEBUG( "PIO_Initialize()\n\r" ) ;
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| 181 |
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| 182 | /* Reset sources */
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| 183 | _dwNumSources = 0 ;
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| 184 |
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| 185 | /* Configure PIO interrupt sources */
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| 186 | TRACE_DEBUG( "PIO_Initialize: Configuring PIOA\n\r" ) ;
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| 187 | PMC_EnablePeripheral( ID_PIOA ) ;
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| 188 | PIOA->PIO_ISR ;
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| 189 | PIOA->PIO_IDR = 0xFFFFFFFF ;
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| 190 | NVIC_DisableIRQ( PIOA_IRQn ) ;
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| 191 | NVIC_ClearPendingIRQ( PIOA_IRQn ) ;
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| 192 | NVIC_SetPriority( PIOA_IRQn, dwPriority ) ;
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| 193 | NVIC_EnableIRQ( PIOA_IRQn ) ;
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| 194 |
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| 195 | TRACE_DEBUG( "PIO_Initialize: Configuring PIOB\n\r" ) ;
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| 196 | PMC_EnablePeripheral( ID_PIOB ) ;
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| 197 | PIOB->PIO_ISR ;
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| 198 | PIOB->PIO_IDR = 0xFFFFFFFF ;
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| 199 | NVIC_DisableIRQ( PIOB_IRQn ) ;
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| 200 | NVIC_ClearPendingIRQ( PIOB_IRQn ) ;
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| 201 | NVIC_SetPriority( PIOB_IRQn, dwPriority ) ;
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| 202 | NVIC_EnableIRQ( PIOB_IRQn ) ;
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| 203 |
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| 204 | TRACE_DEBUG( "PIO_Initialize: Configuring PIOC\n\r" ) ;
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| 205 | PMC_EnablePeripheral( ID_PIOC ) ;
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| 206 | PIOC->PIO_ISR ;
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| 207 | PIOC->PIO_IDR = 0xFFFFFFFF ;
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| 208 | NVIC_DisableIRQ( PIOC_IRQn ) ;
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| 209 | NVIC_ClearPendingIRQ( PIOC_IRQn ) ;
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| 210 | NVIC_SetPriority( PIOC_IRQn, dwPriority ) ;
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| 211 | NVIC_EnableIRQ( PIOC_IRQn ) ;
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| 212 | }
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| 213 |
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| 214 | /**
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| 215 | * Configures a PIO or a group of PIO to generate an interrupt on status
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| 216 | * change. The provided interrupt handler will be called with the triggering
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| 217 | * pin as its parameter (enabling different pin instances to share the same
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| 218 | * handler).
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| 219 | * \param pPin Pointer to a Pin instance.
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| 220 | * \param handler Interrupt handler function pointer.
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| 221 | */
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| 222 | extern void PIO_ConfigureIt( const Pin *pPin, void (*handler)( const Pin* ) )
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| 223 | {
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| 224 | Pio* pio ;
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| 225 | InterruptSource* pSource ;
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| 226 |
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| 227 | TRACE_DEBUG( "PIO_ConfigureIt()\n\r" ) ;
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| 228 |
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| 229 | assert( pPin ) ;
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| 230 | pio = pPin->pio ;
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| 231 | assert( _dwNumSources < MAX_INTERRUPT_SOURCES ) ;
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| 232 |
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| 233 | /* Define new source */
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Christina Quast | 061fa6e | 2015-01-27 15:31:02 +0100 | [diff] [blame] | 234 | TRACE_DEBUG( "PIO_ConfigureIt: Defining new source #%" PRIu32 ".\n\r", _dwNumSources ) ;
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Christina Quast | 8be71e4 | 2014-12-02 13:06:01 +0100 | [diff] [blame] | 235 |
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| 236 | pSource = &(_aIntSources[_dwNumSources]) ;
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| 237 | pSource->pPin = pPin ;
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| 238 | pSource->handler = handler ;
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| 239 | _dwNumSources++ ;
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| 240 |
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| 241 | /* PIO3 with additional interrupt support
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| 242 | * Configure additional interrupt mode registers */
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| 243 | if ( pPin->attribute & PIO_IT_AIME )
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| 244 | {
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| 245 | // enable additional interrupt mode
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| 246 | pio->PIO_AIMER = pPin->mask ;
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| 247 |
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| 248 | // if bit field of selected pin is 1, set as Rising Edge/High level detection event
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| 249 | if ( pPin->attribute & PIO_IT_RE_OR_HL )
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| 250 | {
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| 251 | pio->PIO_REHLSR = pPin->mask ;
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| 252 | }
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| 253 | else
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| 254 | {
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| 255 | pio->PIO_FELLSR = pPin->mask;
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| 256 | }
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| 257 |
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| 258 | /* if bit field of selected pin is 1, set as edge detection source */
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| 259 | if (pPin->attribute & PIO_IT_EDGE)
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| 260 | pio->PIO_ESR = pPin->mask;
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| 261 | else
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| 262 | pio->PIO_LSR = pPin->mask;
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| 263 | }
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| 264 | else
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| 265 | {
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| 266 | /* disable additional interrupt mode */
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| 267 | pio->PIO_AIMDR = pPin->mask;
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| 268 | }
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| 269 | }
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| 270 |
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| 271 | /**
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| 272 | * Enables the given interrupt source if it has been configured. The status
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| 273 | * register of the corresponding PIO controller is cleared prior to enabling
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| 274 | * the interrupt.
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| 275 | * \param pPin Interrupt source to enable.
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| 276 | */
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| 277 | extern void PIO_EnableIt( const Pin *pPin )
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| 278 | {
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| 279 | TRACE_DEBUG( "PIO_EnableIt()\n\r" ) ;
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| 280 |
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| 281 | assert( pPin != NULL ) ;
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| 282 |
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| 283 | #ifndef NOASSERT
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| 284 | uint32_t i = 0;
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| 285 | uint32_t dwFound = 0;
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| 286 |
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| 287 | while ( (i < _dwNumSources) && !dwFound )
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| 288 | {
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| 289 | if ( _aIntSources[i].pPin == pPin )
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| 290 | {
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| 291 | dwFound = 1 ;
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| 292 | }
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| 293 | i++ ;
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| 294 | }
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| 295 | assert( dwFound != 0 ) ;
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| 296 | #endif
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| 297 |
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| 298 | pPin->pio->PIO_ISR;
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| 299 | pPin->pio->PIO_IER = pPin->mask ;
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| 300 | }
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| 301 |
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| 302 | /**
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| 303 | * Disables a given interrupt source, with no added side effects.
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| 304 | *
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| 305 | * \param pPin Interrupt source to disable.
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| 306 | */
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| 307 | extern void PIO_DisableIt( const Pin *pPin )
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| 308 | {
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| 309 | assert( pPin != NULL ) ;
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| 310 |
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| 311 | TRACE_DEBUG( "PIO_DisableIt()\n\r" ) ;
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| 312 |
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| 313 | pPin->pio->PIO_IDR = pPin->mask;
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| 314 | }
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| 315 |
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