Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 1 | /* ----------------------------------------------------------------------------
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| 2 | * ATMEL Microcontroller Software Support
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| 3 | * ----------------------------------------------------------------------------
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| 4 | * Copyright (c) 2009, Atmel Corporation
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| 5 | *
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| 6 | * All rights reserved.
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| 7 | *
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| 8 | * Redistribution and use in source and binary forms, with or without
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| 9 | * modification, are permitted provided that the following conditions are met:
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| 10 | *
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| 11 | * - Redistributions of source code must retain the above copyright notice,
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| 12 | * this list of conditions and the disclaimer below.
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| 13 | *
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| 14 | * Atmel's name may not be used to endorse or promote products derived from
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| 15 | * this software without specific prior written permission.
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| 16 | *
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| 17 | * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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| 19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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| 20 | * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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| 22 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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| 23 | * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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| 24 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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| 25 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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| 26 | * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | * ----------------------------------------------------------------------------
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| 28 | */
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| 29 |
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| 30 | /**
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| 31 | * \file
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| 32 | * This file contains the default exception handlers.
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| 33 | *
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| 34 | * \note
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| 35 | * The exception handler has weak aliases.
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| 36 | * As they are weak aliases, any function with the same name will override
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| 37 | * this definition.
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| 38 | */
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| 39 |
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| 40 | /*----------------------------------------------------------------------------
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| 41 | * Headers
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| 42 | *----------------------------------------------------------------------------*/
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| 43 |
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| 44 | #include "chip.h"
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| 45 |
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| 46 | /*----------------------------------------------------------------------------
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| 47 | * Exported functions
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| 48 | *----------------------------------------------------------------------------*/
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| 49 |
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| 50 | /**
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| 51 | * \brief Default interrupt handler for not used irq.
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| 52 | */
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| 53 | void IrqHandlerNotUsed( void )
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| 54 | {
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Harald Welte | e26c943 | 2016-03-20 17:24:33 +0100 | [diff] [blame] | 55 | printf("NotUsed\r\n");
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 56 | while ( 1 ) ;
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| 57 | }
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| 58 |
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| 59 | /**
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| 60 | * \brief Default NMI interrupt handler.
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| 61 | */
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| 62 | WEAK void NMI_Handler( void )
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| 63 | {
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Harald Welte | e26c943 | 2016-03-20 17:24:33 +0100 | [diff] [blame] | 64 | printf("NMI\r\n");
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 65 | while ( 1 ) ;
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| 66 | }
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| 67 |
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| 68 | /**
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| 69 | * \brief Default HardFault interrupt handler.
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| 70 | */
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Harald Welte | 990f010 | 2016-03-20 18:15:45 +0100 | [diff] [blame] | 71 | struct hardfault_args {
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| 72 | unsigned long r0;
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| 73 | unsigned long r1;
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| 74 | unsigned long r2;
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| 75 | unsigned long r3;
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| 76 | unsigned long r12;
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| 77 | unsigned long lr;
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| 78 | unsigned long pc;
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| 79 | unsigned long psr;
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| 80 | };
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| 81 |
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| 82 | void hard_fault_handler_c(struct hardfault_args *args)
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 83 | {
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Harald Welte | e26c943 | 2016-03-20 17:24:33 +0100 | [diff] [blame] | 84 | printf("HardFault\r\n");
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Harald Welte | 990f010 | 2016-03-20 18:15:45 +0100 | [diff] [blame] | 85 | printf("R0=%08x, R1=%08x, R2=%08x, R3=%08x, R12=%08x\r\n",
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| 86 | args->r0, args->r1, args->r2, args->r3, args->r12);
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| 87 | printf("LR[R14]=%08x, PC[R15]=%08x, PSR=%08x\r\n",
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| 88 | args->lr, args->pc, args->psr);
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| 89 | printf("BFAR=%08x, CFSR=%08x, HFSR=%08x\r\n",
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| 90 | SCB->BFAR, SCB->CFSR, SCB->HFSR);
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| 91 | printf("DFSR=%08x, AFSR=%08x, SHCSR=%08x\r\n",
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| 92 | SCB->DFSR, SCB->CFSR, SCB->SHCSR);
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 93 | while ( 1 ) ;
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| 94 | }
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| 95 |
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Harald Welte | 990f010 | 2016-03-20 18:15:45 +0100 | [diff] [blame] | 96 | __attribute__((naked))
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| 97 | WEAK void HardFault_Handler( void )
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| 98 | {
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| 99 | __asm volatile(
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| 100 | ".syntax unified \n"
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| 101 | " tst lr, #4 \n"
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| 102 | " ite eq \n"
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| 103 | " mrseq r0, msp \n"
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| 104 | " mrsne r0, psp \n"
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| 105 | //" ldr r1, [r0, #24] \n"
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| 106 | " b hard_fault_handler_c\n"
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| 107 | ".syntax divided \n");
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| 108 | }
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| 109 |
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 110 | /**
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| 111 | * \brief Default MemManage interrupt handler.
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| 112 | */
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| 113 | WEAK void MemManage_Handler( void )
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| 114 | {
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Harald Welte | e26c943 | 2016-03-20 17:24:33 +0100 | [diff] [blame] | 115 | printf("MemManage\r\n");
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 116 | while ( 1 ) ;
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| 117 | }
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| 118 |
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| 119 | /**
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| 120 | * \brief Default BusFault interrupt handler.
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| 121 | */
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| 122 | WEAK void BusFault_Handler( void )
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| 123 | {
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Harald Welte | e26c943 | 2016-03-20 17:24:33 +0100 | [diff] [blame] | 124 | printf("BusFault\r\n");
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 125 | while ( 1 ) ;
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| 126 | }
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| 127 |
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| 128 | /**
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| 129 | * \brief Default UsageFault interrupt handler.
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| 130 | */
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| 131 | WEAK void UsageFault_Handler( void )
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| 132 | {
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Harald Welte | e26c943 | 2016-03-20 17:24:33 +0100 | [diff] [blame] | 133 | printf("UsageFault\r\n");
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 134 | while ( 1 ) ;
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| 135 | }
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| 136 |
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| 137 | /**
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| 138 | * \brief Default SVC interrupt handler.
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| 139 | */
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| 140 | WEAK void SVC_Handler( void )
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| 141 | {
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Harald Welte | e26c943 | 2016-03-20 17:24:33 +0100 | [diff] [blame] | 142 | printf("SVC\r\n");
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 143 | while ( 1 ) ;
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| 144 | }
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| 145 |
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| 146 | /**
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| 147 | * \brief Default DebugMon interrupt handler.
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| 148 | */
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| 149 | WEAK void DebugMon_Handler( void )
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| 150 | {
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Harald Welte | e26c943 | 2016-03-20 17:24:33 +0100 | [diff] [blame] | 151 | printf("DebugMon\r\n");
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 152 | while ( 1 ) ;
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| 153 | }
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| 154 |
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| 155 | /**
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| 156 | * \brief Default PendSV interrupt handler.
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| 157 | */
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| 158 | WEAK void PendSV_Handler( void )
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| 159 | {
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Harald Welte | e26c943 | 2016-03-20 17:24:33 +0100 | [diff] [blame] | 160 | printf("PendSV\r\n");
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 161 | while ( 1 ) ;
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| 162 | }
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| 163 |
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| 164 | /**
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| 165 | * \brief Default SysTick interrupt handler.
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| 166 | */
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| 167 | WEAK void SysTick_Handler( void )
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| 168 | {
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Harald Welte | e26c943 | 2016-03-20 17:24:33 +0100 | [diff] [blame] | 169 | printf("SysTick\r\n");
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 170 | while ( 1 ) ;
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| 171 | }
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| 172 |
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| 173 | /**
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| 174 | * \brief Default interrupt handler for Supply Controller.
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| 175 | */
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| 176 | WEAK void SUPC_IrqHandler( void )
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| 177 | {
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Harald Welte | e26c943 | 2016-03-20 17:24:33 +0100 | [diff] [blame] | 178 | printf("SUPC\r\n");
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 179 | while ( 1 ) ;
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| 180 | }
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| 181 |
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| 182 | /**
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| 183 | * \brief Default interrupt handler for Reset Controller.
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| 184 | */
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| 185 | WEAK void RSTC_IrqHandler( void )
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| 186 | {
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Harald Welte | e26c943 | 2016-03-20 17:24:33 +0100 | [diff] [blame] | 187 | printf("RSTC\r\n");
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 188 | while ( 1 ) ;
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| 189 | }
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| 190 |
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| 191 | /**
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| 192 | * \brief Default interrupt handler for Real Time Clock.
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| 193 | */
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| 194 | WEAK void RTC_IrqHandler( void )
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| 195 | {
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Harald Welte | e26c943 | 2016-03-20 17:24:33 +0100 | [diff] [blame] | 196 | printf("RTC\r\n");
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 197 | while ( 1 ) ;
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| 198 | }
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| 199 |
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| 200 | /**
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| 201 | * \brief Default interrupt handler for Real Time Timer.
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| 202 | */
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| 203 | WEAK void RTT_IrqHandler( void )
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| 204 | {
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Harald Welte | e26c943 | 2016-03-20 17:24:33 +0100 | [diff] [blame] | 205 | printf("RTT\r\n");
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 206 | while ( 1 ) ;
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| 207 | }
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| 208 |
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| 209 | /**
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| 210 | * \brief Default interrupt handler for Watchdog Timer.
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| 211 | */
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| 212 | WEAK void WDT_IrqHandler( void )
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| 213 | {
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Harald Welte | e26c943 | 2016-03-20 17:24:33 +0100 | [diff] [blame] | 214 | printf("WDT\r\n");
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 215 | while ( 1 ) ;
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| 216 | }
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| 217 |
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| 218 | /**
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| 219 | * \brief Default interrupt handler for PMC.
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| 220 | */
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| 221 | WEAK void PMC_IrqHandler( void )
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| 222 | {
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Harald Welte | e26c943 | 2016-03-20 17:24:33 +0100 | [diff] [blame] | 223 | printf("PMC\r\n");
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 224 | while ( 1 ) ;
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| 225 | }
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| 226 |
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| 227 | /**
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| 228 | * \brief Default interrupt handler for EEFC.
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| 229 | */
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| 230 | WEAK void EEFC_IrqHandler( void )
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| 231 | {
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Harald Welte | e26c943 | 2016-03-20 17:24:33 +0100 | [diff] [blame] | 232 | printf("EEFC\r\n");
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 233 | while ( 1 ) ;
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| 234 | }
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| 235 |
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| 236 | /**
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| 237 | * \brief Default interrupt handler for UART0.
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| 238 | */
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| 239 | WEAK void UART0_IrqHandler( void )
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| 240 | {
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Harald Welte | e26c943 | 2016-03-20 17:24:33 +0100 | [diff] [blame] | 241 | printf("UART0\r\n");
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 242 | while ( 1 ) ;
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| 243 | }
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| 244 |
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| 245 | /**
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| 246 | * \brief Default interrupt handler for UART1.
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| 247 | */
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| 248 | WEAK void UART1_IrqHandler( void )
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| 249 | {
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Harald Welte | e26c943 | 2016-03-20 17:24:33 +0100 | [diff] [blame] | 250 | printf("UART1\r\n");
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 251 | while ( 1 ) ;
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| 252 | }
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| 253 |
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| 254 | /**
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| 255 | * \brief Default interrupt handler for SMC.
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| 256 | */
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| 257 | WEAK void SMC_IrqHandler( void )
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| 258 | {
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Harald Welte | e26c943 | 2016-03-20 17:24:33 +0100 | [diff] [blame] | 259 | printf("SMC\r\n");
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 260 | while ( 1 ) ;
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| 261 | }
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| 262 |
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| 263 | /**
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| 264 | * \brief Default interrupt handler for PIOA Controller.
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| 265 | */
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| 266 | WEAK void PIOA_IrqHandler( void )
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| 267 | {
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Harald Welte | e26c943 | 2016-03-20 17:24:33 +0100 | [diff] [blame] | 268 | printf("PIOA\r\n");
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 269 | while ( 1 ) ;
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| 270 | }
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| 271 |
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| 272 | /**
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| 273 | * \brief Default interrupt handler for PIOB Controller.
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| 274 | */
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| 275 | WEAK void PIOB_IrqHandler( void )
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| 276 | {
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Harald Welte | e26c943 | 2016-03-20 17:24:33 +0100 | [diff] [blame] | 277 | printf("PIOB\r\n");
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 278 | while ( 1 ) ;
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| 279 | }
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| 280 |
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| 281 | /**
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| 282 | * \brief Default interrupt handler for PIOC Controller.
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| 283 | */
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| 284 | WEAK void PIOC_IrqHandler( void )
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| 285 | {
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Harald Welte | e26c943 | 2016-03-20 17:24:33 +0100 | [diff] [blame] | 286 | printf("PIOC\r\n");
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 287 | while ( 1 ) ;
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| 288 | }
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| 289 |
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| 290 | /**
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| 291 | * \brief Default interrupt handler for USART0.
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| 292 | */
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| 293 | WEAK void USART0_IrqHandler( void )
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| 294 | {
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Harald Welte | e26c943 | 2016-03-20 17:24:33 +0100 | [diff] [blame] | 295 | printf("USART0\r\n");
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 296 | while ( 1 ) ;
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| 297 | }
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| 298 |
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| 299 | /**
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| 300 | * \brief Default interrupt handler for USART1.
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| 301 | */
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| 302 | WEAK void USART1_IrqHandler( void )
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| 303 | {
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Harald Welte | e26c943 | 2016-03-20 17:24:33 +0100 | [diff] [blame] | 304 | printf("USART1\r\n");
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 305 | while ( 1 ) ;
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| 306 | }
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| 307 |
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| 308 | /**
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| 309 | * \brief Default interrupt handler for MCI.
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| 310 | */
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| 311 | WEAK void MCI_IrqHandler( void )
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| 312 | {
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Harald Welte | e26c943 | 2016-03-20 17:24:33 +0100 | [diff] [blame] | 313 | printf("MCI\r\n");
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 314 | while ( 1 ) ;
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| 315 | }
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| 316 |
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| 317 | /**
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| 318 | * \brief Default interrupt handler for TWI0.
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| 319 | */
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| 320 | WEAK void TWI0_IrqHandler( void )
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| 321 | {
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Harald Welte | e26c943 | 2016-03-20 17:24:33 +0100 | [diff] [blame] | 322 | printf("TWI0\r\n");
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 323 | while ( 1 ) ;
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| 324 | }
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| 325 |
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| 326 | /**
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| 327 | * \brief Default interrupt handler for TWI1.
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| 328 | */
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| 329 | WEAK void TWI1_IrqHandler( void )
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| 330 | {
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Harald Welte | e26c943 | 2016-03-20 17:24:33 +0100 | [diff] [blame] | 331 | printf("TWI1\r\n");
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 332 | while ( 1 ) ;
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| 333 | }
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| 334 |
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| 335 | /**
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| 336 | * \brief Default interrupt handler for SPI.
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| 337 | */
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| 338 | WEAK void SPI_IrqHandler( void )
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| 339 | {
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Harald Welte | e26c943 | 2016-03-20 17:24:33 +0100 | [diff] [blame] | 340 | printf("SPI\r\n");
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 341 | while ( 1 ) ;
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| 342 | }
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| 343 |
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| 344 | /**
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| 345 | * \brief Default interrupt handler for SSC.
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| 346 | */
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| 347 | WEAK void SSC_IrqHandler( void )
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| 348 | {
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Harald Welte | e26c943 | 2016-03-20 17:24:33 +0100 | [diff] [blame] | 349 | printf("SSC\r\n");
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 350 | while ( 1 ) ;
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| 351 | }
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| 352 |
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| 353 | /**
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| 354 | * \brief Default interrupt handler for TC0.
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| 355 | */
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| 356 | WEAK void TC0_IrqHandler( void )
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| 357 | {
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Harald Welte | e26c943 | 2016-03-20 17:24:33 +0100 | [diff] [blame] | 358 | printf("TC0\r\n");
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 359 | while ( 1 ) ;
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| 360 | }
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| 361 |
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| 362 | /**
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| 363 | * \brief Default interrupt handler for TC1.
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| 364 | */
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| 365 | WEAK void TC1_IrqHandler( void )
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| 366 | {
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Harald Welte | e26c943 | 2016-03-20 17:24:33 +0100 | [diff] [blame] | 367 | printf("TC1\r\n");
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 368 | while ( 1 ) ;
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| 369 | }
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| 370 |
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| 371 | /**
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| 372 | * \brief Default interrupt handler for TC2.
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| 373 | */
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| 374 | WEAK void TC2_IrqHandler( void )
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| 375 | {
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Harald Welte | e26c943 | 2016-03-20 17:24:33 +0100 | [diff] [blame] | 376 | printf("TC2\r\n");
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 377 | while ( 1 ) ;
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| 378 | }
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| 379 |
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| 380 | /**
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| 381 | * \brief Default SUPC interrupt handler for TC3.
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| 382 | */
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| 383 | WEAK void TC3_IrqHandler( void )
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| 384 | {
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Harald Welte | e26c943 | 2016-03-20 17:24:33 +0100 | [diff] [blame] | 385 | printf("TC3\r\n");
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 386 | while ( 1 ) ;
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| 387 | }
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| 388 |
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| 389 | /**
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| 390 | * \brief Default SUPC interrupt handler for TC4.
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| 391 | */
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| 392 | WEAK void TC4_IrqHandler( void )
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| 393 | {
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Harald Welte | e26c943 | 2016-03-20 17:24:33 +0100 | [diff] [blame] | 394 | printf("TC4\r\n");
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 395 | while ( 1 ) ;
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| 396 | }
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| 397 |
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| 398 | /**
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| 399 | * \brief Default SUPC interrupt handler for TC5.
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| 400 | */
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| 401 | WEAK void TC5_IrqHandler( void )
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| 402 | {
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Harald Welte | e26c943 | 2016-03-20 17:24:33 +0100 | [diff] [blame] | 403 | printf("TC5\r\n");
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 404 | while ( 1 ) ;
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| 405 | }
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| 406 |
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| 407 | /**
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| 408 | * \brief Default SUPC interrupt handler for ADC.
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| 409 | */
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| 410 | WEAK void ADC_IrqHandler( void )
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| 411 | {
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Harald Welte | e26c943 | 2016-03-20 17:24:33 +0100 | [diff] [blame] | 412 | printf("ADC\r\n");
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 413 | while ( 1 ) ;
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| 414 | }
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| 415 |
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| 416 | /**
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| 417 | * \brief Default SUPC interrupt handler for DAC.
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| 418 | */
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| 419 | WEAK void DAC_IrqHandler( void )
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| 420 | {
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Harald Welte | e26c943 | 2016-03-20 17:24:33 +0100 | [diff] [blame] | 421 | printf("DAC\r\n");
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 422 | while ( 1 ) ;
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| 423 | }
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| 424 |
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| 425 | /**
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| 426 | * \brief Default SUPC interrupt handler for PWM.
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| 427 | */
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| 428 | WEAK void PWM_IrqHandler( void )
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| 429 | {
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Harald Welte | e26c943 | 2016-03-20 17:24:33 +0100 | [diff] [blame] | 430 | printf("PWM\r\n");
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 431 | while ( 1 ) ;
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| 432 | }
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| 433 |
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| 434 | /**
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| 435 | * \brief Default SUPC interrupt handler for CRCCU.
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| 436 | */
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| 437 | WEAK void CRCCU_IrqHandler( void )
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| 438 | {
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Harald Welte | e26c943 | 2016-03-20 17:24:33 +0100 | [diff] [blame] | 439 | printf("CRCCU\r\n");
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 440 | while ( 1 ) ;
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| 441 | }
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| 442 |
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| 443 | /**
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| 444 | * \brief Default SUPC interrupt handler for ACC.
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| 445 | */
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| 446 | WEAK void ACC_IrqHandler( void )
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| 447 | {
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Harald Welte | e26c943 | 2016-03-20 17:24:33 +0100 | [diff] [blame] | 448 | printf("ACC\r\n");
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 449 | while ( 1 ) ;
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| 450 | }
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| 451 |
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| 452 | /**
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| 453 | * \brief Default SUPC interrupt handler for USBD.
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| 454 | */
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| 455 | WEAK void USBD_IrqHandler( void )
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| 456 | {
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Harald Welte | e26c943 | 2016-03-20 17:24:33 +0100 | [diff] [blame] | 457 | printf("USBD\r\n");
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Christina Quast | b0a0570 | 2014-11-28 10:27:32 +0100 | [diff] [blame] | 458 | while ( 1 ) ;
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| 459 | }
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