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| 58 | <body> |
| 59 | <h1>Cortex Microcontroller Software Interface Standard</h1> |
| 60 | |
| 61 | <p align="center">This file describes the Cortex Microcontroller Software Interface Standard (CMSIS).</p> |
| 62 | <p align="center">Version: 1.30 - 30. October 2009</p> |
| 63 | |
| 64 | <p class="TinyT">Information in this file, the accompany manuals, and software is<br> |
| 65 | Copyright © ARM Ltd.<br>All rights reserved. |
| 66 | </p> |
| 67 | |
| 68 | <hr> |
| 69 | |
| 70 | <p><span style="FONT-WEIGHT: bold">Revision History</span></p> |
| 71 | <ul> |
| 72 | <li>Version 1.00: initial release. </li> |
| 73 | <li>Version 1.01: added __LDREX<em>x</em>, __STREX<em>x</em>, and __CLREX.</li> |
| 74 | <li>Version 1.02: added Cortex-M0. </li> |
| 75 | <li>Version 1.10: second review. </li> |
| 76 | <li>Version 1.20: third review. </li> |
| 77 | <li>Version 1.30 PRE-RELEASE: reworked Startup Concept, additional Debug Functionality.</li> |
| 78 | <li>Version 1.30 2nd PRE-RELEASE: changed folder structure, added doxyGen comments, added Bit definitions.</li> |
| 79 | <li>Version 1.30: updated Device Support Packages.</li> |
| 80 | </ul> |
| 81 | |
| 82 | <hr> |
| 83 | |
| 84 | <h2>Contents</h2> |
| 85 | |
| 86 | <ol> |
| 87 | <li class="LI2"><a href="#1">About</a></li> |
| 88 | <li class="LI2"><a href="#2">Coding Rules and Conventions</a></li> |
| 89 | <li class="LI2"><a href="#3">CMSIS Files</a></li> |
| 90 | <li class="LI2"><a href="#4">Core Peripheral Access Layer</a></li> |
| 91 | <li class="LI2"><a href="#5">CMSIS Example</a></li> |
| 92 | </ol> |
| 93 | |
| 94 | <h2><a name="1"></a>About</h2> |
| 95 | |
| 96 | <p> |
| 97 | The <strong>Cortex Microcontroller Software Interface Standard (CMSIS)</strong> answers the challenges |
| 98 | that are faced when software components are deployed to physical microcontroller devices based on a |
| 99 | Cortex-M0 or Cortex-M3 processor. The CMSIS will be also expanded to future Cortex-M |
| 100 | processor cores (the term Cortex-M is used to indicate that). The CMSIS is defined in close co-operation |
| 101 | with various silicon and software vendors and provides a common approach to interface to peripherals, |
| 102 | real-time operating systems, and middleware components. |
| 103 | </p> |
| 104 | |
| 105 | <p>ARM provides as part of the CMSIS the following software layers that are |
| 106 | available for various compiler implementations:</p> |
| 107 | <ul> |
| 108 | <li><strong>Core Peripheral Access Layer</strong>: contains name definitions, |
| 109 | address definitions and helper functions to |
| 110 | access core registers and peripherals. It defines also a device |
| 111 | independent interface for RTOS Kernels that includes debug channel |
| 112 | definitions.</li> |
| 113 | </ul> |
| 114 | |
| 115 | <p>These software layers are expanded by Silicon partners with:</p> |
| 116 | <ul> |
| 117 | <li><strong>Device Peripheral Access Layer</strong>: provides definitions |
| 118 | for all device peripherals</li> |
| 119 | <li><strong>Access Functions for Peripherals (optional)</strong>: provides |
| 120 | additional helper functions for peripherals</li> |
| 121 | </ul> |
| 122 | |
| 123 | <p>CMSIS defines for a Cortex-M Microcontroller System:</p> |
| 124 | <ul> |
| 125 | <li style="text-align: left;">A common way to access peripheral registers |
| 126 | and a common way to define exception vectors.</li> |
| 127 | <li style="text-align: left;">The register names of the <strong>Core |
| 128 | Peripherals</strong> and<strong> </strong>the names of the <strong>Core |
| 129 | Exception Vectors</strong>.</li> |
| 130 | <li>An device independent interface for RTOS Kernels including a debug |
| 131 | channel.</li> |
| 132 | </ul> |
| 133 | |
| 134 | <p> |
| 135 | By using CMSIS compliant software components, the user can easier re-use template code. |
| 136 | CMSIS is intended to enable the combination of software components from multiple middleware vendors. |
| 137 | </p> |
| 138 | |
| 139 | <h2><a name="2"></a>Coding Rules and Conventions</h2> |
| 140 | |
| 141 | <p> |
| 142 | The following section describes the coding rules and conventions used in the CMSIS |
| 143 | implementation. It contains also information about data types and version number information. |
| 144 | </p> |
| 145 | |
| 146 | <h3>Essentials</h3> |
| 147 | <ul> |
| 148 | <li>The CMSIS C code conforms to MISRA 2004 rules. In case of MISRA violations, |
| 149 | there are disable and enable sequences for PC-LINT inserted.</li> |
| 150 | <li>ANSI standard data types defined in the ANSI C header file |
| 151 | <strong><stdint.h></strong> are used.</li> |
| 152 | <li>#define constants that include expressions must be enclosed by |
| 153 | parenthesis.</li> |
| 154 | <li>Variables and parameters have a complete data type.</li> |
| 155 | <li>All functions in the <strong>Core Peripheral Access Layer</strong> are |
| 156 | re-entrant.</li> |
| 157 | <li>The <strong>Core Peripheral Access Layer</strong> has no blocking code |
| 158 | (which means that wait/query loops are done at other software layers).</li> |
| 159 | <li>For each exception/interrupt there is definition for: |
| 160 | <ul> |
| 161 | <li>an exception/interrupt handler with the postfix <strong>_Handler </strong> |
| 162 | (for exceptions) or <strong>_IRQHandler</strong> (for interrupts).</li> |
| 163 | <li>a default exception/interrupt handler (weak definition) that contains an endless loop.</li> |
| 164 | <li>a #define of the interrupt number with the postfix <strong>_IRQn</strong>.</li> |
| 165 | </ul></li> |
| 166 | </ul> |
| 167 | |
| 168 | <h3>Recommendations</h3> |
| 169 | |
| 170 | <p>The CMSIS recommends the following conventions for identifiers.</p> |
| 171 | <ul> |
| 172 | <li><strong>CAPITAL</strong> names to identify Core Registers, Peripheral Registers, and CPU Instructions.</li> |
| 173 | <li><strong>CamelCase</strong> names to identify peripherals access functions and interrupts.</li> |
| 174 | <li><strong>PERIPHERAL_</strong> prefix to identify functions that belong to specify peripherals.</li> |
| 175 | <li><strong>Doxygen</strong> comments for all functions are included as described under <strong>Function Comments</strong> below.</li> |
| 176 | </ul> |
| 177 | |
| 178 | <b>Comments</b> |
| 179 | |
| 180 | <ul> |
| 181 | <li>Comments use the ANSI C90 style (<em>/* comment */</em>) or C++ style |
| 182 | (<em>// comment</em>). It is assumed that the programming tools support today |
| 183 | consistently the C++ comment style.</li> |
| 184 | <li><strong>Function Comments</strong> provide for each function the following information: |
| 185 | <ul> |
| 186 | <li>one-line brief function overview.</li> |
| 187 | <li>detailed parameter explanation.</li> |
| 188 | <li>detailed information about return values.</li> |
| 189 | <li>detailed description of the actual function.</li> |
| 190 | </ul> |
| 191 | <p><b>Doxygen Example:</b></p> |
| 192 | <pre> |
| 193 | /** |
| 194 | * @brief Enable Interrupt in NVIC Interrupt Controller |
| 195 | * @param IRQn interrupt number that specifies the interrupt |
| 196 | * @return none. |
| 197 | * Enable the specified interrupt in the NVIC Interrupt Controller. |
| 198 | * Other settings of the interrupt such as priority are not affected. |
| 199 | */</pre> |
| 200 | </li> |
| 201 | </ul> |
| 202 | |
| 203 | <h3>Data Types and IO Type Qualifiers</h3> |
| 204 | |
| 205 | <p> |
| 206 | The <strong>Cortex-M HAL</strong> uses the standard types from the standard ANSI C header file |
| 207 | <strong><stdint.h></strong>. <strong>IO Type Qualifiers</strong> are used to specify the access |
| 208 | to peripheral variables. IO Type Qualifiers are indented to be used for automatic generation of |
| 209 | debug information of peripheral registers. |
| 210 | </p> |
| 211 | |
| 212 | <table class="kt" border="0" cellpadding="0" cellspacing="0"> |
| 213 | <tbody> |
| 214 | <tr> |
| 215 | <th class="kt" nowrap="nowrap">IO Type Qualifier</th> |
| 216 | <th class="kt">#define</th> |
| 217 | <th class="kt">Description</th> |
| 218 | </tr> |
| 219 | <tr> |
| 220 | <td class="kt" nowrap="nowrap">__I</td> |
| 221 | <td class="kt">volatile const</td> |
| 222 | <td class="kt">Read access only</td> |
| 223 | </tr> |
| 224 | <tr> |
| 225 | <td class="kt" nowrap="nowrap">__O</td> |
| 226 | <td class="kt">volatile</td> |
| 227 | <td class="kt">Write access only</td> |
| 228 | </tr> |
| 229 | <tr> |
| 230 | <td class="kt" nowrap="nowrap">__IO</td> |
| 231 | <td class="kt">volatile</td> |
| 232 | <td class="kt">Read and write access</td> |
| 233 | </tr> |
| 234 | </tbody> |
| 235 | </table> |
| 236 | |
| 237 | <h3>CMSIS Version Number</h3> |
| 238 | <p> |
| 239 | File <strong>core_cm3.h</strong> contains the version number of the CMSIS with the following define: |
| 240 | </p> |
| 241 | |
| 242 | <pre> |
| 243 | #define __CM3_CMSIS_VERSION_MAIN (0x01) /* [31:16] main version */ |
| 244 | #define __CM3_CMSIS_VERSION_SUB (0x30) /* [15:0] sub version */ |
| 245 | #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB)</pre> |
| 246 | |
| 247 | <p> |
| 248 | File <strong>core_cm0.h</strong> contains the version number of the CMSIS with the following define: |
| 249 | </p> |
| 250 | |
| 251 | <pre> |
| 252 | #define __CM0_CMSIS_VERSION_MAIN (0x01) /* [31:16] main version */ |
| 253 | #define __CM0_CMSIS_VERSION_SUB (0x30) /* [15:0] sub version */ |
| 254 | #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB)</pre> |
| 255 | |
| 256 | |
| 257 | <h3>CMSIS Cortex Core</h3> |
| 258 | <p> |
| 259 | File <strong>core_cm3.h</strong> contains the type of the CMSIS Cortex-M with the following define: |
| 260 | </p> |
| 261 | |
| 262 | <pre> |
| 263 | #define __CORTEX_M (0x03)</pre> |
| 264 | |
| 265 | <p> |
| 266 | File <strong>core_cm0.h</strong> contains the type of the CMSIS Cortex-M with the following define: |
| 267 | </p> |
| 268 | |
| 269 | <pre> |
| 270 | #define __CORTEX_M (0x00)</pre> |
| 271 | |
| 272 | |
| 273 | <h2><a name="3"></a>CMSIS Files</h2> |
| 274 | <p> |
| 275 | This section describes the Files provided in context with the CMSIS to access the Cortex-M |
| 276 | hardware and peripherals. |
| 277 | </p> |
| 278 | |
| 279 | <table class="kt" border="0" cellpadding="0" cellspacing="0"> |
| 280 | <tbody> |
| 281 | <tr> |
| 282 | <th class="kt" nowrap="nowrap">File</th> |
| 283 | <th class="kt">Provider</th> |
| 284 | <th class="kt">Description</th> |
| 285 | </tr> |
| 286 | <tr> |
| 287 | <td class="kt" nowrap="nowrap"><i>device.h</i></td> |
| 288 | <td class="kt">Device specific (provided by silicon partner)</td> |
| 289 | <td class="kt">Defines the peripherals for the actual device. The file may use |
| 290 | several other include files to define the peripherals of the actual device.</td> |
| 291 | </tr> |
| 292 | <tr> |
| 293 | <td class="kt" nowrap="nowrap">core_cm0.h</td> |
| 294 | <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td> |
| 295 | <td class="kt">Defines the core peripherals for the Cortex-M0 CPU and core peripherals.</td> |
| 296 | </tr> |
| 297 | <tr> |
| 298 | <td class="kt" nowrap="nowrap">core_cm3.h</td> |
| 299 | <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td> |
| 300 | <td class="kt">Defines the core peripherals for the Cortex-M3 CPU and core peripherals.</td> |
| 301 | </tr> |
| 302 | <tr> |
| 303 | <td class="kt" nowrap="nowrap">core_cm0.c</td> |
| 304 | <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td> |
| 305 | <td class="kt">Provides helper functions that access core registers.</td> |
| 306 | </tr> |
| 307 | <tr> |
| 308 | <td class="kt" nowrap="nowrap">core_cm3.c</td> |
| 309 | <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td> |
| 310 | <td class="kt">Provides helper functions that access core registers.</td> |
| 311 | </tr> |
| 312 | <tr> |
| 313 | <td class="kt" nowrap="nowrap">startup<i>_device</i></td> |
| 314 | <td class="kt">ARM (adapted by compiler partner / silicon partner)</td> |
| 315 | <td class="kt">Provides the Cortex-M startup code and the complete (device specific) Interrupt Vector Table</td> |
| 316 | </tr> |
| 317 | <tr> |
| 318 | <td class="kt" nowrap="nowrap">system<i>_device</i></td> |
| 319 | <td class="kt">ARM (adapted by silicon partner)</td> |
| 320 | <td class="kt">Provides a device specific configuration file for the device. It configures the device initializes |
| 321 | typically the oscillator (PLL) that is part of the microcontroller device</td> |
| 322 | </tr> |
| 323 | </tbody> |
| 324 | </table> |
| 325 | |
| 326 | <h3><em>device.h</em></h3> |
| 327 | |
| 328 | <p> |
| 329 | The file <em><strong>device.h</strong></em> is provided by the silicon vendor and is the |
| 330 | <u><strong>central include file</strong></u> that the application programmer is using in |
| 331 | the C source code. This file contains: |
| 332 | </p> |
| 333 | <ul> |
| 334 | <li> |
| 335 | <p><strong>Interrupt Number Definition</strong>: provides interrupt numbers |
| 336 | (IRQn) for all core and device specific exceptions and interrupts.</p> |
| 337 | </li> |
| 338 | <li> |
| 339 | <p><strong>Configuration for core_cm0.h / core_cm3.h</strong>: reflects the |
| 340 | actual configuration of the Cortex-M processor that is part of the actual |
| 341 | device. As such the file <strong>core_cm0.h / core_cm3.h</strong> is included that |
| 342 | implements access to processor registers and core peripherals. </p> |
| 343 | </li> |
| 344 | <li> |
| 345 | <p><strong>Device Peripheral Access Layer</strong>: provides definitions |
| 346 | for all device peripherals. It contains all data structures and the address |
| 347 | mapping for the device specific peripherals. </p> |
| 348 | </li> |
| 349 | <li><strong>Access Functions for Peripherals (optional)</strong>: provides |
| 350 | additional helper functions for peripherals that are useful for programming |
| 351 | of these peripherals. Access Functions may be provided as inline functions |
| 352 | or can be extern references to a device specific library provided by the |
| 353 | silicon vendor.</li> |
| 354 | </ul> |
| 355 | |
| 356 | |
| 357 | <h4><strong>Interrupt Number Definition</strong></h4> |
| 358 | |
| 359 | <p>To access the device specific interrupts the device.h file defines IRQn |
| 360 | numbers for the complete device using a enum typedef as shown below:</p> |
| 361 | <pre> |
| 362 | typedef enum IRQn |
| 363 | { |
| 364 | /****** Cortex-M3 Processor Exceptions/Interrupt Numbers ************************************************/ |
| 365 | NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ |
| 366 | HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ |
| 367 | MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ |
| 368 | BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ |
| 369 | UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ |
| 370 | SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ |
| 371 | DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ |
| 372 | PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ |
| 373 | SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ |
| 374 | /****** STM32 specific Interrupt Numbers ****************************************************************/ |
| 375 | WWDG_STM_IRQn = 0, /*!< Window WatchDog Interrupt */ |
| 376 | PVD_STM_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ |
| 377 | : |
| 378 | : |
| 379 | } IRQn_Type;</pre> |
| 380 | |
| 381 | |
| 382 | <h4>Configuration for core_cm0.h / core_cm3.h</h4> |
| 383 | <p> |
| 384 | The Cortex-M core configuration options which are defined for each device implementation. Some |
| 385 | configuration options are reflected in the CMSIS layer using the #define settings described below. |
| 386 | </p> |
| 387 | <p> |
| 388 | To access core peripherals file <em><strong>device.h</strong></em> includes file <b>core_cm0.h / core_cm3.h</b>. |
| 389 | Several features in <strong>core_cm0.h / core_cm3.h</strong> are configured by the following defines that must be |
| 390 | defined before <strong>#include <core_cm0.h></strong> / <strong>#include <core_cm3.h></strong> |
| 391 | preprocessor command. |
| 392 | </p> |
| 393 | |
| 394 | <table class="kt" border="0" cellpadding="0" cellspacing="0"> |
| 395 | <tbody> |
| 396 | <tr> |
| 397 | <th class="kt" nowrap="nowrap">#define</th> |
| 398 | <th class="kt" nowrap="nowrap">File</th> |
| 399 | <th class="kt" nowrap="nowrap">Value</th> |
| 400 | <th class="kt">Description</th> |
| 401 | </tr> |
| 402 | <tr> |
| 403 | <td class="kt" nowrap="nowrap">__NVIC_PRIO_BITS</td> |
| 404 | <td class="kt">core_cm0.h</td> |
| 405 | <td class="kt" nowrap="nowrap">(2)</td> |
| 406 | <td class="kt">Number of priority bits implemented in the NVIC (device specific)</td> |
| 407 | </tr> |
| 408 | <tr> |
| 409 | <td class="kt" nowrap="nowrap">__NVIC_PRIO_BITS</td> |
| 410 | <td class="kt">core_cm3.h</td> |
| 411 | <td class="kt" nowrap="nowrap">(2 ... 8)</td> |
| 412 | <td class="kt">Number of priority bits implemented in the NVIC (device specific)</td> |
| 413 | </tr> |
| 414 | <tr> |
| 415 | <td class="kt" nowrap="nowrap">__MPU_PRESENT</td> |
| 416 | <td class="kt">core_cm0.h, core_cm3.h</td> |
| 417 | <td class="kt" nowrap="nowrap">(0, 1)</td> |
| 418 | <td class="kt">Defines if an MPU is present or not</td> |
| 419 | </tr> |
| 420 | <tr> |
| 421 | <td class="kt" nowrap="nowrap">__Vendor_SysTickConfig</td> |
| 422 | <td class="kt">core_cm0.h, core_cm3.h</td> |
| 423 | <td class="kt" nowrap="nowrap">(1)</td> |
| 424 | <td class="kt">When this define is setup to 1, the <strong>SysTickConfig</strong> function |
| 425 | in <strong>core_cm3.h</strong> is excluded. In this case the <em><strong>device.h</strong></em> |
| 426 | file must contain a vendor specific implementation of this function.</td> |
| 427 | </tr> |
| 428 | </tbody> |
| 429 | </table> |
| 430 | |
| 431 | |
| 432 | <h4>Device Peripheral Access Layer</h4> |
| 433 | <p> |
| 434 | Each peripheral uses a prefix which consists of <strong><device abbreviation>_</strong> |
| 435 | and <strong><peripheral name>_</strong> to identify peripheral registers that access this |
| 436 | specific peripheral. The intention of this is to avoid name collisions caused |
| 437 | due to short names. If more than one peripheral of the same type exists, |
| 438 | identifiers have a postfix (digit or letter). For example: |
| 439 | </p> |
| 440 | <ul> |
| 441 | <li><device abbreviation>_UART_Type: defines the generic register layout for all UART channels in a device. |
| 442 | <pre> |
| 443 | typedef struct |
| 444 | { |
| 445 | union { |
| 446 | __I uint8_t RBR; /*!< Offset: 0x000 Receiver Buffer Register */ |
| 447 | __O uint8_t THR; /*!< Offset: 0x000 Transmit Holding Register */ |
| 448 | __IO uint8_t DLL; /*!< Offset: 0x000 Divisor Latch LSB */ |
| 449 | uint32_t RESERVED0; |
| 450 | }; |
| 451 | union { |
| 452 | __IO uint8_t DLM; /*!< Offset: 0x004 Divisor Latch MSB */ |
| 453 | __IO uint32_t IER; /*!< Offset: 0x004 Interrupt Enable Register */ |
| 454 | }; |
| 455 | union { |
| 456 | __I uint32_t IIR; /*!< Offset: 0x008 Interrupt ID Register */ |
| 457 | __O uint8_t FCR; /*!< Offset: 0x008 FIFO Control Register */ |
| 458 | }; |
| 459 | __IO uint8_t LCR; /*!< Offset: 0x00C Line Control Register */ |
| 460 | uint8_t RESERVED1[7]; |
| 461 | __I uint8_t LSR; /*!< Offset: 0x014 Line Status Register */ |
| 462 | uint8_t RESERVED2[7]; |
| 463 | __IO uint8_t SCR; /*!< Offset: 0x01C Scratch Pad Register */ |
| 464 | uint8_t RESERVED3[3]; |
| 465 | __IO uint32_t ACR; /*!< Offset: 0x020 Autobaud Control Register */ |
| 466 | __IO uint8_t ICR; /*!< Offset: 0x024 IrDA Control Register */ |
| 467 | uint8_t RESERVED4[3]; |
| 468 | __IO uint8_t FDR; /*!< Offset: 0x028 Fractional Divider Register */ |
| 469 | uint8_t RESERVED5[7]; |
| 470 | __IO uint8_t TER; /*!< Offset: 0x030 Transmit Enable Register */ |
| 471 | uint8_t RESERVED6[39]; |
| 472 | __I uint8_t FIFOLVL; /*!< Offset: 0x058 FIFO Level Register */ |
| 473 | } LPC_UART_TypeDef;</pre> |
| 474 | </li> |
| 475 | <li><device abbreviation>_UART1: is a pointer to a register structure that refers to a specific UART. |
| 476 | For example UART1->DR is the data register of UART1. |
| 477 | <pre> |
| 478 | #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE ) |
| 479 | #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )</pre> |
| 480 | </li> |
| 481 | </ul> |
| 482 | |
| 483 | <h5>Minimal Requiements</h5> |
| 484 | <p> |
| 485 | To access the peripheral registers and related function in a device the files <strong><em>device.h</em></strong> |
| 486 | and <strong>core_cm0.h</strong> / <strong>core_cm3.h</strong> defines as a minimum: |
| 487 | </p> |
| 488 | <ul> |
| 489 | <li>The <strong>Register Layout Typedef</strong> for each peripheral that defines all register names. |
| 490 | Names that start with RESERVE are used to introduce space into the structure to adjust the addresses of |
| 491 | the peripheral registers. For example: |
| 492 | <pre> |
| 493 | typedef struct { |
| 494 | __IO uint32_t CTRL; /* SysTick Control and Status Register */ |
| 495 | __IO uint32_t LOAD; /* SysTick Reload Value Register */ |
| 496 | __IO uint32_t VAL; /* SysTick Current Value Register */ |
| 497 | __I uint32_t CALIB; /* SysTick Calibration Register */ |
| 498 | } SysTick_Type;</pre> |
| 499 | </li> |
| 500 | |
| 501 | <li> |
| 502 | <strong>Base Address</strong> for each peripheral (in case of multiple peripherals |
| 503 | that use the same <strong>register layout typedef</strong> multiple base addresses are defined). For example: |
| 504 | <pre> |
| 505 | #define SysTick_BASE (SCS_BASE + 0x0010) /* SysTick Base Address */</pre> |
| 506 | </li> |
| 507 | |
| 508 | <li> |
| 509 | <strong>Access Definition</strong> for each peripheral (in case of multiple peripherals that use |
| 510 | the same <strong>register layout typedef</strong> multiple access definitions exist, i.e. LPC_UART0, |
| 511 | LPC_UART2). For Example: |
| 512 | <pre> |
| 513 | #define SysTick ((SysTick_Type *) SysTick_BASE) /* SysTick access definition */</pre> |
| 514 | </li> |
| 515 | </ul> |
| 516 | |
| 517 | <p> |
| 518 | These definitions allow to access the peripheral registers from user code with simple assignments like: |
| 519 | </p> |
| 520 | <pre>SysTick->CTRL = 0;</pre> |
| 521 | |
| 522 | <h5>Optional Features</h5> |
| 523 | <p>In addition the <em> <strong>device.h </strong></em>file may define:</p> |
| 524 | <ul> |
| 525 | <li> |
| 526 | #define constants that simplify access to the peripheral registers. |
| 527 | These constant define bit-positions or other specific patterns are that required for the |
| 528 | programming of the peripheral registers. The identifiers used start with |
| 529 | <strong><device abbreviation>_</strong> and <strong><peripheral name>_</strong>. |
| 530 | It is recommended to use CAPITAL letters for such #define constants. |
| 531 | </li> |
| 532 | <li> |
| 533 | Functions that perform more complex functions with the peripheral (i.e. status query before |
| 534 | a sending register is accessed). Again these function start with |
| 535 | <strong><device abbreviation>_</strong> and <strong><peripheral name>_</strong>. |
| 536 | </li> |
| 537 | </ul> |
| 538 | |
| 539 | <h3>core_cm0.h and core_cm0.c</h3> |
| 540 | <p> |
| 541 | File <b>core_cm0.h</b> describes the data structures for the Cortex-M0 core peripherals and does |
| 542 | the address mapping of this structures. It also provides basic access to the Cortex-M0 core registers |
| 543 | and core peripherals with efficient functions (defined as <strong>static inline</strong>). |
| 544 | </p> |
| 545 | <p> |
| 546 | File <b>core_cm0.c</b> defines several helper functions that access processor registers. |
| 547 | </p> |
| 548 | <p>Together these files implement the <a href="#4">Core Peripheral Access Layer</a> for a Cortex-M0.</p> |
| 549 | |
| 550 | <h3>core_cm3.h and core_cm3.c</h3> |
| 551 | <p> |
| 552 | File <b>core_cm3.h</b> describes the data structures for the Cortex-M3 core peripherals and does |
| 553 | the address mapping of this structures. It also provides basic access to the Cortex-M3 core registers |
| 554 | and core peripherals with efficient functions (defined as <strong>static inline</strong>). |
| 555 | </p> |
| 556 | <p> |
| 557 | File <b>core_cm3.c</b> defines several helper functions that access processor registers. |
| 558 | </p> |
| 559 | <p>Together these files implement the <a href="#4">Core Peripheral Access Layer</a> for a Cortex-M3.</p> |
| 560 | |
| 561 | <h3>startup_<em>device</em></h3> |
| 562 | <p> |
| 563 | A template file for <strong>startup_<em>device</em></strong> is provided by ARM for each supported |
| 564 | compiler. It is adapted by the silicon vendor to include interrupt vectors for all device specific |
| 565 | interrupt handlers. Each interrupt handler is defined as <strong><em>weak</em></strong> function |
| 566 | to an dummy handler. Therefore the interrupt handler can be directly used in application software |
| 567 | without any requirements to adapt the <strong>startup_<em>device</em></strong> file. |
| 568 | </p> |
| 569 | <p> |
| 570 | The following exception names are fixed and define the start of the vector table for a Cortex-M0: |
| 571 | </p> |
| 572 | <pre> |
| 573 | __Vectors DCD __initial_sp ; Top of Stack |
| 574 | DCD Reset_Handler ; Reset Handler |
| 575 | DCD NMI_Handler ; NMI Handler |
| 576 | DCD HardFault_Handler ; Hard Fault Handler |
| 577 | DCD 0 ; Reserved |
| 578 | DCD 0 ; Reserved |
| 579 | DCD 0 ; Reserved |
| 580 | DCD 0 ; Reserved |
| 581 | DCD 0 ; Reserved |
| 582 | DCD 0 ; Reserved |
| 583 | DCD 0 ; Reserved |
| 584 | DCD SVC_Handler ; SVCall Handler |
| 585 | DCD 0 ; Reserved |
| 586 | DCD 0 ; Reserved |
| 587 | DCD PendSV_Handler ; PendSV Handler |
| 588 | DCD SysTick_Handler ; SysTick Handler</pre> |
| 589 | |
| 590 | <p> |
| 591 | The following exception names are fixed and define the start of the vector table for a Cortex-M3: |
| 592 | </p> |
| 593 | <pre> |
| 594 | __Vectors DCD __initial_sp ; Top of Stack |
| 595 | DCD Reset_Handler ; Reset Handler |
| 596 | DCD NMI_Handler ; NMI Handler |
| 597 | DCD HardFault_Handler ; Hard Fault Handler |
| 598 | DCD MemManage_Handler ; MPU Fault Handler |
| 599 | DCD BusFault_Handler ; Bus Fault Handler |
| 600 | DCD UsageFault_Handler ; Usage Fault Handler |
| 601 | DCD 0 ; Reserved |
| 602 | DCD 0 ; Reserved |
| 603 | DCD 0 ; Reserved |
| 604 | DCD 0 ; Reserved |
| 605 | DCD SVC_Handler ; SVCall Handler |
| 606 | DCD DebugMon_Handler ; Debug Monitor Handler |
| 607 | DCD 0 ; Reserved |
| 608 | DCD PendSV_Handler ; PendSV Handler |
| 609 | DCD SysTick_Handler ; SysTick Handler</pre> |
| 610 | |
| 611 | <p> |
| 612 | In the following examples for device specific interrupts are shown: |
| 613 | </p> |
| 614 | <pre> |
| 615 | ; External Interrupts |
| 616 | DCD WWDG_IRQHandler ; Window Watchdog |
| 617 | DCD PVD_IRQHandler ; PVD through EXTI Line detect |
| 618 | DCD TAMPER_IRQHandler ; Tamper</pre> |
| 619 | |
| 620 | <p> |
| 621 | Device specific interrupts must have a dummy function that can be overwritten in user code. |
| 622 | Below is an example for this dummy function. |
| 623 | </p> |
| 624 | <pre> |
| 625 | Default_Handler PROC |
| 626 | EXPORT WWDG_IRQHandler [WEAK] |
| 627 | EXPORT PVD_IRQHandler [WEAK] |
| 628 | EXPORT TAMPER_IRQHandler [WEAK] |
| 629 | : |
| 630 | : |
| 631 | WWDG_IRQHandler |
| 632 | PVD_IRQHandler |
| 633 | TAMPER_IRQHandler |
| 634 | : |
| 635 | : |
| 636 | B . |
| 637 | ENDP</pre> |
| 638 | |
| 639 | <p> |
| 640 | The user application may simply define an interrupt handler function by using the handler name |
| 641 | as shown below. |
| 642 | </p> |
| 643 | <pre> |
| 644 | void WWDG_IRQHandler(void) |
| 645 | { |
| 646 | : |
| 647 | : |
| 648 | }</pre> |
| 649 | |
| 650 | |
| 651 | <h3><a name="4"></a>system_<em>device</em>.c</h3> |
| 652 | <p> |
| 653 | A template file for <strong>system_<em>device</em>.c</strong> is provided by ARM but adapted by |
| 654 | the silicon vendor to match their actual device. As a <strong>minimum requirement</strong> |
| 655 | this file must provide a device specific system configuration function and a global variable |
| 656 | that contains the system frequency. It configures the device and initializes typically the |
| 657 | oscillator (PLL) that is part of the microcontroller device. |
| 658 | </p> |
| 659 | <p> |
| 660 | The file <strong>system_</strong><em><strong>device</strong></em><strong>.c</strong> must provide |
| 661 | as a minimum requirement the SystemInit function as shown below. |
| 662 | </p> |
| 663 | |
| 664 | <table class="kt" border="0" cellpadding="0" cellspacing="0"> |
| 665 | <tbody> |
| 666 | <tr> |
| 667 | <th class="kt">Function Definition</th> |
| 668 | <th class="kt">Description</th> |
| 669 | </tr> |
| 670 | <tr> |
| 671 | <td class="kt" nowrap="nowrap">void SystemInit (void)</td> |
| 672 | <td class="kt">Setup the microcontroller system. Typically this function configures the |
| 673 | oscillator (PLL) that is part of the microcontroller device. For systems |
| 674 | with variable clock speed it also updates the variable SystemCoreClock.<br> |
| 675 | SystemInit is called from startup<i>_device</i> file.</td> |
| 676 | </tr> |
| 677 | <tr> |
| 678 | <td class="kt" nowrap="nowrap">void SystemCoreClockUpdate (void)</td> |
| 679 | <td class="kt">Updates the variable SystemCoreClock and must be called whenever the |
| 680 | core clock is changed during program execution. SystemCoreClockUpdate() |
| 681 | evaluates the clock register settings and calculates the current core clock. |
| 682 | </td> |
| 683 | </tr> |
| 684 | </tbody> |
| 685 | </table> |
| 686 | |
| 687 | <p> |
| 688 | Also part of the file <strong>system_</strong><em><strong>device</strong></em><strong>.c</strong> |
| 689 | is the variable <strong>SystemCoreClock</strong> which contains the current CPU clock speed shown below. |
| 690 | </p> |
| 691 | |
| 692 | <table class="kt" border="0" cellpadding="0" cellspacing="0"> |
| 693 | <tbody> |
| 694 | <tr> |
| 695 | <th class="kt">Variable Definition</th> |
| 696 | <th class="kt">Description</th> |
| 697 | </tr> |
| 698 | <tr> |
| 699 | <td class="kt" nowrap="nowrap">uint32_t SystemCoreClock</td> |
| 700 | <td class="kt">Contains the system core clock (which is the system clock frequency supplied |
| 701 | to the SysTick timer and the processor core clock). This variable can be |
| 702 | used by the user application to setup the SysTick timer or configure other |
| 703 | parameters. It may also be used by debugger to query the frequency of the |
| 704 | debug timer or configure the trace clock speed.<br> |
| 705 | SystemCoreClock is initialized with a correct predefined value.<br><br> |
| 706 | The compiler must be configured to avoid the removal of this variable in |
| 707 | case that the application program is not using it. It is important for |
| 708 | debug systems that the variable is physically present in memory so that |
| 709 | it can be examined to configure the debugger.</td> |
| 710 | </tr> |
| 711 | </tbody> |
| 712 | </table> |
| 713 | |
| 714 | <p class="Note">Note</p> |
| 715 | <ul> |
| 716 | <li><p>The above definitions are the minimum requirements for the file <strong> |
| 717 | system_</strong><em><strong>device</strong></em><strong>.c</strong>. This |
| 718 | file may export more functions or variables that provide a more flexible |
| 719 | configuration of the microcontroller system.</p> |
| 720 | </li> |
| 721 | </ul> |
| 722 | |
| 723 | |
| 724 | <h2>Core Peripheral Access Layer</h2> |
| 725 | |
| 726 | <h3>Cortex-M Core Register Access</h3> |
| 727 | <p> |
| 728 | The following functions are defined in <strong>core_cm0.h</strong> / <strong>core_cm3.h</strong> |
| 729 | and provide access to Cortex-M core registers. |
| 730 | </p> |
| 731 | |
| 732 | <table class="kt" border="0" cellpadding="0" cellspacing="0"> |
| 733 | <tbody> |
| 734 | <tr> |
| 735 | <th class="kt">Function Definition</th> |
| 736 | <th class="kt">Core</th> |
| 737 | <th class="kt">Core Register</th> |
| 738 | <th class="kt">Description</th> |
| 739 | </tr> |
| 740 | <tr> |
| 741 | <td class="kt" nowrap="nowrap">void __enable_irq (void)</td> |
| 742 | <td class="kt">M0, M3</td> |
| 743 | <td class="kt">PRIMASK = 0</td> |
| 744 | <td class="kt">Global Interrupt enable (using the instruction <strong>CPSIE |
| 745 | i</strong>)</td> |
| 746 | </tr> |
| 747 | <tr> |
| 748 | <td class="kt" nowrap="nowrap">void __disable_irq (void)</td> |
| 749 | <td class="kt">M0, M3</td> |
| 750 | <td class="kt">PRIMASK = 1</td> |
| 751 | <td class="kt">Global Interrupt disable (using the instruction <strong> |
| 752 | CPSID i</strong>)</td> |
| 753 | </tr> |
| 754 | <tr> |
| 755 | <td class="kt" nowrap="nowrap">void __set_PRIMASK (uint32_t value)</td> |
| 756 | <td class="kt">M0, M3</td> |
| 757 | <td class="kt">PRIMASK = value</td> |
| 758 | <td class="kt">Assign value to Priority Mask Register (using the instruction |
| 759 | <strong>MSR</strong>)</td> |
| 760 | </tr> |
| 761 | <tr> |
| 762 | <td class="kt" nowrap="nowrap">uint32_t __get_PRIMASK (void)</td> |
| 763 | <td class="kt">M0, M3</td> |
| 764 | <td class="kt">return PRIMASK</td> |
| 765 | <td class="kt">Return Priority Mask Register (using the instruction |
| 766 | <strong>MRS</strong>)</td> |
| 767 | </tr> |
| 768 | <tr> |
| 769 | <td class="kt" nowrap="nowrap">void __enable_fault_irq (void)</td> |
| 770 | <td class="kt">M3</td> |
| 771 | <td class="kt">FAULTMASK = 0</td> |
| 772 | <td class="kt">Global Fault exception and Interrupt enable (using the |
| 773 | instruction <strong>CPSIE |
| 774 | f</strong>)</td> |
| 775 | </tr> |
| 776 | <tr> |
| 777 | <td class="kt" nowrap="nowrap">void __disable_fault_irq (void)</td> |
| 778 | <td class="kt">M3</td> |
| 779 | <td class="kt">FAULTMASK = 1</td> |
| 780 | <td class="kt">Global Fault exception and Interrupt disable (using the |
| 781 | instruction <strong>CPSID f</strong>)</td> |
| 782 | </tr> |
| 783 | <tr> |
| 784 | <td class="kt" nowrap="nowrap">void __set_FAULTMASK (uint32_t value)</td> |
| 785 | <td class="kt">M3</td> |
| 786 | <td class="kt">FAULTMASK = value</td> |
| 787 | <td class="kt">Assign value to Fault Mask Register (using the instruction |
| 788 | <strong>MSR</strong>)</td> |
| 789 | </tr> |
| 790 | <tr> |
| 791 | <td class="kt" nowrap="nowrap">uint32_t __get_FAULTMASK (void)</td> |
| 792 | <td class="kt">M3</td> |
| 793 | <td class="kt">return FAULTMASK</td> |
| 794 | <td class="kt">Return Fault Mask Register (using the instruction <strong>MRS</strong>)</td> |
| 795 | </tr> |
| 796 | <tr> |
| 797 | <td class="kt" nowrap="nowrap">void __set_BASEPRI (uint32_t value)</td> |
| 798 | <td class="kt">M3</td> |
| 799 | <td class="kt">BASEPRI = value</td> |
| 800 | <td class="kt">Set Base Priority (using the instruction <strong>MSR</strong>)</td> |
| 801 | </tr> |
| 802 | <tr> |
| 803 | <td class="kt" nowrap="nowrap">uiuint32_t __get_BASEPRI (void)</td> |
| 804 | <td class="kt">M3</td> |
| 805 | <td class="kt">return BASEPRI</td> |
| 806 | <td class="kt">Return Base Priority (using the instruction <strong>MRS</strong>)</td> |
| 807 | </tr> |
| 808 | <tr> |
| 809 | <td class="kt" nowrap="nowrap">void __set_CONTROL (uint32_t value)</td> |
| 810 | <td class="kt">M0, M3</td> |
| 811 | <td class="kt">CONTROL = value</td> |
| 812 | <td class="kt">Set CONTROL register value (using the instruction <strong>MSR</strong>)</td> |
| 813 | </tr> |
| 814 | <tr> |
| 815 | <td class="kt" nowrap="nowrap">uint32_t __get_CONTROL (void)</td> |
| 816 | <td class="kt">M0, M3</td> |
| 817 | <td class="kt">return CONTROL</td> |
| 818 | <td class="kt">Return Control Register Value (using the instruction |
| 819 | <strong>MRS</strong>)</td> |
| 820 | </tr> |
| 821 | <tr> |
| 822 | <td class="kt" nowrap="nowrap">void __set_PSP (uint32_t TopOfProcStack)</td> |
| 823 | <td class="kt">M0, M3</td> |
| 824 | <td class="kt">PSP = TopOfProcStack</td> |
| 825 | <td class="kt">Set Process Stack Pointer value (using the instruction |
| 826 | <strong>MSR</strong>)</td> |
| 827 | </tr> |
| 828 | <tr> |
| 829 | <td class="kt" nowrap="nowrap">uint32_t __get_PSP (void)</td> |
| 830 | <td class="kt">M0, M3</td> |
| 831 | <td class="kt">return PSP</td> |
| 832 | <td class="kt">Return Process Stack Pointer (using the instruction <strong>MRS</strong>)</td> |
| 833 | </tr> |
| 834 | <tr> |
| 835 | <td class="kt" nowrap="nowrap">void __set_MSP (uint32_t TopOfMainStack)</td> |
| 836 | <td class="kt">M0, M3</td> |
| 837 | <td class="kt">MSP = TopOfMainStack</td> |
| 838 | <td class="kt">Set Main Stack Pointer (using the instruction <strong>MSR</strong>)</td> |
| 839 | </tr> |
| 840 | <tr> |
| 841 | <td class="kt" nowrap="nowrap">uint32_t __get_MSP (void)</td> |
| 842 | <td class="kt">M0, M3</td> |
| 843 | <td class="kt">return MSP</td> |
| 844 | <td class="kt">Return Main Stack Pointer (using the instruction <strong>MRS</strong>)</td> |
| 845 | </tr> |
| 846 | </tbody> |
| 847 | </table> |
| 848 | |
| 849 | <h3>Cortex-M Instruction Access</h3> |
| 850 | <p> |
| 851 | The following functions are defined in <strong>core_cm0.h</strong> / <strong>core_cm3.h</strong>and |
| 852 | generate specific Cortex-M instructions. The functions are implemented in the file |
| 853 | <strong>core_cm0.c</strong> / <strong>core_cm3.c</strong>. |
| 854 | </p> |
| 855 | |
| 856 | <table class="kt" border="0" cellpadding="0" cellspacing="0"> |
| 857 | <tbody> |
| 858 | <tr> |
| 859 | <th class="kt">Name</th> |
| 860 | <th class="kt">Core</th> |
| 861 | <th class="kt">Generated CPU Instruction</th> |
| 862 | <th class="kt">Description</th> |
| 863 | </tr> |
| 864 | <tr> |
| 865 | <td class="kt" nowrap="nowrap">void __NOP (void)</td> |
| 866 | <td class="kt">M0, M3</td> |
| 867 | <td class="kt">NOP</td> |
| 868 | <td class="kt">No Operation</td> |
| 869 | </tr> |
| 870 | <tr> |
| 871 | <td class="kt" nowrap="nowrap">void __WFI (void)</td> |
| 872 | <td class="kt">M0, M3</td> |
| 873 | <td class="kt">WFI</td> |
| 874 | <td class="kt">Wait for Interrupt</td> |
| 875 | </tr> |
| 876 | <tr> |
| 877 | <td class="kt" nowrap="nowrap">void __WFE (void)</td> |
| 878 | <td class="kt">M0, M3</td> |
| 879 | <td class="kt">WFE</td> |
| 880 | <td class="kt">Wait for Event</td> |
| 881 | </tr> |
| 882 | <tr> |
| 883 | <td class="kt" nowrap="nowrap">void __SEV (void)</td> |
| 884 | <td class="kt">M0, M3</td> |
| 885 | <td class="kt">SEV</td> |
| 886 | <td class="kt">Set Event</td> |
| 887 | </tr> |
| 888 | <tr> |
| 889 | <td class="kt" nowrap="nowrap">void __ISB (void)</td> |
| 890 | <td class="kt">M0, M3</td> |
| 891 | <td class="kt">ISB</td> |
| 892 | <td class="kt">Instruction Synchronization Barrier</td> |
| 893 | </tr> |
| 894 | <tr> |
| 895 | <td class="kt" nowrap="nowrap">void __DSB (void)</td> |
| 896 | <td class="kt">M0, M3</td> |
| 897 | <td class="kt">DSB</td> |
| 898 | <td class="kt">Data Synchronization Barrier</td> |
| 899 | </tr> |
| 900 | <tr> |
| 901 | <td class="kt" nowrap="nowrap">void __DMB (void)</td> |
| 902 | <td class="kt">M0, M3</td> |
| 903 | <td class="kt">DMB</td> |
| 904 | <td class="kt">Data Memory Barrier</td> |
| 905 | </tr> |
| 906 | <tr> |
| 907 | <td class="kt" nowrap="nowrap">uint32_t __REV (uint32_t value)</td> |
| 908 | <td class="kt">M0, M3</td> |
| 909 | <td class="kt">REV</td> |
| 910 | <td class="kt">Reverse byte order in integer value.</td> |
| 911 | </tr> |
| 912 | <tr> |
| 913 | <td class="kt" nowrap="nowrap">uint32_t __REV16 (uint16_t value)</td> |
| 914 | <td class="kt">M0, M3</td> |
| 915 | <td class="kt">REV16</td> |
| 916 | <td class="kt">Reverse byte order in unsigned short value. </td> |
| 917 | </tr> |
| 918 | <tr> |
| 919 | <td class="kt" nowrap="nowrap">sint32_t __REVSH (sint16_t value)</td> |
| 920 | <td class="kt">M0, M3</td> |
| 921 | <td class="kt">REVSH</td> |
| 922 | <td class="kt">Reverse byte order in signed short value with sign extension to integer.</td> |
| 923 | </tr> |
| 924 | <tr> |
| 925 | <td class="kt" nowrap="nowrap">uint32_t __RBIT (uint32_t value)</td> |
| 926 | <td class="kt">M3</td> |
| 927 | <td class="kt">RBIT</td> |
| 928 | <td class="kt">Reverse bit order of value</td> |
| 929 | </tr> |
| 930 | <tr> |
| 931 | <td class="kt" nowrap="nowrap">uint8_t __LDREXB (uint8_t *addr)</td> |
| 932 | <td class="kt">M3</td> |
| 933 | <td class="kt">LDREXB</td> |
| 934 | <td class="kt">Load exclusive byte</td> |
| 935 | </tr> |
| 936 | <tr> |
| 937 | <td class="kt" nowrap="nowrap">uint16_t __LDREXH (uint16_t *addr)</td> |
| 938 | <td class="kt">M3</td> |
| 939 | <td class="kt">LDREXH</td> |
| 940 | <td class="kt">Load exclusive half-word</td> |
| 941 | </tr> |
| 942 | <tr> |
| 943 | <td class="kt" nowrap="nowrap">uint32_t __LDREXW (uint32_t *addr)</td> |
| 944 | <td class="kt">M3</td> |
| 945 | <td class="kt">LDREXW</td> |
| 946 | <td class="kt">Load exclusive word</td> |
| 947 | </tr> |
| 948 | <tr> |
| 949 | <td class="kt" nowrap="nowrap">uint32_t __STREXB (uint8_t value, uint8_t *addr)</td> |
| 950 | <td class="kt">M3</td> |
| 951 | <td class="kt">STREXB</td> |
| 952 | <td class="kt">Store exclusive byte</td> |
| 953 | </tr> |
| 954 | <tr> |
| 955 | <td class="kt" nowrap="nowrap">uint32_t __STREXB (uint16_t value, uint16_t *addr)</td> |
| 956 | <td class="kt">M3</td> |
| 957 | <td class="kt">STREXH</td> |
| 958 | <td class="kt">Store exclusive half-word</td> |
| 959 | </tr> |
| 960 | <tr> |
| 961 | <td class="kt" nowrap="nowrap">uint32_t __STREXB (uint32_t value, uint32_t *addr)</td> |
| 962 | <td class="kt">M3</td> |
| 963 | <td class="kt">STREXW</td> |
| 964 | <td class="kt">Store exclusive word</td> |
| 965 | </tr> |
| 966 | <tr> |
| 967 | <td class="kt" nowrap="nowrap">void __CLREX (void)</td> |
| 968 | <td class="kt">M3</td> |
| 969 | <td class="kt">CLREX</td> |
| 970 | <td class="kt">Remove the exclusive lock created by __LDREXB, __LDREXH, or __LDREXW</td> |
| 971 | </tr> |
| 972 | </tbody> |
| 973 | </table> |
| 974 | |
| 975 | |
| 976 | <h3>NVIC Access Functions</h3> |
| 977 | <p> |
| 978 | The CMSIS provides access to the NVIC via the register interface structure and several helper |
| 979 | functions that simplify the setup of the NVIC. The CMSIS HAL uses IRQ numbers (IRQn) to |
| 980 | identify the interrupts. The first device interrupt has the IRQn value 0. Therefore negative |
| 981 | IRQn values are used for processor core exceptions. |
| 982 | </p> |
| 983 | <p> |
| 984 | For the IRQn values of core exceptions the file <strong><em>device.h</em></strong> provides |
| 985 | the following enum names. |
| 986 | </p> |
| 987 | |
| 988 | <table class="kt" border="0" cellpadding="0" cellspacing="0"> |
| 989 | <tbody> |
| 990 | <tr> |
| 991 | <th class="kt" nowrap="nowrap">Core Exception enum Value</th> |
| 992 | <th class="kt">Core</th> |
| 993 | <th class="kt">IRQn</th> |
| 994 | <th class="kt">Description</th> |
| 995 | </tr> |
| 996 | <tr> |
| 997 | <td class="kt" nowrap="nowrap">NonMaskableInt_IRQn</td> |
| 998 | <td class="kt">M0, M3</td> |
| 999 | <td class="kt">-14</td> |
| 1000 | <td class="kt">Cortex-M Non Maskable Interrupt</td> |
| 1001 | </tr> |
| 1002 | <tr> |
| 1003 | <td class="kt" nowrap="nowrap">HardFault_IRQn</td> |
| 1004 | <td class="kt">M0, M3</td> |
| 1005 | <td class="kt">-13</td> |
| 1006 | <td class="kt">Cortex-M Hard Fault Interrupt</td> |
| 1007 | </tr> |
| 1008 | <tr> |
| 1009 | <td class="kt" nowrap="nowrap">MemoryManagement_IRQn</td> |
| 1010 | <td class="kt">M3</td> |
| 1011 | <td class="kt">-12</td> |
| 1012 | <td class="kt">Cortex-M Memory Management Interrupt</td> |
| 1013 | </tr> |
| 1014 | <tr> |
| 1015 | <td class="kt" nowrap="nowrap">BusFault_IRQn</td> |
| 1016 | <td class="kt">M3</td> |
| 1017 | <td class="kt">-11</td> |
| 1018 | <td class="kt">Cortex-M Bus Fault Interrupt</td> |
| 1019 | </tr> |
| 1020 | <tr> |
| 1021 | <td class="kt" nowrap="nowrap">UsageFault_IRQn</td> |
| 1022 | <td class="kt">M3</td> |
| 1023 | <td class="kt">-10</td> |
| 1024 | <td class="kt">Cortex-M Usage Fault Interrupt</td> |
| 1025 | </tr> |
| 1026 | <tr> |
| 1027 | <td class="kt" nowrap="nowrap">SVCall_IRQn</td> |
| 1028 | <td class="kt">M0, M3</td> |
| 1029 | <td class="kt">-5</td> |
| 1030 | <td class="kt">Cortex-M SV Call Interrupt </td> |
| 1031 | </tr> |
| 1032 | <tr> |
| 1033 | <td class="kt" nowrap="nowrap">DebugMonitor_IRQn</td> |
| 1034 | <td class="kt">M3</td> |
| 1035 | <td class="kt">-4</td> |
| 1036 | <td class="kt">Cortex-M Debug Monitor Interrupt</td> |
| 1037 | </tr> |
| 1038 | <tr> |
| 1039 | <td class="kt" nowrap="nowrap">PendSV_IRQn</td> |
| 1040 | <td class="kt">M0, M3</td> |
| 1041 | <td class="kt">-2</td> |
| 1042 | <td class="kt">Cortex-M Pend SV Interrupt</td> |
| 1043 | </tr> |
| 1044 | <tr> |
| 1045 | <td class="kt" nowrap="nowrap">SysTick_IRQn</td> |
| 1046 | <td class="kt">M0, M3</td> |
| 1047 | <td class="kt">-1</td> |
| 1048 | <td class="kt">Cortex-M System Tick Interrupt</td> |
| 1049 | </tr> |
| 1050 | </tbody> |
| 1051 | </table> |
| 1052 | |
| 1053 | <p>The following functions simplify the setup of the NVIC. |
| 1054 | The functions are defined as <strong>static inline</strong>.</p> |
| 1055 | |
| 1056 | <table class="kt" border="0" cellpadding="0" cellspacing="0"> |
| 1057 | <tbody> |
| 1058 | <tr> |
| 1059 | <th class="kt" nowrap="nowrap">Name</th> |
| 1060 | <th class="kt">Core</th> |
| 1061 | <th class="kt">Parameter</th> |
| 1062 | <th class="kt">Description</th> |
| 1063 | </tr> |
| 1064 | <tr> |
| 1065 | <td class="kt" nowrap="nowrap">void NVIC_SetPriorityGrouping (uint32_t PriorityGroup)</td> |
| 1066 | <td class="kt">M3</td> |
| 1067 | <td class="kt">Priority Grouping Value</td> |
| 1068 | <td class="kt">Set the Priority Grouping (Groups . Subgroups)</td> |
| 1069 | </tr> |
| 1070 | <tr> |
| 1071 | <td class="kt" nowrap="nowrap">uint32_t NVIC_GetPriorityGrouping (void)</td> |
| 1072 | <td class="kt">M3</td> |
| 1073 | <td class="kt">(void)</td> |
| 1074 | <td class="kt">Get the Priority Grouping (Groups . Subgroups)</td> |
| 1075 | </tr> |
| 1076 | <tr> |
| 1077 | <td class="kt" nowrap="nowrap">void NVIC_EnableIRQ (IRQn_Type IRQn)</td> |
| 1078 | <td class="kt">M0, M3</td> |
| 1079 | <td class="kt">IRQ Number</td> |
| 1080 | <td class="kt">Enable IRQn</td> |
| 1081 | </tr> |
| 1082 | <tr> |
| 1083 | <td class="kt" nowrap="nowrap">void NVIC_DisableIRQ (IRQn_Type IRQn)</td> |
| 1084 | <td class="kt">M0, M3</td> |
| 1085 | <td class="kt">IRQ Number</td> |
| 1086 | <td class="kt">Disable IRQn</td> |
| 1087 | </tr> |
| 1088 | <tr> |
| 1089 | <td class="kt" nowrap="nowrap">uint32_t NVIC_GetPendingIRQ (IRQn_Type IRQn)</td> |
| 1090 | <td class="kt">M0, M3</td> |
| 1091 | <td class="kt">IRQ Number</td> |
| 1092 | <td class="kt">Return 1 if IRQn is pending else 0</td> |
| 1093 | </tr> |
| 1094 | <tr> |
| 1095 | <td class="kt" nowrap="nowrap">void NVIC_SetPendingIRQ (IRQn_Type IRQn)</td> |
| 1096 | <td class="kt">M0, M3</td> |
| 1097 | <td class="kt">IRQ Number</td> |
| 1098 | <td class="kt">Set IRQn Pending</td> |
| 1099 | </tr> |
| 1100 | <tr> |
| 1101 | <td class="kt" nowrap="nowrap">void NVIC_ClearPendingIRQ (IRQn_Type IRQn)</td> |
| 1102 | <td class="kt">M0, M3</td> |
| 1103 | <td class="kt">IRQ Number</td> |
| 1104 | <td class="kt">Clear IRQn Pending Status</td> |
| 1105 | </tr> |
| 1106 | <tr> |
| 1107 | <td class="kt" nowrap="nowrap">uint32_t NVIC_GetActive (IRQn_Type IRQn)</td> |
| 1108 | <td class="kt">M3</td> |
| 1109 | <td class="kt">IRQ Number</td> |
| 1110 | <td class="kt">Return 1 if IRQn is active else 0</td> |
| 1111 | </tr> |
| 1112 | <tr> |
| 1113 | <td class="kt" nowrap="nowrap">void NVIC_SetPriority (IRQn_Type IRQn, uint32_t priority)</td> |
| 1114 | <td class="kt">M0, M3</td> |
| 1115 | <td class="kt">IRQ Number, Priority</td> |
| 1116 | <td class="kt">Set Priority for IRQn<br> |
| 1117 | (not threadsafe for Cortex-M0)</td> |
| 1118 | </tr> |
| 1119 | <tr> |
| 1120 | <td class="kt" nowrap="nowrap">uint32_t NVIC_GetPriority (IRQn_Type IRQn)</td> |
| 1121 | <td class="kt">M0, M3</td> |
| 1122 | <td class="kt">IRQ Number</td> |
| 1123 | <td class="kt">Get Priority for IRQn</td> |
| 1124 | </tr> |
| 1125 | <tr> |
| 1126 | <!-- <td class="kt" nowrap="nowrap">uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)</td> --> |
| 1127 | <td class="kt">uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)</td> |
| 1128 | <td class="kt">M3</td> |
| 1129 | <td class="kt">IRQ Number, Priority Group, Preemptive Priority, Sub Priority</td> |
| 1130 | <td class="kt">Encode priority for given group, preemptive and sub priority</td> |
| 1131 | </tr> |
| 1132 | <!-- <td class="kt" nowrap="nowrap">NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)</td> --> |
| 1133 | <td class="kt">NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)</td> |
| 1134 | <td class="kt">M3</td> |
| 1135 | <td class="kt">IRQ Number, Priority, pointer to Priority Group, pointer to Preemptive Priority, pointer to Sub Priority</td> |
| 1136 | <td class="kt">Deccode given priority to group, preemptive and sub priority</td> |
| 1137 | </tr> |
| 1138 | <tr> |
| 1139 | <td class="kt" nowrap="nowrap">void NVIC_SystemReset (void)</td> |
| 1140 | <td class="kt">M0, M3</td> |
| 1141 | <td class="kt">(void)</td> |
| 1142 | <td class="kt">Resets the System</td> |
| 1143 | </tr> |
| 1144 | </tbody> |
| 1145 | </table> |
| 1146 | <p class="Note">Note</p> |
| 1147 | <ul> |
| 1148 | <li><p>The processor exceptions have negative enum values. Device specific interrupts |
| 1149 | have positive enum values and start with 0. The values are defined in |
| 1150 | <b><em>device.h</em></b> file. |
| 1151 | </p> |
| 1152 | </li> |
| 1153 | <li><p>The values for <b>PreemptPriority</b> and <b>SubPriority</b> |
| 1154 | used in functions <b>NVIC_EncodePriority</b> and <b>NVIC_DecodePriority</b> |
| 1155 | depend on the available __NVIC_PRIO_BITS implemented in the NVIC. |
| 1156 | </p> |
| 1157 | </li> |
| 1158 | </ul> |
| 1159 | |
| 1160 | |
| 1161 | <h3>SysTick Configuration Function</h3> |
| 1162 | |
| 1163 | <p>The following function is used to configure the SysTick timer and start the |
| 1164 | SysTick interrupt.</p> |
| 1165 | |
| 1166 | <table class="kt" border="0" cellpadding="0" cellspacing="0"> |
| 1167 | <tbody> |
| 1168 | <tr> |
| 1169 | <th class="kt" nowrap="nowrap">Name</th> |
| 1170 | <th class="kt">Parameter</th> |
| 1171 | <th class="kt">Description</th> |
| 1172 | </tr> |
| 1173 | <tr> |
| 1174 | <td class="kt" nowrap="nowrap">uint32_t Sys<span class="style1">TickConfig |
| 1175 | (uint32_t ticks)</span></td> |
| 1176 | <td class="kt">ticks is SysTick counter reload value</td> |
| 1177 | <td class="kt">Setup the SysTick timer and enable the SysTick interrupt. After this |
| 1178 | call the SysTick timer creates interrupts with the specified time |
| 1179 | interval. <br> |
| 1180 | <br> |
| 1181 | Return: 0 when successful, 1 on failure.<br> |
| 1182 | </td> |
| 1183 | </tr> |
| 1184 | </tbody> |
| 1185 | </table> |
| 1186 | |
| 1187 | |
| 1188 | <h3>Cortex-M3 ITM Debug Access</h3> |
| 1189 | |
| 1190 | <p>The Cortex-M3 incorporates the Instrumented Trace Macrocell (ITM) that |
| 1191 | provides together with the Serial Viewer Output trace capabilities for the |
| 1192 | microcontroller system. The ITM has 32 communication channels; two ITM |
| 1193 | communication channels are used by CMSIS to output the following information:</p> |
| 1194 | <ul> |
| 1195 | <li>ITM Channel 0: implements the <strong>ITM_SendChar</strong> function |
| 1196 | which can be used for printf-style output via the debug interface.</li> |
| 1197 | <li>ITM Channel 31: is reserved for the RTOS kernel and can be used for |
| 1198 | kernel awareness debugging.</li> |
| 1199 | </ul> |
| 1200 | <p class="Note">Note</p> |
| 1201 | <ul> |
| 1202 | <li><p>The ITM channel 31 is selected for the RTOS kernel since some kernels |
| 1203 | may use the Privileged level for program execution. ITM |
| 1204 | channels have 4 groups with 8 channels each, whereby each group can be |
| 1205 | configured for access rights in the Unprivileged level. The ITM channel 0 |
| 1206 | may be therefore enabled for the user task whereas ITM channel 31 may be |
| 1207 | accessible only in Privileged level from the RTOS kernel itself.</p> |
| 1208 | </li> |
| 1209 | </ul> |
| 1210 | |
| 1211 | <p>The prototype of the <strong>ITM_SendChar</strong> routine is shown in the |
| 1212 | table below.</p> |
| 1213 | |
| 1214 | <table class="kt" border="0" cellpadding="0" cellspacing="0"> |
| 1215 | <tbody> |
| 1216 | <tr> |
| 1217 | <th class="kt" nowrap="nowrap">Name</th> |
| 1218 | <th class="kt">Parameter</th> |
| 1219 | <th class="kt">Description</th> |
| 1220 | </tr> |
| 1221 | <tr> |
| 1222 | <td class="kt" nowrap="nowrap">void uint32_t ITM_SendChar(uint32_t chr)</td> |
| 1223 | <td class="kt">character to output</td> |
| 1224 | <td class="kt">The function outputs a character via the ITM channel 0. The |
| 1225 | function returns when no debugger is connected that has booked the |
| 1226 | output. It is blocking when a debugger is connected, but the |
| 1227 | previous character send is not transmitted. <br><br> |
| 1228 | Return: the input character 'chr'.</td> |
| 1229 | </tr> |
| 1230 | </tbody> |
| 1231 | </table> |
| 1232 | |
| 1233 | <p> |
| 1234 | Example for the usage of the ITM Channel 31 for RTOS Kernels: |
| 1235 | </p> |
| 1236 | <pre> |
| 1237 | // check if debugger connected and ITM channel enabled for tracing |
| 1238 | if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) && |
| 1239 | (ITM->TCR & ITM_TCR_ITMENA) && |
| 1240 | (ITM->TER & (1UL << 31))) { |
| 1241 | // transmit trace data |
| 1242 | while (ITM->PORT31_U32 == 0); |
| 1243 | ITM->PORT[31].u8 = task_id; // id of next task |
| 1244 | while (ITM->PORT[31].u32 == 0); |
| 1245 | ITM->PORT[31].u32 = task_status; // status information |
| 1246 | }</pre> |
| 1247 | |
| 1248 | |
| 1249 | <h3>Cortex-M3 additional Debug Access</h3> |
| 1250 | |
| 1251 | <p>CMSIS provides additional debug functions to enlarge the Cortex-M3 Debug Access. |
| 1252 | Data can be transmitted via a certain global buffer variable towards the target system.</p> |
| 1253 | |
| 1254 | <p>The buffer variable and the prototypes of the additional functions are shown in the |
| 1255 | table below.</p> |
| 1256 | |
| 1257 | <table class="kt" border="0" cellpadding="0" cellspacing="0"> |
| 1258 | <tbody> |
| 1259 | <tr> |
| 1260 | <th class="kt" nowrap="nowrap">Name</th> |
| 1261 | <th class="kt">Parameter</th> |
| 1262 | <th class="kt">Description</th> |
| 1263 | </tr> |
| 1264 | <tr> |
| 1265 | <td class="kt" nowrap="nowrap">extern volatile int ITM_RxBuffer</td> |
| 1266 | <td class="kt"> </td> |
| 1267 | <td class="kt">Buffer to transmit data towards debug system. <br><br> |
| 1268 | Value 0x5AA55AA5 indicates that buffer is empty.</td> |
| 1269 | </tr> |
| 1270 | <tr> |
| 1271 | <td class="kt" nowrap="nowrap">int ITM_ReceiveChar (void)</td> |
| 1272 | <td class="kt">none</td> |
| 1273 | <td class="kt">The nonblocking functions returns the character stored in |
| 1274 | ITM_RxBuffer. <br><br> |
| 1275 | Return: -1 indicates that no character was received.</td> |
| 1276 | </tr> |
| 1277 | <tr> |
| 1278 | <td class="kt" nowrap="nowrap">int ITM_CheckChar (void)</td> |
| 1279 | <td class="kt">none</td> |
| 1280 | <td class="kt">The function checks if a character is available in ITM_RxBuffer. <br><br> |
| 1281 | Return: 1 indicates that a character is available, 0 indicates that |
| 1282 | no character is available.</td> |
| 1283 | </tr> |
| 1284 | </tbody> |
| 1285 | </table> |
| 1286 | |
| 1287 | |
| 1288 | <h2><a name="5"></a>CMSIS Example</h2> |
| 1289 | <p> |
| 1290 | The following section shows a typical example for using the CMSIS layer in user applications. |
| 1291 | The example is based on a STM32F10x Device. |
| 1292 | </p> |
| 1293 | <pre> |
| 1294 | #include "stm32f10x.h" |
| 1295 | |
| 1296 | volatile uint32_t msTicks; /* timeTicks counter */ |
| 1297 | |
| 1298 | void SysTick_Handler(void) { |
| 1299 | msTicks++; /* increment timeTicks counter */ |
| 1300 | } |
| 1301 | |
| 1302 | __INLINE static void Delay (uint32_t dlyTicks) { |
| 1303 | uint32_t curTicks = msTicks; |
| 1304 | |
| 1305 | while ((msTicks - curTicks) < dlyTicks); |
| 1306 | } |
| 1307 | |
| 1308 | __INLINE static void LED_Config(void) { |
| 1309 | ; /* Configure the LEDs */ |
| 1310 | } |
| 1311 | |
| 1312 | __INLINE static void LED_On (uint32_t led) { |
| 1313 | ; /* Turn On LED */ |
| 1314 | } |
| 1315 | |
| 1316 | __INLINE static void LED_Off (uint32_t led) { |
| 1317 | ; /* Turn Off LED */ |
| 1318 | } |
| 1319 | |
| 1320 | int main (void) { |
| 1321 | if (SysTick_Config (SystemCoreClock / 1000)) { /* Setup SysTick for 1 msec interrupts */ |
| 1322 | ; /* Handle Error */ |
| 1323 | while (1); |
| 1324 | } |
| 1325 | |
| 1326 | LED_Config(); /* configure the LEDs */ |
| 1327 | |
| 1328 | while(1) { |
| 1329 | LED_On (0x100); /* Turn on the LED */ |
| 1330 | Delay (100); /* delay 100 Msec */ |
| 1331 | LED_Off (0x100); /* Turn off the LED */ |
| 1332 | Delay (100); /* delay 100 Msec */ |
| 1333 | } |
| 1334 | }</pre> |
| 1335 | |
| 1336 | |
| 1337 | </body></html> |