Harald Welte | bb9b0dc | 2019-02-28 18:24:36 +0100 | [diff] [blame] | 1 | #include <stdint.h> |
| 2 | #include "utils.h" |
| 3 | #include "tc_etu.h" |
| 4 | #include "chip.h" |
| 5 | |
| 6 | |
| 7 | /* pins for Channel 0 of TC-block 0 */ |
| 8 | #define PIN_TIOA0 {PIO_PA0, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT} |
| 9 | |
| 10 | /* pins for Channel 1 of TC-block 0 */ |
| 11 | #define PIN_TIOA1 {PIO_PA15, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT} |
| 12 | #define PIN_TCLK1 {PIO_PA28, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT} |
| 13 | |
| 14 | static const Pin pins_tc[] = { PIN_TIOA0, PIN_TIOA1, PIN_TCLK1 }; |
| 15 | |
| 16 | static TcChannel *tc1 = &TC0->TC_CHANNEL[1]; |
| 17 | |
| 18 | void TC1_IrqHandler(void) |
| 19 | { |
| 20 | uint32_t sr = tc1->TC_SR; |
| 21 | printf("TC1=%lu; SR=0x%08lx\r\n", tc1->TC_RA, sr); |
| 22 | } |
| 23 | |
| 24 | void freq_ctr_init(void) |
| 25 | { |
| 26 | TcChannel *tc0 = &TC0->TC_CHANNEL[0]; |
| 27 | |
| 28 | PIO_Configure(pins_tc, ARRAY_SIZE(pins_tc)); |
| 29 | |
| 30 | PMC_EnablePeripheral(ID_TC0); |
| 31 | PMC_EnablePeripheral(ID_TC1); |
| 32 | |
| 33 | /* route TCLK1 to XC1 */ |
| 34 | TC0->TC_BMR &= ~TC_BMR_TC1XC1S_Msk; |
| 35 | TC0->TC_BMR |= TC_BMR_TC1XC1S_TCLK1; |
| 36 | |
| 37 | /* TC0 in wveform mode: Run from SCLK. Raise TIOA on RA; lower TIOA on RC + trigger */ |
| 38 | tc0->TC_CMR = TC_CMR_TCCLKS_TIMER_CLOCK5 | TC_CMR_BURST_NONE | |
| 39 | TC_CMR_EEVTEDG_NONE | TC_CMR_WAVSEL_UP_RC | TC_CMR_WAVE | |
| 40 | TC_CMR_ACPA_SET | TC_CMR_ACPC_CLEAR; |
| 41 | tc0->TC_RA = 16384; /* set high at 16384 */ |
| 42 | tc0->TC_RC = 32786; /* set low at 32786 */ |
| 43 | |
| 44 | /* TC1 in capture mode: Run from XC1. Trigger on TIOA rising. Load RA on rising */ |
| 45 | tc1->TC_CMR = TC_CMR_TCCLKS_XC1 | TC_CMR_BURST_NONE | |
| 46 | TC_CMR_ETRGEDG_RISING | TC_CMR_ABETRG | TC_CMR_LDRA_RISING; |
| 47 | /* Interrupt us if the external trigger happens */ |
| 48 | tc1->TC_IER = TC_IER_ETRGS; |
| 49 | NVIC_EnableIRQ(TC1_IRQn); |
| 50 | |
| 51 | TC0->TC_BCR = TC_BCR_SYNC; |
| 52 | |
| 53 | tc0->TC_CCR = TC_CCR_CLKEN|TC_CCR_SWTRG; |
| 54 | tc1->TC_CCR = TC_CCR_CLKEN|TC_CCR_SWTRG; |
| 55 | } |