Christina Quast | 53b2105 | 2014-12-09 15:34:35 +0100 | [diff] [blame] | 1 | /* ---------------------------------------------------------------------------- */ |
| 2 | /* Atmel Microcontroller Software Support */ |
| 3 | /* ---------------------------------------------------------------------------- */ |
| 4 | /* Copyright (c) 2010, Atmel Corporation */ |
| 5 | /* */ |
| 6 | /* All rights reserved. */ |
| 7 | /* */ |
| 8 | /* Redistribution and use in source and binary forms, with or without */ |
| 9 | /* modification, are permitted provided that the following condition is met: */ |
| 10 | /* */ |
| 11 | /* - Redistributions of source code must retain the above copyright notice, */ |
| 12 | /* this list of conditions and the disclaimer below. */ |
| 13 | /* */ |
| 14 | /* Atmel's name may not be used to endorse or promote products derived from */ |
| 15 | /* this software without specific prior written permission. */ |
| 16 | /* */ |
| 17 | /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ |
| 18 | /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ |
| 19 | /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ |
| 20 | /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ |
| 21 | /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ |
| 22 | /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ |
| 23 | /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ |
| 24 | /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ |
| 25 | /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ |
| 26 | /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ |
| 27 | /* ---------------------------------------------------------------------------- */ |
| 28 | /* */ |
| 29 | /* File Name : SAM3S.h */ |
| 30 | /* Object : SAM3S definitions */ |
| 31 | /* Generated by : AT91 SW Application Group */ |
| 32 | /* Generated on : 2010-09-06 */ |
| 33 | |
| 34 | #ifndef SAM3S_H |
| 35 | #define SAM3S_H |
| 36 | |
| 37 | /** \addtogroup SAM3S_definitions SAM3S definitions |
| 38 | This file defines all structures and symbols for SAM3S: |
| 39 | - registers and bitfields |
| 40 | - peripheral base address |
| 41 | - peripheral ID |
| 42 | - PIO definitions |
| 43 | */ |
| 44 | /*@{*/ |
| 45 | |
| 46 | #ifdef __cplusplus |
| 47 | extern "C" { |
| 48 | #endif |
| 49 | |
| 50 | #ifndef __ASSEMBLY__ |
| 51 | #include <stdint.h> |
| 52 | #ifndef __cplusplus |
| 53 | typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ |
| 54 | #else |
| 55 | typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ |
| 56 | #endif |
| 57 | typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ |
| 58 | typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ |
| 59 | #define CAST(type, value) ((type *) value) |
| 60 | #define REG_ACCESS(type, address) (*(type*)address) /**< C code: Register value */ |
| 61 | #else |
| 62 | #define CAST(type, value) (value) |
| 63 | #define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ |
| 64 | #endif |
| 65 | |
| 66 | /* ************************************************************************** */ |
| 67 | /* CMSIS DEFINITIONS FOR SAM3S */ |
| 68 | /* ************************************************************************** */ |
| 69 | /** \addtogroup SAM3S_cmsis CMSIS Definitions */ |
| 70 | /*@{*/ |
| 71 | |
| 72 | /**< Interrupt Number Definition */ |
| 73 | typedef enum IRQn |
| 74 | { |
| 75 | /****** Cortex-M3 Processor Exceptions Numbers ******************************/ |
| 76 | NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ |
| 77 | MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */ |
| 78 | BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */ |
| 79 | UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */ |
| 80 | SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */ |
| 81 | DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */ |
| 82 | PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */ |
| 83 | SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */ |
| 84 | /****** SAM3S specific Interrupt Numbers *********************************/ |
| 85 | |
| 86 | SUPC_IRQn = 0, /**< 0 SAM3S Supply Controller (SUPC) */ |
| 87 | RSTC_IRQn = 1, /**< 1 SAM3S Reset Controller (RSTC) */ |
| 88 | RTC_IRQn = 2, /**< 2 SAM3S Real Time Clock (RTC) */ |
| 89 | RTT_IRQn = 3, /**< 3 SAM3S Real Time Timer (RTT) */ |
| 90 | WDT_IRQn = 4, /**< 4 SAM3S Watchdog Timer (WDT) */ |
| 91 | PMC_IRQn = 5, /**< 5 SAM3S Power Management Controller (PMC) */ |
| 92 | EFC_IRQn = 6, /**< 6 SAM3S Enhanced Embedded Flash Controller (EFC) */ |
| 93 | UART0_IRQn = 8, /**< 8 SAM3S UART 0 (UART0) */ |
| 94 | UART1_IRQn = 9, /**< 9 SAM3S UART 1 (UART1) */ |
| 95 | SMC_IRQn = 10, /**< 10 SAM3S Static Memory Controller (SMC) */ |
| 96 | PIOA_IRQn = 11, /**< 11 SAM3S Parallel I/O Controller A (PIOA) */ |
| 97 | PIOB_IRQn = 12, /**< 12 SAM3S Parallel I/O Controller B (PIOB) */ |
| 98 | PIOC_IRQn = 13, /**< 13 SAM3S Parallel I/O Controller C (PIOC) */ |
| 99 | USART0_IRQn = 14, /**< 14 SAM3S USART 0 (USART0) */ |
| 100 | USART1_IRQn = 15, /**< 15 SAM3S USART 1 (USART1) */ |
| 101 | HSMCI_IRQn = 18, /**< 18 SAM3S Multimedia Card Interface (HSMCI) */ |
| 102 | TWI0_IRQn = 19, /**< 19 SAM3S Two Wire Interface 0 (TWI0) */ |
| 103 | TWI1_IRQn = 20, /**< 20 SAM3S Two Wire Interface 1 (TWI1) */ |
| 104 | SPI_IRQn = 21, /**< 21 SAM3S Serial Peripheral Interface (SPI) */ |
| 105 | SSC_IRQn = 22, /**< 22 SAM3S Synchronous Serial Controler (SSC) */ |
| 106 | TC0_IRQn = 23, /**< 23 SAM3S Timer/Counter 0 (TC0) */ |
| 107 | TC1_IRQn = 24, /**< 24 SAM3S Timer/Counter 1 (TC1) */ |
| 108 | TC2_IRQn = 25, /**< 25 SAM3S Timer/Counter 2 (TC2) */ |
| 109 | TC3_IRQn = 26, /**< 26 SAM3S Timer/Counter 3 (TC3) */ |
| 110 | TC4_IRQn = 27, /**< 27 SAM3S Timer/Counter 4 (TC4) */ |
| 111 | TC5_IRQn = 28, /**< 28 SAM3S Timer/Counter 5 (TC5) */ |
| 112 | ADC_IRQn = 29, /**< 29 SAM3S Analog To Digital Converter (ADC) */ |
| 113 | DACC_IRQn = 30, /**< 30 SAM3S Digital To Analog Converter (DACC) */ |
| 114 | PWM_IRQn = 31, /**< 31 SAM3S Pulse Width Modulation (PWM) */ |
| 115 | CRCCU_IRQn = 32, /**< 32 SAM3S CRC Calculation Unit (CRCCU) */ |
| 116 | ACC_IRQn = 33, /**< 33 SAM3S Analog Comparator (ACC) */ |
| 117 | UDP_IRQn = 34 /**< 34 SAM3S USB Device Port (UDP) */ |
| 118 | } IRQn_Type; |
| 119 | |
| 120 | /** |
| 121 | * \brief Configuration of the Cortex-M3 Processor and Core Peripherals |
| 122 | */ |
| 123 | |
| 124 | #define __MPU_PRESENT 1 /**< $product does provide a MPU */ |
| 125 | #define __NVIC_PRIO_BITS 4 /**< $product uses 4 Bits for the Priority Levels */ |
| 126 | #define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ |
| 127 | |
| 128 | /* |
| 129 | * \brief CMSIS includes |
| 130 | */ |
| 131 | |
| 132 | #include "core_cm3.h" |
| 133 | |
| 134 | /*@}*/ |
| 135 | |
| 136 | /* ************************************************************************** */ |
| 137 | /** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3S */ |
| 138 | /* ************************************************************************** */ |
| 139 | /** \addtogroup SAM3S_api Peripheral Software API */ |
| 140 | /*@{*/ |
| 141 | /* ============================================================================= */ |
| 142 | /** SOFTWARE API DEFINITION FOR Analog Comparator Controller */ |
| 143 | /* ============================================================================= */ |
| 144 | /** \addtogroup SAM3S_ACC Analog Comparator Controller */ |
| 145 | /*@{*/ |
| 146 | |
| 147 | #ifndef __ASSEMBLY__ |
| 148 | /** \brief Acc hardware registers */ |
| 149 | typedef struct { |
| 150 | WoReg ACC_CR; /**< \brief (Acc Offset: 0x00) Control Register */ |
| 151 | RwReg ACC_MR; /**< \brief (Acc Offset: 0x04) Mode Register */ |
| 152 | RwReg Reserved1[7]; |
| 153 | WoReg ACC_IER; /**< \brief (Acc Offset: 0x24) Interrupt Enable Register */ |
| 154 | WoReg ACC_IDR; /**< \brief (Acc Offset: 0x28) Interrupt Disable Register */ |
| 155 | RoReg ACC_IMR; /**< \brief (Acc Offset: 0x2C) Interrupt Mask Register */ |
| 156 | RoReg ACC_ISR; /**< \brief (Acc Offset: 0x30) Interrupt Status Register */ |
| 157 | RwReg Reserved2[24]; |
| 158 | RwReg ACC_ACR; /**< \brief (Acc Offset: 0x94) Analog Control Register */ |
| 159 | RwReg Reserved3[19]; |
| 160 | RwReg ACC_WPMR; /**< \brief (Acc Offset: 0xE4) Write Protect Mode Register */ |
| 161 | RoReg ACC_WPSR; /**< \brief (Acc Offset: 0xE8) Write Protect Status Register */ |
| 162 | } Acc; |
| 163 | #endif /* __ASSEMBLY__ */ |
| 164 | /* -------- ACC_CR : (ACC Offset: 0x00) Control Register -------- */ |
| 165 | #define ACC_CR_SWRST (0x1u << 0) /**< \brief (ACC_CR) SoftWare ReSeT */ |
| 166 | /* -------- ACC_MR : (ACC Offset: 0x04) Mode Register -------- */ |
| 167 | #define ACC_MR_SELMINUS_Pos 0 |
| 168 | #define ACC_MR_SELMINUS_Msk (0x7u << ACC_MR_SELMINUS_Pos) /**< \brief (ACC_MR) SELection for MINUS comparator input */ |
| 169 | #define ACC_MR_SELMINUS_TS (0x0u << 0) /**< \brief (ACC_MR) SelectTS */ |
| 170 | #define ACC_MR_SELMINUS_ADVREF (0x1u << 0) /**< \brief (ACC_MR) Select ADVREF */ |
| 171 | #define ACC_MR_SELMINUS_DAC0 (0x2u << 0) /**< \brief (ACC_MR) Select DAC0 */ |
| 172 | #define ACC_MR_SELMINUS_DAC1 (0x3u << 0) /**< \brief (ACC_MR) Select DAC1 */ |
| 173 | #define ACC_MR_SELMINUS_AD0 (0x4u << 0) /**< \brief (ACC_MR) Select AD0 */ |
| 174 | #define ACC_MR_SELMINUS_AD1 (0x5u << 0) /**< \brief (ACC_MR) Select AD1 */ |
| 175 | #define ACC_MR_SELMINUS_AD2 (0x6u << 0) /**< \brief (ACC_MR) Select AD2 */ |
| 176 | #define ACC_MR_SELMINUS_AD3 (0x7u << 0) /**< \brief (ACC_MR) Select AD3 */ |
| 177 | #define ACC_MR_SELPLUS_Pos 4 |
| 178 | #define ACC_MR_SELPLUS_Msk (0x7u << ACC_MR_SELPLUS_Pos) /**< \brief (ACC_MR) SELection for PLUS comparator input */ |
| 179 | #define ACC_MR_SELPLUS_AD0 (0x0u << 4) /**< \brief (ACC_MR) Select AD0 */ |
| 180 | #define ACC_MR_SELPLUS_AD1 (0x1u << 4) /**< \brief (ACC_MR) Select AD1 */ |
| 181 | #define ACC_MR_SELPLUS_AD2 (0x2u << 4) /**< \brief (ACC_MR) Select AD2 */ |
| 182 | #define ACC_MR_SELPLUS_AD3 (0x3u << 4) /**< \brief (ACC_MR) Select AD3 */ |
| 183 | #define ACC_MR_SELPLUS_AD4 (0x4u << 4) /**< \brief (ACC_MR) Select AD4 */ |
| 184 | #define ACC_MR_SELPLUS_AD5 (0x5u << 4) /**< \brief (ACC_MR) Select AD5 */ |
| 185 | #define ACC_MR_SELPLUS_AD6 (0x6u << 4) /**< \brief (ACC_MR) Select AD6 */ |
| 186 | #define ACC_MR_SELPLUS_AD7 (0x7u << 4) /**< \brief (ACC_MR) Select AD7 */ |
| 187 | #define ACC_MR_ACEN (0x1u << 8) /**< \brief (ACC_MR) Analog Comparator ENable */ |
| 188 | #define ACC_MR_ACEN_DIS (0x0u << 8) /**< \brief (ACC_MR) Analog Comparator Disabled. */ |
| 189 | #define ACC_MR_ACEN_EN (0x1u << 8) /**< \brief (ACC_MR) Analog Comparator Enabled. */ |
| 190 | #define ACC_MR_EDGETYP_Pos 9 |
| 191 | #define ACC_MR_EDGETYP_Msk (0x3u << ACC_MR_EDGETYP_Pos) /**< \brief (ACC_MR) EDGE TYPe */ |
| 192 | #define ACC_MR_EDGETYP_RISING (0x0u << 9) /**< \brief (ACC_MR) only rising edge of comparator output */ |
| 193 | #define ACC_MR_EDGETYP_FALLING (0x1u << 9) /**< \brief (ACC_MR) falling edge of comparator output */ |
| 194 | #define ACC_MR_EDGETYP_ANY (0x2u << 9) /**< \brief (ACC_MR) any edge of comparator output */ |
| 195 | #define ACC_MR_INV (0x1u << 12) /**< \brief (ACC_MR) INVert comparator output */ |
| 196 | #define ACC_MR_INV_DIS (0x0u << 12) /**< \brief (ACC_MR) Analog Comparator output is directly processed. */ |
| 197 | #define ACC_MR_INV_EN (0x1u << 12) /**< \brief (ACC_MR) Analog Comparator output is inverted prior to being processed. */ |
| 198 | #define ACC_MR_SELFS (0x1u << 13) /**< \brief (ACC_MR) SELection of Fault Source */ |
| 199 | #define ACC_MR_SELFS_CF (0x0u << 13) /**< \brief (ACC_MR) the CF flag is used to drive the FAULT output. */ |
| 200 | #define ACC_MR_SELFS_OUTPUT (0x1u << 13) /**< \brief (ACC_MR) the output of the Analog Comparator flag is used to drive the FAULT output. */ |
| 201 | #define ACC_MR_FE (0x1u << 14) /**< \brief (ACC_MR) Fault Enable */ |
| 202 | #define ACC_MR_FE_DIS (0x0u << 14) /**< \brief (ACC_MR) the FAULT output is tied to 0. */ |
| 203 | #define ACC_MR_FE_EN (0x1u << 14) /**< \brief (ACC_MR) the FAULT output is driven by the signal defined by SELFS. */ |
| 204 | /* -------- ACC_IER : (ACC Offset: 0x24) Interrupt Enable Register -------- */ |
| 205 | #define ACC_IER_CE (0x1u << 0) /**< \brief (ACC_IER) Comparison Edge */ |
| 206 | /* -------- ACC_IDR : (ACC Offset: 0x28) Interrupt Disable Register -------- */ |
| 207 | #define ACC_IDR_CE (0x1u << 0) /**< \brief (ACC_IDR) Comparison Edge */ |
| 208 | /* -------- ACC_IMR : (ACC Offset: 0x2C) Interrupt Mask Register -------- */ |
| 209 | #define ACC_IMR_CE (0x1u << 0) /**< \brief (ACC_IMR) Comparison Edge */ |
| 210 | /* -------- ACC_ISR : (ACC Offset: 0x30) Interrupt Status Register -------- */ |
| 211 | #define ACC_ISR_CE (0x1u << 0) /**< \brief (ACC_ISR) Comparison Edge */ |
| 212 | #define ACC_ISR_SCO (0x1u << 1) /**< \brief (ACC_ISR) Synchronized Comparator Output */ |
| 213 | #define ACC_ISR_MASK (0x1u << 31) /**< \brief (ACC_ISR) */ |
| 214 | /* -------- ACC_ACR : (ACC Offset: 0x94) Analog Control Register -------- */ |
| 215 | #define ACC_ACR_ISEL (0x1u << 0) /**< \brief (ACC_ACR) Current SELection */ |
| 216 | #define ACC_ACR_ISEL_LOPW (0x0u << 0) /**< \brief (ACC_ACR) low power option. */ |
| 217 | #define ACC_ACR_ISEL_HISP (0x1u << 0) /**< \brief (ACC_ACR) high speed option. */ |
| 218 | #define ACC_ACR_HYST_Pos 1 |
| 219 | #define ACC_ACR_HYST_Msk (0x3u << ACC_ACR_HYST_Pos) /**< \brief (ACC_ACR) HYSTeresis selection */ |
| 220 | #define ACC_ACR_HYST(value) ((ACC_ACR_HYST_Msk & ((value) << ACC_ACR_HYST_Pos))) |
| 221 | /* -------- ACC_WPMR : (ACC Offset: 0xE4) Write Protect Mode Register -------- */ |
| 222 | #define ACC_WPMR_WPEN (0x1u << 0) /**< \brief (ACC_WPMR) Write Protect Enable */ |
| 223 | #define ACC_WPMR_WPKEY_Pos 8 |
| 224 | #define ACC_WPMR_WPKEY_Msk (0xffffffu << ACC_WPMR_WPKEY_Pos) /**< \brief (ACC_WPMR) Write Protect KEY */ |
| 225 | #define ACC_WPMR_WPKEY(value) ((ACC_WPMR_WPKEY_Msk & ((value) << ACC_WPMR_WPKEY_Pos))) |
| 226 | /* -------- ACC_WPSR : (ACC Offset: 0xE8) Write Protect Status Register -------- */ |
| 227 | #define ACC_WPSR_WPROTERR (0x1u << 0) /**< \brief (ACC_WPSR) Write PROTection ERRor */ |
| 228 | |
| 229 | /*@}*/ |
| 230 | |
| 231 | /* ============================================================================= */ |
| 232 | /** SOFTWARE API DEFINITION FOR Analog-to-digital Converter */ |
| 233 | /* ============================================================================= */ |
| 234 | /** \addtogroup SAM3S_ADC Analog-to-digital Converter */ |
| 235 | /*@{*/ |
| 236 | |
| 237 | #ifndef __ASSEMBLY__ |
| 238 | /** \brief Adc hardware registers */ |
| 239 | typedef struct { |
| 240 | WoReg ADC_CR; /**< \brief (Adc Offset: 0x00) Control Register */ |
| 241 | RwReg ADC_MR; /**< \brief (Adc Offset: 0x04) Mode Register */ |
| 242 | RwReg ADC_SEQR1; /**< \brief (Adc Offset: 0x08) Channel Sequence Register 1 */ |
| 243 | RwReg ADC_SEQR2; /**< \brief (Adc Offset: 0x0C) Channel Sequence Register 2 */ |
| 244 | WoReg ADC_CHER; /**< \brief (Adc Offset: 0x10) Channel Enable Register */ |
| 245 | WoReg ADC_CHDR; /**< \brief (Adc Offset: 0x14) Channel Disable Register */ |
| 246 | RoReg ADC_CHSR; /**< \brief (Adc Offset: 0x18) Channel Status Register */ |
| 247 | RwReg Reserved1[1]; |
| 248 | RoReg ADC_LCDR; /**< \brief (Adc Offset: 0x20) Last Converted Data Register */ |
| 249 | WoReg ADC_IER; /**< \brief (Adc Offset: 0x24) Interrupt Enable Register */ |
| 250 | WoReg ADC_IDR; /**< \brief (Adc Offset: 0x28) Interrupt Disable Register */ |
| 251 | RoReg ADC_IMR; /**< \brief (Adc Offset: 0x2C) Interrupt Mask Register */ |
| 252 | RoReg ADC_ISR; /**< \brief (Adc Offset: 0x30) Interrupt Status Register */ |
| 253 | RwReg Reserved2[2]; |
| 254 | RoReg ADC_OVER; /**< \brief (Adc Offset: 0x3C) Overrun Status Register */ |
| 255 | RwReg ADC_EMR; /**< \brief (Adc Offset: 0x40) Extended Mode Register */ |
| 256 | RwReg ADC_CWR; /**< \brief (Adc Offset: 0x44) Compare Window Register */ |
| 257 | RwReg ADC_CGR; /**< \brief (Adc Offset: 0x48) Channel Gain Register */ |
| 258 | RwReg ADC_COR; /**< \brief (Adc Offset: 0x4C) Channel Offset Register */ |
| 259 | RoReg ADC_CDR[16]; /**< \brief (Adc Offset: 0x50) Channel Data Register */ |
| 260 | RwReg Reserved3[1]; |
| 261 | RwReg ADC_ACR; /**< \brief (Adc Offset: 0x94) Analog Control Register */ |
| 262 | RwReg Reserved4[19]; |
| 263 | RwReg ADC_WPMR; /**< \brief (Adc Offset: 0xE4) Write Protect Mode Register */ |
| 264 | RoReg ADC_WPSR; /**< \brief (Adc Offset: 0xE8) Write Protect Status Register */ |
| 265 | RwReg Reserved5[5]; |
| 266 | RwReg ADC_RPR; /**< \brief (Adc Offset: 0x100) Receive Pointer Register */ |
| 267 | RwReg ADC_RCR; /**< \brief (Adc Offset: 0x104) Receive Counter Register */ |
| 268 | RwReg ADC_TPR; /**< \brief (Adc Offset: 0x108) Transmit Pointer Register */ |
| 269 | RwReg ADC_TCR; /**< \brief (Adc Offset: 0x10C) Transmit Counter Register */ |
| 270 | RwReg ADC_RNPR; /**< \brief (Adc Offset: 0x110) Receive Next Pointer Register */ |
| 271 | RwReg ADC_RNCR; /**< \brief (Adc Offset: 0x114) Receive Next Counter Register */ |
| 272 | RwReg ADC_TNPR; /**< \brief (Adc Offset: 0x118) Transmit Next Pointer Register */ |
| 273 | RwReg ADC_TNCR; /**< \brief (Adc Offset: 0x11C) Transmit Next Counter Register */ |
| 274 | WoReg ADC_PTCR; /**< \brief (Adc Offset: 0x120) Transfer Control Register */ |
| 275 | RoReg ADC_PTSR; /**< \brief (Adc Offset: 0x124) Transfer Status Register */ |
| 276 | } Adc; |
| 277 | #endif /* __ASSEMBLY__ */ |
| 278 | /* -------- ADC_CR : (ADC Offset: 0x00) Control Register -------- */ |
| 279 | #define ADC_CR_SWRST (0x1u << 0) /**< \brief (ADC_CR) Software Reset */ |
| 280 | #define ADC_CR_START (0x1u << 1) /**< \brief (ADC_CR) Start Conversion */ |
| 281 | /* -------- ADC_MR : (ADC Offset: 0x04) Mode Register -------- */ |
| 282 | #define ADC_MR_TRGEN (0x1u << 0) /**< \brief (ADC_MR) Trigger Enable */ |
| 283 | #define ADC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (ADC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. */ |
| 284 | #define ADC_MR_TRGEN_EN (0x1u << 0) /**< \brief (ADC_MR) Hardware trigger selected by TRGSEL field is enabled. */ |
| 285 | #define ADC_MR_TRGSEL_Pos 1 |
| 286 | #define ADC_MR_TRGSEL_Msk (0x7u << ADC_MR_TRGSEL_Pos) /**< \brief (ADC_MR) Trigger Selection */ |
| 287 | #define ADC_MR_TRGSEL_ADC_TRIG0 (0x0u << 1) /**< \brief (ADC_MR) External trigger */ |
| 288 | #define ADC_MR_TRGSEL_ADC_TRIG1 (0x1u << 1) /**< \brief (ADC_MR) TIO Output of the Timer Counter Channel 0 */ |
| 289 | #define ADC_MR_TRGSEL_ADC_TRIG2 (0x2u << 1) /**< \brief (ADC_MR) TIO Output of the Timer Counter Channel 1 */ |
| 290 | #define ADC_MR_TRGSEL_ADC_TRIG3 (0x3u << 1) /**< \brief (ADC_MR) TIO Output of the Timer Counter Channel 2 */ |
| 291 | #define ADC_MR_TRGSEL_ADC_TRIG4 (0x4u << 1) /**< \brief (ADC_MR) PWM Event Line 0 */ |
| 292 | #define ADC_MR_TRGSEL_ADC_TRIG5 (0x5u << 1) /**< \brief (ADC_MR) PWM Event Line 1 */ |
| 293 | #define ADC_MR_LOWRES (0x1u << 4) /**< \brief (ADC_MR) Resolution */ |
| 294 | #define ADC_MR_LOWRES_BITS_12 (0x0u << 4) /**< \brief (ADC_MR) 12-bit resolution */ |
| 295 | #define ADC_MR_LOWRES_BITS_10 (0x1u << 4) /**< \brief (ADC_MR) 10-bit resolution */ |
| 296 | #define ADC_MR_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode */ |
| 297 | #define ADC_MR_SLEEP_NORMAL (0x0u << 5) /**< \brief (ADC_MR) Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions */ |
| 298 | #define ADC_MR_SLEEP_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode: The ADC Core and reference voltage circuitry are OFF between conversions */ |
| 299 | #define ADC_MR_FWUP (0x1u << 6) /**< \brief (ADC_MR) Fast Wake Up */ |
| 300 | #define ADC_MR_FWUP_OFF (0x0u << 6) /**< \brief (ADC_MR) Normal Sleep Mode: The sleep mode is defined by the SLEEP bit */ |
| 301 | #define ADC_MR_FWUP_ON (0x1u << 6) /**< \brief (ADC_MR) Fast Wake Up Sleep Mode: The Voltage reference is ON between conversions and ADC Core is OFF */ |
| 302 | #define ADC_MR_FREERUN (0x1u << 7) /**< \brief (ADC_MR) Free Run Mode */ |
| 303 | #define ADC_MR_FREERUN_OFF (0x0u << 7) /**< \brief (ADC_MR) Normal Mode */ |
| 304 | #define ADC_MR_FREERUN_ON (0x1u << 7) /**< \brief (ADC_MR) Free Run Mode: Never wait for any trigger. */ |
| 305 | #define ADC_MR_PRESCAL_Pos 8 |
| 306 | #define ADC_MR_PRESCAL_Msk (0xffu << ADC_MR_PRESCAL_Pos) /**< \brief (ADC_MR) Prescaler Rate Selection */ |
| 307 | #define ADC_MR_PRESCAL(value) ((ADC_MR_PRESCAL_Msk & ((value) << ADC_MR_PRESCAL_Pos))) |
| 308 | #define ADC_MR_STARTUP_Pos 16 |
| 309 | #define ADC_MR_STARTUP_Msk (0xfu << ADC_MR_STARTUP_Pos) /**< \brief (ADC_MR) Start Up Time */ |
| 310 | #define ADC_MR_STARTUP_SUT0 (0x0u << 16) /**< \brief (ADC_MR) 0 periods of ADCClock */ |
| 311 | #define ADC_MR_STARTUP_SUT8 (0x1u << 16) /**< \brief (ADC_MR) 8 periods of ADCClock */ |
| 312 | #define ADC_MR_STARTUP_SUT16 (0x2u << 16) /**< \brief (ADC_MR) 16 periods of ADCClock */ |
| 313 | #define ADC_MR_STARTUP_SUT24 (0x3u << 16) /**< \brief (ADC_MR) 24 periods of ADCClock */ |
| 314 | #define ADC_MR_STARTUP_SUT64 (0x4u << 16) /**< \brief (ADC_MR) 64 periods of ADCClock */ |
| 315 | #define ADC_MR_STARTUP_SUT80 (0x5u << 16) /**< \brief (ADC_MR) 80 periods of ADCClock */ |
| 316 | #define ADC_MR_STARTUP_SUT96 (0x6u << 16) /**< \brief (ADC_MR) 96 periods of ADCClock */ |
| 317 | #define ADC_MR_STARTUP_SUT112 (0x7u << 16) /**< \brief (ADC_MR) 112 periods of ADCClock */ |
| 318 | #define ADC_MR_STARTUP_SUT512 (0x8u << 16) /**< \brief (ADC_MR) 512 periods of ADCClock */ |
| 319 | #define ADC_MR_STARTUP_SUT576 (0x9u << 16) /**< \brief (ADC_MR) 576 periods of ADCClock */ |
| 320 | #define ADC_MR_STARTUP_SUT640 (0xAu << 16) /**< \brief (ADC_MR) 640 periods of ADCClock */ |
| 321 | #define ADC_MR_STARTUP_SUT704 (0xBu << 16) /**< \brief (ADC_MR) 704 periods of ADCClock */ |
| 322 | #define ADC_MR_STARTUP_SUT768 (0xCu << 16) /**< \brief (ADC_MR) 768 periods of ADCClock */ |
| 323 | #define ADC_MR_STARTUP_SUT832 (0xDu << 16) /**< \brief (ADC_MR) 832 periods of ADCClock */ |
| 324 | #define ADC_MR_STARTUP_SUT896 (0xEu << 16) /**< \brief (ADC_MR) 896 periods of ADCClock */ |
| 325 | #define ADC_MR_STARTUP_SUT960 (0xFu << 16) /**< \brief (ADC_MR) 960 periods of ADCClock */ |
| 326 | #define ADC_MR_SETTLING_Pos 20 |
| 327 | #define ADC_MR_SETTLING_Msk (0x3u << ADC_MR_SETTLING_Pos) /**< \brief (ADC_MR) Analog Settling Time */ |
| 328 | #define ADC_MR_SETTLING(value) ((ADC_MR_SETTLING_Msk & ((value) << ADC_MR_SETTLING_Pos))) |
| 329 | #define ADC_MR_ANACH (0x1u << 23) /**< \brief (ADC_MR) Analog Change */ |
| 330 | #define ADC_MR_ANACH_NONE (0x0u << 23) /**< \brief (ADC_MR) No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels */ |
| 331 | #define ADC_MR_ANACH_ALLOWED (0x1u << 23) /**< \brief (ADC_MR) Allows different analog settings for each channel. See ADC_CGR and ADC_COR Registers */ |
| 332 | #define ADC_MR_TRACKTIM_Pos 24 |
| 333 | #define ADC_MR_TRACKTIM_Msk (0xfu << ADC_MR_TRACKTIM_Pos) /**< \brief (ADC_MR) Tracking Time */ |
| 334 | #define ADC_MR_TRACKTIM(value) ((ADC_MR_TRACKTIM_Msk & ((value) << ADC_MR_TRACKTIM_Pos))) |
| 335 | #define ADC_MR_TRANSFER_Pos 28 |
| 336 | #define ADC_MR_TRANSFER_Msk (0x3u << ADC_MR_TRANSFER_Pos) /**< \brief (ADC_MR) */ |
| 337 | #define ADC_MR_TRANSFER(value) ((ADC_MR_TRANSFER_Msk & ((value) << ADC_MR_TRANSFER_Pos))) |
| 338 | #define ADC_MR_USEQ (0x1u << 31) /**< \brief (ADC_MR) Use Sequence Enable */ |
| 339 | #define ADC_MR_USEQ_NUM_ORDER (0x0u << 31) /**< \brief (ADC_MR) Normal Mode: The controller converts channels in a simple numeric order. */ |
| 340 | #define ADC_MR_USEQ_REG_ORDER (0x1u << 31) /**< \brief (ADC_MR) User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers. */ |
| 341 | /* -------- ADC_SEQR1 : (ADC Offset: 0x08) Channel Sequence Register 1 -------- */ |
| 342 | #define ADC_SEQR1_USCH1_Pos 0 |
| 343 | #define ADC_SEQR1_USCH1_Msk (0x7u << ADC_SEQR1_USCH1_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 1 */ |
| 344 | #define ADC_SEQR1_USCH1(value) ((ADC_SEQR1_USCH1_Msk & ((value) << ADC_SEQR1_USCH1_Pos))) |
| 345 | #define ADC_SEQR1_USCH2_Pos 4 |
| 346 | #define ADC_SEQR1_USCH2_Msk (0x7u << ADC_SEQR1_USCH2_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 2 */ |
| 347 | #define ADC_SEQR1_USCH2(value) ((ADC_SEQR1_USCH2_Msk & ((value) << ADC_SEQR1_USCH2_Pos))) |
| 348 | #define ADC_SEQR1_USCH3_Pos 8 |
| 349 | #define ADC_SEQR1_USCH3_Msk (0x7u << ADC_SEQR1_USCH3_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 3 */ |
| 350 | #define ADC_SEQR1_USCH3(value) ((ADC_SEQR1_USCH3_Msk & ((value) << ADC_SEQR1_USCH3_Pos))) |
| 351 | #define ADC_SEQR1_USCH4_Pos 12 |
| 352 | #define ADC_SEQR1_USCH4_Msk (0x7u << ADC_SEQR1_USCH4_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 4 */ |
| 353 | #define ADC_SEQR1_USCH4(value) ((ADC_SEQR1_USCH4_Msk & ((value) << ADC_SEQR1_USCH4_Pos))) |
| 354 | #define ADC_SEQR1_USCH5_Pos 16 |
| 355 | #define ADC_SEQR1_USCH5_Msk (0x7u << ADC_SEQR1_USCH5_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 5 */ |
| 356 | #define ADC_SEQR1_USCH5(value) ((ADC_SEQR1_USCH5_Msk & ((value) << ADC_SEQR1_USCH5_Pos))) |
| 357 | #define ADC_SEQR1_USCH6_Pos 20 |
| 358 | #define ADC_SEQR1_USCH6_Msk (0x7u << ADC_SEQR1_USCH6_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 6 */ |
| 359 | #define ADC_SEQR1_USCH6(value) ((ADC_SEQR1_USCH6_Msk & ((value) << ADC_SEQR1_USCH6_Pos))) |
| 360 | #define ADC_SEQR1_USCH7_Pos 24 |
| 361 | #define ADC_SEQR1_USCH7_Msk (0x7u << ADC_SEQR1_USCH7_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 7 */ |
| 362 | #define ADC_SEQR1_USCH7(value) ((ADC_SEQR1_USCH7_Msk & ((value) << ADC_SEQR1_USCH7_Pos))) |
| 363 | #define ADC_SEQR1_USCH8_Pos 28 |
| 364 | #define ADC_SEQR1_USCH8_Msk (0x7u << ADC_SEQR1_USCH8_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 8 */ |
| 365 | #define ADC_SEQR1_USCH8(value) ((ADC_SEQR1_USCH8_Msk & ((value) << ADC_SEQR1_USCH8_Pos))) |
| 366 | /* -------- ADC_SEQR2 : (ADC Offset: 0x0C) Channel Sequence Register 2 -------- */ |
| 367 | #define ADC_SEQR2_USCH9_Pos 0 |
| 368 | #define ADC_SEQR2_USCH9_Msk (0x7u << ADC_SEQR2_USCH9_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 9 */ |
| 369 | #define ADC_SEQR2_USCH9(value) ((ADC_SEQR2_USCH9_Msk & ((value) << ADC_SEQR2_USCH9_Pos))) |
| 370 | #define ADC_SEQR2_USCH10_Pos 4 |
| 371 | #define ADC_SEQR2_USCH10_Msk (0x7u << ADC_SEQR2_USCH10_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 10 */ |
| 372 | #define ADC_SEQR2_USCH10(value) ((ADC_SEQR2_USCH10_Msk & ((value) << ADC_SEQR2_USCH10_Pos))) |
| 373 | #define ADC_SEQR2_USCH11_Pos 8 |
| 374 | #define ADC_SEQR2_USCH11_Msk (0x7u << ADC_SEQR2_USCH11_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 11 */ |
| 375 | #define ADC_SEQR2_USCH11(value) ((ADC_SEQR2_USCH11_Msk & ((value) << ADC_SEQR2_USCH11_Pos))) |
| 376 | #define ADC_SEQR2_USCH12_Pos 12 |
| 377 | #define ADC_SEQR2_USCH12_Msk (0x7u << ADC_SEQR2_USCH12_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 12 */ |
| 378 | #define ADC_SEQR2_USCH12(value) ((ADC_SEQR2_USCH12_Msk & ((value) << ADC_SEQR2_USCH12_Pos))) |
| 379 | #define ADC_SEQR2_USCH13_Pos 16 |
| 380 | #define ADC_SEQR2_USCH13_Msk (0x7u << ADC_SEQR2_USCH13_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 13 */ |
| 381 | #define ADC_SEQR2_USCH13(value) ((ADC_SEQR2_USCH13_Msk & ((value) << ADC_SEQR2_USCH13_Pos))) |
| 382 | #define ADC_SEQR2_USCH14_Pos 20 |
| 383 | #define ADC_SEQR2_USCH14_Msk (0x7u << ADC_SEQR2_USCH14_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 14 */ |
| 384 | #define ADC_SEQR2_USCH14(value) ((ADC_SEQR2_USCH14_Msk & ((value) << ADC_SEQR2_USCH14_Pos))) |
| 385 | #define ADC_SEQR2_USCH15_Pos 24 |
| 386 | #define ADC_SEQR2_USCH15_Msk (0x7u << ADC_SEQR2_USCH15_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 15 */ |
| 387 | #define ADC_SEQR2_USCH15(value) ((ADC_SEQR2_USCH15_Msk & ((value) << ADC_SEQR2_USCH15_Pos))) |
| 388 | #define ADC_SEQR2_USCH16_Pos 28 |
| 389 | #define ADC_SEQR2_USCH16_Msk (0x7u << ADC_SEQR2_USCH16_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 16 */ |
| 390 | #define ADC_SEQR2_USCH16(value) ((ADC_SEQR2_USCH16_Msk & ((value) << ADC_SEQR2_USCH16_Pos))) |
| 391 | /* -------- ADC_CHER : (ADC Offset: 0x10) Channel Enable Register -------- */ |
| 392 | #define ADC_CHER_CH0 (0x1u << 0) /**< \brief (ADC_CHER) Channel 0 Enable */ |
| 393 | #define ADC_CHER_CH1 (0x1u << 1) /**< \brief (ADC_CHER) Channel 1 Enable */ |
| 394 | #define ADC_CHER_CH2 (0x1u << 2) /**< \brief (ADC_CHER) Channel 2 Enable */ |
| 395 | #define ADC_CHER_CH3 (0x1u << 3) /**< \brief (ADC_CHER) Channel 3 Enable */ |
| 396 | #define ADC_CHER_CH4 (0x1u << 4) /**< \brief (ADC_CHER) Channel 4 Enable */ |
| 397 | #define ADC_CHER_CH5 (0x1u << 5) /**< \brief (ADC_CHER) Channel 5 Enable */ |
| 398 | #define ADC_CHER_CH6 (0x1u << 6) /**< \brief (ADC_CHER) Channel 6 Enable */ |
| 399 | #define ADC_CHER_CH7 (0x1u << 7) /**< \brief (ADC_CHER) Channel 7 Enable */ |
| 400 | #define ADC_CHER_CH8 (0x1u << 8) /**< \brief (ADC_CHER) Channel 8 Enable */ |
| 401 | #define ADC_CHER_CH9 (0x1u << 9) /**< \brief (ADC_CHER) Channel 9 Enable */ |
| 402 | #define ADC_CHER_CH10 (0x1u << 10) /**< \brief (ADC_CHER) Channel 10 Enable */ |
| 403 | #define ADC_CHER_CH11 (0x1u << 11) /**< \brief (ADC_CHER) Channel 11 Enable */ |
| 404 | #define ADC_CHER_CH12 (0x1u << 12) /**< \brief (ADC_CHER) Channel 12 Enable */ |
| 405 | #define ADC_CHER_CH13 (0x1u << 13) /**< \brief (ADC_CHER) Channel 13 Enable */ |
| 406 | #define ADC_CHER_CH14 (0x1u << 14) /**< \brief (ADC_CHER) Channel 14 Enable */ |
| 407 | #define ADC_CHER_CH15 (0x1u << 15) /**< \brief (ADC_CHER) Channel 15 Enable */ |
| 408 | /* -------- ADC_CHDR : (ADC Offset: 0x14) Channel Disable Register -------- */ |
| 409 | #define ADC_CHDR_CH0 (0x1u << 0) /**< \brief (ADC_CHDR) Channel 0 Disable */ |
| 410 | #define ADC_CHDR_CH1 (0x1u << 1) /**< \brief (ADC_CHDR) Channel 1 Disable */ |
| 411 | #define ADC_CHDR_CH2 (0x1u << 2) /**< \brief (ADC_CHDR) Channel 2 Disable */ |
| 412 | #define ADC_CHDR_CH3 (0x1u << 3) /**< \brief (ADC_CHDR) Channel 3 Disable */ |
| 413 | #define ADC_CHDR_CH4 (0x1u << 4) /**< \brief (ADC_CHDR) Channel 4 Disable */ |
| 414 | #define ADC_CHDR_CH5 (0x1u << 5) /**< \brief (ADC_CHDR) Channel 5 Disable */ |
| 415 | #define ADC_CHDR_CH6 (0x1u << 6) /**< \brief (ADC_CHDR) Channel 6 Disable */ |
| 416 | #define ADC_CHDR_CH7 (0x1u << 7) /**< \brief (ADC_CHDR) Channel 7 Disable */ |
| 417 | #define ADC_CHDR_CH8 (0x1u << 8) /**< \brief (ADC_CHDR) Channel 8 Disable */ |
| 418 | #define ADC_CHDR_CH9 (0x1u << 9) /**< \brief (ADC_CHDR) Channel 9 Disable */ |
| 419 | #define ADC_CHDR_CH10 (0x1u << 10) /**< \brief (ADC_CHDR) Channel 10 Disable */ |
| 420 | #define ADC_CHDR_CH11 (0x1u << 11) /**< \brief (ADC_CHDR) Channel 11 Disable */ |
| 421 | #define ADC_CHDR_CH12 (0x1u << 12) /**< \brief (ADC_CHDR) Channel 12 Disable */ |
| 422 | #define ADC_CHDR_CH13 (0x1u << 13) /**< \brief (ADC_CHDR) Channel 13 Disable */ |
| 423 | #define ADC_CHDR_CH14 (0x1u << 14) /**< \brief (ADC_CHDR) Channel 14 Disable */ |
| 424 | #define ADC_CHDR_CH15 (0x1u << 15) /**< \brief (ADC_CHDR) Channel 15 Disable */ |
| 425 | /* -------- ADC_CHSR : (ADC Offset: 0x18) Channel Status Register -------- */ |
| 426 | #define ADC_CHSR_CH0 (0x1u << 0) /**< \brief (ADC_CHSR) Channel 0 Status */ |
| 427 | #define ADC_CHSR_CH1 (0x1u << 1) /**< \brief (ADC_CHSR) Channel 1 Status */ |
| 428 | #define ADC_CHSR_CH2 (0x1u << 2) /**< \brief (ADC_CHSR) Channel 2 Status */ |
| 429 | #define ADC_CHSR_CH3 (0x1u << 3) /**< \brief (ADC_CHSR) Channel 3 Status */ |
| 430 | #define ADC_CHSR_CH4 (0x1u << 4) /**< \brief (ADC_CHSR) Channel 4 Status */ |
| 431 | #define ADC_CHSR_CH5 (0x1u << 5) /**< \brief (ADC_CHSR) Channel 5 Status */ |
| 432 | #define ADC_CHSR_CH6 (0x1u << 6) /**< \brief (ADC_CHSR) Channel 6 Status */ |
| 433 | #define ADC_CHSR_CH7 (0x1u << 7) /**< \brief (ADC_CHSR) Channel 7 Status */ |
| 434 | #define ADC_CHSR_CH8 (0x1u << 8) /**< \brief (ADC_CHSR) Channel 8 Status */ |
| 435 | #define ADC_CHSR_CH9 (0x1u << 9) /**< \brief (ADC_CHSR) Channel 9 Status */ |
| 436 | #define ADC_CHSR_CH10 (0x1u << 10) /**< \brief (ADC_CHSR) Channel 10 Status */ |
| 437 | #define ADC_CHSR_CH11 (0x1u << 11) /**< \brief (ADC_CHSR) Channel 11 Status */ |
| 438 | #define ADC_CHSR_CH12 (0x1u << 12) /**< \brief (ADC_CHSR) Channel 12 Status */ |
| 439 | #define ADC_CHSR_CH13 (0x1u << 13) /**< \brief (ADC_CHSR) Channel 13 Status */ |
| 440 | #define ADC_CHSR_CH14 (0x1u << 14) /**< \brief (ADC_CHSR) Channel 14 Status */ |
| 441 | #define ADC_CHSR_CH15 (0x1u << 15) /**< \brief (ADC_CHSR) Channel 15 Status */ |
| 442 | /* -------- ADC_LCDR : (ADC Offset: 0x20) Last Converted Data Register -------- */ |
| 443 | #define ADC_LCDR_LDATA_Pos 0 |
| 444 | #define ADC_LCDR_LDATA_Msk (0xfffu << ADC_LCDR_LDATA_Pos) /**< \brief (ADC_LCDR) Last Data Converted */ |
| 445 | #define ADC_LCDR_CHNB_Pos 12 |
| 446 | #define ADC_LCDR_CHNB_Msk (0xfu << ADC_LCDR_CHNB_Pos) /**< \brief (ADC_LCDR) Channel Number */ |
| 447 | /* -------- ADC_IER : (ADC Offset: 0x24) Interrupt Enable Register -------- */ |
| 448 | #define ADC_IER_EOC0 (0x1u << 0) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 0 */ |
| 449 | #define ADC_IER_EOC1 (0x1u << 1) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 1 */ |
| 450 | #define ADC_IER_EOC2 (0x1u << 2) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 2 */ |
| 451 | #define ADC_IER_EOC3 (0x1u << 3) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 3 */ |
| 452 | #define ADC_IER_EOC4 (0x1u << 4) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 4 */ |
| 453 | #define ADC_IER_EOC5 (0x1u << 5) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 5 */ |
| 454 | #define ADC_IER_EOC6 (0x1u << 6) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 6 */ |
| 455 | #define ADC_IER_EOC7 (0x1u << 7) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 7 */ |
| 456 | #define ADC_IER_EOC8 (0x1u << 8) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 8 */ |
| 457 | #define ADC_IER_EOC9 (0x1u << 9) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 9 */ |
| 458 | #define ADC_IER_EOC10 (0x1u << 10) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 10 */ |
| 459 | #define ADC_IER_EOC11 (0x1u << 11) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 11 */ |
| 460 | #define ADC_IER_EOC12 (0x1u << 12) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 12 */ |
| 461 | #define ADC_IER_EOC13 (0x1u << 13) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 13 */ |
| 462 | #define ADC_IER_EOC14 (0x1u << 14) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 14 */ |
| 463 | #define ADC_IER_EOC15 (0x1u << 15) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 15 */ |
| 464 | #define ADC_IER_DRDY (0x1u << 24) /**< \brief (ADC_IER) Data Ready Interrupt Enable */ |
| 465 | #define ADC_IER_GOVRE (0x1u << 25) /**< \brief (ADC_IER) General Overrun Error Interrupt Enable */ |
| 466 | #define ADC_IER_COMPE (0x1u << 26) /**< \brief (ADC_IER) Comparison Event Interrupt Enable */ |
| 467 | #define ADC_IER_ENDRX (0x1u << 27) /**< \brief (ADC_IER) End of Receive Buffer Interrupt Enable */ |
| 468 | #define ADC_IER_RXBUFF (0x1u << 28) /**< \brief (ADC_IER) Receive Buffer Full Interrupt Enable */ |
| 469 | /* -------- ADC_IDR : (ADC Offset: 0x28) Interrupt Disable Register -------- */ |
| 470 | #define ADC_IDR_EOC0 (0x1u << 0) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 0 */ |
| 471 | #define ADC_IDR_EOC1 (0x1u << 1) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 1 */ |
| 472 | #define ADC_IDR_EOC2 (0x1u << 2) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 2 */ |
| 473 | #define ADC_IDR_EOC3 (0x1u << 3) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 3 */ |
| 474 | #define ADC_IDR_EOC4 (0x1u << 4) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 4 */ |
| 475 | #define ADC_IDR_EOC5 (0x1u << 5) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 5 */ |
| 476 | #define ADC_IDR_EOC6 (0x1u << 6) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 6 */ |
| 477 | #define ADC_IDR_EOC7 (0x1u << 7) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 7 */ |
| 478 | #define ADC_IDR_EOC8 (0x1u << 8) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 8 */ |
| 479 | #define ADC_IDR_EOC9 (0x1u << 9) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 9 */ |
| 480 | #define ADC_IDR_EOC10 (0x1u << 10) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 10 */ |
| 481 | #define ADC_IDR_EOC11 (0x1u << 11) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 11 */ |
| 482 | #define ADC_IDR_EOC12 (0x1u << 12) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 12 */ |
| 483 | #define ADC_IDR_EOC13 (0x1u << 13) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 13 */ |
| 484 | #define ADC_IDR_EOC14 (0x1u << 14) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 14 */ |
| 485 | #define ADC_IDR_EOC15 (0x1u << 15) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 15 */ |
| 486 | #define ADC_IDR_DRDY (0x1u << 24) /**< \brief (ADC_IDR) Data Ready Interrupt Disable */ |
| 487 | #define ADC_IDR_GOVRE (0x1u << 25) /**< \brief (ADC_IDR) General Overrun Error Interrupt Disable */ |
| 488 | #define ADC_IDR_COMPE (0x1u << 26) /**< \brief (ADC_IDR) Comparison Event Interrupt Disable */ |
| 489 | #define ADC_IDR_ENDRX (0x1u << 27) /**< \brief (ADC_IDR) End of Receive Buffer Interrupt Disable */ |
| 490 | #define ADC_IDR_RXBUFF (0x1u << 28) /**< \brief (ADC_IDR) Receive Buffer Full Interrupt Disable */ |
| 491 | /* -------- ADC_IMR : (ADC Offset: 0x2C) Interrupt Mask Register -------- */ |
| 492 | #define ADC_IMR_EOC0 (0x1u << 0) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 0 */ |
| 493 | #define ADC_IMR_EOC1 (0x1u << 1) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 1 */ |
| 494 | #define ADC_IMR_EOC2 (0x1u << 2) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 2 */ |
| 495 | #define ADC_IMR_EOC3 (0x1u << 3) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 3 */ |
| 496 | #define ADC_IMR_EOC4 (0x1u << 4) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 4 */ |
| 497 | #define ADC_IMR_EOC5 (0x1u << 5) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 5 */ |
| 498 | #define ADC_IMR_EOC6 (0x1u << 6) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 6 */ |
| 499 | #define ADC_IMR_EOC7 (0x1u << 7) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 7 */ |
| 500 | #define ADC_IMR_EOC8 (0x1u << 8) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 8 */ |
| 501 | #define ADC_IMR_EOC9 (0x1u << 9) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 9 */ |
| 502 | #define ADC_IMR_EOC10 (0x1u << 10) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 10 */ |
| 503 | #define ADC_IMR_EOC11 (0x1u << 11) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 11 */ |
| 504 | #define ADC_IMR_EOC12 (0x1u << 12) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 12 */ |
| 505 | #define ADC_IMR_EOC13 (0x1u << 13) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 13 */ |
| 506 | #define ADC_IMR_EOC14 (0x1u << 14) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 14 */ |
| 507 | #define ADC_IMR_EOC15 (0x1u << 15) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 15 */ |
| 508 | #define ADC_IMR_DRDY (0x1u << 24) /**< \brief (ADC_IMR) Data Ready Interrupt Mask */ |
| 509 | #define ADC_IMR_GOVRE (0x1u << 25) /**< \brief (ADC_IMR) General Overrun Error Interrupt Mask */ |
| 510 | #define ADC_IMR_COMPE (0x1u << 26) /**< \brief (ADC_IMR) Comparison Event Interrupt Mask */ |
| 511 | #define ADC_IMR_ENDRX (0x1u << 27) /**< \brief (ADC_IMR) End of Receive Buffer Interrupt Mask */ |
| 512 | #define ADC_IMR_RXBUFF (0x1u << 28) /**< \brief (ADC_IMR) Receive Buffer Full Interrupt Mask */ |
| 513 | /* -------- ADC_ISR : (ADC Offset: 0x30) Interrupt Status Register -------- */ |
| 514 | #define ADC_ISR_EOC0 (0x1u << 0) /**< \brief (ADC_ISR) End of Conversion 0 */ |
| 515 | #define ADC_ISR_EOC1 (0x1u << 1) /**< \brief (ADC_ISR) End of Conversion 1 */ |
| 516 | #define ADC_ISR_EOC2 (0x1u << 2) /**< \brief (ADC_ISR) End of Conversion 2 */ |
| 517 | #define ADC_ISR_EOC3 (0x1u << 3) /**< \brief (ADC_ISR) End of Conversion 3 */ |
| 518 | #define ADC_ISR_EOC4 (0x1u << 4) /**< \brief (ADC_ISR) End of Conversion 4 */ |
| 519 | #define ADC_ISR_EOC5 (0x1u << 5) /**< \brief (ADC_ISR) End of Conversion 5 */ |
| 520 | #define ADC_ISR_EOC6 (0x1u << 6) /**< \brief (ADC_ISR) End of Conversion 6 */ |
| 521 | #define ADC_ISR_EOC7 (0x1u << 7) /**< \brief (ADC_ISR) End of Conversion 7 */ |
| 522 | #define ADC_ISR_EOC8 (0x1u << 8) /**< \brief (ADC_ISR) End of Conversion 8 */ |
| 523 | #define ADC_ISR_EOC9 (0x1u << 9) /**< \brief (ADC_ISR) End of Conversion 9 */ |
| 524 | #define ADC_ISR_EOC10 (0x1u << 10) /**< \brief (ADC_ISR) End of Conversion 10 */ |
| 525 | #define ADC_ISR_EOC11 (0x1u << 11) /**< \brief (ADC_ISR) End of Conversion 11 */ |
| 526 | #define ADC_ISR_EOC12 (0x1u << 12) /**< \brief (ADC_ISR) End of Conversion 12 */ |
| 527 | #define ADC_ISR_EOC13 (0x1u << 13) /**< \brief (ADC_ISR) End of Conversion 13 */ |
| 528 | #define ADC_ISR_EOC14 (0x1u << 14) /**< \brief (ADC_ISR) End of Conversion 14 */ |
| 529 | #define ADC_ISR_EOC15 (0x1u << 15) /**< \brief (ADC_ISR) End of Conversion 15 */ |
| 530 | #define ADC_ISR_DRDY (0x1u << 24) /**< \brief (ADC_ISR) Data Ready */ |
| 531 | #define ADC_ISR_GOVRE (0x1u << 25) /**< \brief (ADC_ISR) General Overrun Error */ |
| 532 | #define ADC_ISR_COMPE (0x1u << 26) /**< \brief (ADC_ISR) Comparison Error */ |
| 533 | #define ADC_ISR_ENDRX (0x1u << 27) /**< \brief (ADC_ISR) End of RX Buffer */ |
| 534 | #define ADC_ISR_RXBUFF (0x1u << 28) /**< \brief (ADC_ISR) RX Buffer Full */ |
| 535 | /* -------- ADC_OVER : (ADC Offset: 0x3C) Overrun Status Register -------- */ |
| 536 | #define ADC_OVER_OVRE0 (0x1u << 0) /**< \brief (ADC_OVER) Overrun Error 0 */ |
| 537 | #define ADC_OVER_OVRE1 (0x1u << 1) /**< \brief (ADC_OVER) Overrun Error 1 */ |
| 538 | #define ADC_OVER_OVRE2 (0x1u << 2) /**< \brief (ADC_OVER) Overrun Error 2 */ |
| 539 | #define ADC_OVER_OVRE3 (0x1u << 3) /**< \brief (ADC_OVER) Overrun Error 3 */ |
| 540 | #define ADC_OVER_OVRE4 (0x1u << 4) /**< \brief (ADC_OVER) Overrun Error 4 */ |
| 541 | #define ADC_OVER_OVRE5 (0x1u << 5) /**< \brief (ADC_OVER) Overrun Error 5 */ |
| 542 | #define ADC_OVER_OVRE6 (0x1u << 6) /**< \brief (ADC_OVER) Overrun Error 6 */ |
| 543 | #define ADC_OVER_OVRE7 (0x1u << 7) /**< \brief (ADC_OVER) Overrun Error 7 */ |
| 544 | #define ADC_OVER_OVRE8 (0x1u << 8) /**< \brief (ADC_OVER) Overrun Error 8 */ |
| 545 | #define ADC_OVER_OVRE9 (0x1u << 9) /**< \brief (ADC_OVER) Overrun Error 9 */ |
| 546 | #define ADC_OVER_OVRE10 (0x1u << 10) /**< \brief (ADC_OVER) Overrun Error 10 */ |
| 547 | #define ADC_OVER_OVRE11 (0x1u << 11) /**< \brief (ADC_OVER) Overrun Error 11 */ |
| 548 | #define ADC_OVER_OVRE12 (0x1u << 12) /**< \brief (ADC_OVER) Overrun Error 12 */ |
| 549 | #define ADC_OVER_OVRE13 (0x1u << 13) /**< \brief (ADC_OVER) Overrun Error 13 */ |
| 550 | #define ADC_OVER_OVRE14 (0x1u << 14) /**< \brief (ADC_OVER) Overrun Error 14 */ |
| 551 | #define ADC_OVER_OVRE15 (0x1u << 15) /**< \brief (ADC_OVER) Overrun Error 15 */ |
| 552 | /* -------- ADC_EMR : (ADC Offset: 0x40) Extended Mode Register -------- */ |
| 553 | #define ADC_EMR_CMPMODE_Pos 0 |
| 554 | #define ADC_EMR_CMPMODE_Msk (0x3u << ADC_EMR_CMPMODE_Pos) /**< \brief (ADC_EMR) Comparison Mode */ |
| 555 | #define ADC_EMR_CMPMODE_LOW (0x0u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is lower than the low threshold of the window. */ |
| 556 | #define ADC_EMR_CMPMODE_HIGH (0x1u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is higher than the high threshold of the window. */ |
| 557 | #define ADC_EMR_CMPMODE_IN (0x2u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is in the comparison window. */ |
| 558 | #define ADC_EMR_CMPMODE_OUT (0x3u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is out of the comparison window. */ |
| 559 | #define ADC_EMR_CMPSEL_Pos 4 |
| 560 | #define ADC_EMR_CMPSEL_Msk (0xfu << ADC_EMR_CMPSEL_Pos) /**< \brief (ADC_EMR) Comparison Selected Channel */ |
| 561 | #define ADC_EMR_CMPSEL(value) ((ADC_EMR_CMPSEL_Msk & ((value) << ADC_EMR_CMPSEL_Pos))) |
| 562 | #define ADC_EMR_CMPALL (0x1u << 9) /**< \brief (ADC_EMR) Compare All Channels */ |
| 563 | #define ADC_EMR_TAG (0x1u << 24) /**< \brief (ADC_EMR) TAG of ADC_LDCR register */ |
| 564 | /* -------- ADC_CWR : (ADC Offset: 0x44) Compare Window Register -------- */ |
| 565 | #define ADC_CWR_LOWTHRES_Pos 0 |
| 566 | #define ADC_CWR_LOWTHRES_Msk (0xfffu << ADC_CWR_LOWTHRES_Pos) /**< \brief (ADC_CWR) Low Threshold */ |
| 567 | #define ADC_CWR_LOWTHRES(value) ((ADC_CWR_LOWTHRES_Msk & ((value) << ADC_CWR_LOWTHRES_Pos))) |
| 568 | #define ADC_CWR_HIGHTHRES_Pos 16 |
| 569 | #define ADC_CWR_HIGHTHRES_Msk (0xfffu << ADC_CWR_HIGHTHRES_Pos) /**< \brief (ADC_CWR) High Threshold */ |
| 570 | #define ADC_CWR_HIGHTHRES(value) ((ADC_CWR_HIGHTHRES_Msk & ((value) << ADC_CWR_HIGHTHRES_Pos))) |
| 571 | /* -------- ADC_CGR : (ADC Offset: 0x48) Channel Gain Register -------- */ |
| 572 | #define ADC_CGR_GAIN0_Pos 0 |
| 573 | #define ADC_CGR_GAIN0_Msk (0x3u << ADC_CGR_GAIN0_Pos) /**< \brief (ADC_CGR) Gain for channel 0 */ |
| 574 | #define ADC_CGR_GAIN0(value) ((ADC_CGR_GAIN0_Msk & ((value) << ADC_CGR_GAIN0_Pos))) |
| 575 | #define ADC_CGR_GAIN1_Pos 2 |
| 576 | #define ADC_CGR_GAIN1_Msk (0x3u << ADC_CGR_GAIN1_Pos) /**< \brief (ADC_CGR) Gain for channel 1 */ |
| 577 | #define ADC_CGR_GAIN1(value) ((ADC_CGR_GAIN1_Msk & ((value) << ADC_CGR_GAIN1_Pos))) |
| 578 | #define ADC_CGR_GAIN2_Pos 4 |
| 579 | #define ADC_CGR_GAIN2_Msk (0x3u << ADC_CGR_GAIN2_Pos) /**< \brief (ADC_CGR) Gain for channel 2 */ |
| 580 | #define ADC_CGR_GAIN2(value) ((ADC_CGR_GAIN2_Msk & ((value) << ADC_CGR_GAIN2_Pos))) |
| 581 | #define ADC_CGR_GAIN3_Pos 6 |
| 582 | #define ADC_CGR_GAIN3_Msk (0x3u << ADC_CGR_GAIN3_Pos) /**< \brief (ADC_CGR) Gain for channel 3 */ |
| 583 | #define ADC_CGR_GAIN3(value) ((ADC_CGR_GAIN3_Msk & ((value) << ADC_CGR_GAIN3_Pos))) |
| 584 | #define ADC_CGR_GAIN4_Pos 8 |
| 585 | #define ADC_CGR_GAIN4_Msk (0x3u << ADC_CGR_GAIN4_Pos) /**< \brief (ADC_CGR) Gain for channel 4 */ |
| 586 | #define ADC_CGR_GAIN4(value) ((ADC_CGR_GAIN4_Msk & ((value) << ADC_CGR_GAIN4_Pos))) |
| 587 | #define ADC_CGR_GAIN5_Pos 10 |
| 588 | #define ADC_CGR_GAIN5_Msk (0x3u << ADC_CGR_GAIN5_Pos) /**< \brief (ADC_CGR) Gain for channel 5 */ |
| 589 | #define ADC_CGR_GAIN5(value) ((ADC_CGR_GAIN5_Msk & ((value) << ADC_CGR_GAIN5_Pos))) |
| 590 | #define ADC_CGR_GAIN6_Pos 12 |
| 591 | #define ADC_CGR_GAIN6_Msk (0x3u << ADC_CGR_GAIN6_Pos) /**< \brief (ADC_CGR) Gain for channel 6 */ |
| 592 | #define ADC_CGR_GAIN6(value) ((ADC_CGR_GAIN6_Msk & ((value) << ADC_CGR_GAIN6_Pos))) |
| 593 | #define ADC_CGR_GAIN7_Pos 14 |
| 594 | #define ADC_CGR_GAIN7_Msk (0x3u << ADC_CGR_GAIN7_Pos) /**< \brief (ADC_CGR) Gain for channel 7 */ |
| 595 | #define ADC_CGR_GAIN7(value) ((ADC_CGR_GAIN7_Msk & ((value) << ADC_CGR_GAIN7_Pos))) |
| 596 | #define ADC_CGR_GAIN8_Pos 16 |
| 597 | #define ADC_CGR_GAIN8_Msk (0x3u << ADC_CGR_GAIN8_Pos) /**< \brief (ADC_CGR) Gain for channel 8 */ |
| 598 | #define ADC_CGR_GAIN8(value) ((ADC_CGR_GAIN8_Msk & ((value) << ADC_CGR_GAIN8_Pos))) |
| 599 | #define ADC_CGR_GAIN9_Pos 18 |
| 600 | #define ADC_CGR_GAIN9_Msk (0x3u << ADC_CGR_GAIN9_Pos) /**< \brief (ADC_CGR) Gain for channel 9 */ |
| 601 | #define ADC_CGR_GAIN9(value) ((ADC_CGR_GAIN9_Msk & ((value) << ADC_CGR_GAIN9_Pos))) |
| 602 | #define ADC_CGR_GAIN10_Pos 20 |
| 603 | #define ADC_CGR_GAIN10_Msk (0x3u << ADC_CGR_GAIN10_Pos) /**< \brief (ADC_CGR) Gain for channel 10 */ |
| 604 | #define ADC_CGR_GAIN10(value) ((ADC_CGR_GAIN10_Msk & ((value) << ADC_CGR_GAIN10_Pos))) |
| 605 | #define ADC_CGR_GAIN11_Pos 22 |
| 606 | #define ADC_CGR_GAIN11_Msk (0x3u << ADC_CGR_GAIN11_Pos) /**< \brief (ADC_CGR) Gain for channel 11 */ |
| 607 | #define ADC_CGR_GAIN11(value) ((ADC_CGR_GAIN11_Msk & ((value) << ADC_CGR_GAIN11_Pos))) |
| 608 | #define ADC_CGR_GAIN12_Pos 24 |
| 609 | #define ADC_CGR_GAIN12_Msk (0x3u << ADC_CGR_GAIN12_Pos) /**< \brief (ADC_CGR) Gain for channel 12 */ |
| 610 | #define ADC_CGR_GAIN12(value) ((ADC_CGR_GAIN12_Msk & ((value) << ADC_CGR_GAIN12_Pos))) |
| 611 | #define ADC_CGR_GAIN13_Pos 26 |
| 612 | #define ADC_CGR_GAIN13_Msk (0x3u << ADC_CGR_GAIN13_Pos) /**< \brief (ADC_CGR) Gain for channel 13 */ |
| 613 | #define ADC_CGR_GAIN13(value) ((ADC_CGR_GAIN13_Msk & ((value) << ADC_CGR_GAIN13_Pos))) |
| 614 | #define ADC_CGR_GAIN14_Pos 28 |
| 615 | #define ADC_CGR_GAIN14_Msk (0x3u << ADC_CGR_GAIN14_Pos) /**< \brief (ADC_CGR) Gain for channel 14 */ |
| 616 | #define ADC_CGR_GAIN14(value) ((ADC_CGR_GAIN14_Msk & ((value) << ADC_CGR_GAIN14_Pos))) |
| 617 | #define ADC_CGR_GAIN15_Pos 30 |
| 618 | #define ADC_CGR_GAIN15_Msk (0x3u << ADC_CGR_GAIN15_Pos) /**< \brief (ADC_CGR) Gain for channel 15 */ |
| 619 | #define ADC_CGR_GAIN15(value) ((ADC_CGR_GAIN15_Msk & ((value) << ADC_CGR_GAIN15_Pos))) |
| 620 | /* -------- ADC_COR : (ADC Offset: 0x4C) Channel Offset Register -------- */ |
| 621 | #define ADC_COR_OFF0 (0x1u << 0) /**< \brief (ADC_COR) Offset for channel 0 */ |
| 622 | #define ADC_COR_OFF1 (0x1u << 1) /**< \brief (ADC_COR) Offset for channel 1 */ |
| 623 | #define ADC_COR_OFF2 (0x1u << 2) /**< \brief (ADC_COR) Offset for channel 2 */ |
| 624 | #define ADC_COR_OFF3 (0x1u << 3) /**< \brief (ADC_COR) Offset for channel 3 */ |
| 625 | #define ADC_COR_OFF4 (0x1u << 4) /**< \brief (ADC_COR) Offset for channel 4 */ |
| 626 | #define ADC_COR_OFF5 (0x1u << 5) /**< \brief (ADC_COR) Offset for channel 5 */ |
| 627 | #define ADC_COR_OFF6 (0x1u << 6) /**< \brief (ADC_COR) Offset for channel 6 */ |
| 628 | #define ADC_COR_OFF7 (0x1u << 7) /**< \brief (ADC_COR) Offset for channel 7 */ |
| 629 | #define ADC_COR_OFF8 (0x1u << 8) /**< \brief (ADC_COR) Offset for channel 8 */ |
| 630 | #define ADC_COR_OFF9 (0x1u << 9) /**< \brief (ADC_COR) Offset for channel 9 */ |
| 631 | #define ADC_COR_OFF10 (0x1u << 10) /**< \brief (ADC_COR) Offset for channel 10 */ |
| 632 | #define ADC_COR_OFF11 (0x1u << 11) /**< \brief (ADC_COR) Offset for channel 11 */ |
| 633 | #define ADC_COR_OFF12 (0x1u << 12) /**< \brief (ADC_COR) Offset for channel 12 */ |
| 634 | #define ADC_COR_OFF13 (0x1u << 13) /**< \brief (ADC_COR) Offset for channel 13 */ |
| 635 | #define ADC_COR_OFF14 (0x1u << 14) /**< \brief (ADC_COR) Offset for channel 14 */ |
| 636 | #define ADC_COR_OFF15 (0x1u << 15) /**< \brief (ADC_COR) Offset for channel 15 */ |
| 637 | #define ADC_COR_DIFF0 (0x1u << 16) /**< \brief (ADC_COR) Differential inputs for channel 0 */ |
| 638 | #define ADC_COR_DIFF1 (0x1u << 17) /**< \brief (ADC_COR) Differential inputs for channel 1 */ |
| 639 | #define ADC_COR_DIFF2 (0x1u << 18) /**< \brief (ADC_COR) Differential inputs for channel 2 */ |
| 640 | #define ADC_COR_DIFF3 (0x1u << 19) /**< \brief (ADC_COR) Differential inputs for channel 3 */ |
| 641 | #define ADC_COR_DIFF4 (0x1u << 20) /**< \brief (ADC_COR) Differential inputs for channel 4 */ |
| 642 | #define ADC_COR_DIFF5 (0x1u << 21) /**< \brief (ADC_COR) Differential inputs for channel 5 */ |
| 643 | #define ADC_COR_DIFF6 (0x1u << 22) /**< \brief (ADC_COR) Differential inputs for channel 6 */ |
| 644 | #define ADC_COR_DIFF7 (0x1u << 23) /**< \brief (ADC_COR) Differential inputs for channel 7 */ |
| 645 | #define ADC_COR_DIFF8 (0x1u << 24) /**< \brief (ADC_COR) Differential inputs for channel 8 */ |
| 646 | #define ADC_COR_DIFF9 (0x1u << 25) /**< \brief (ADC_COR) Differential inputs for channel 9 */ |
| 647 | #define ADC_COR_DIFF10 (0x1u << 26) /**< \brief (ADC_COR) Differential inputs for channel 10 */ |
| 648 | #define ADC_COR_DIFF11 (0x1u << 27) /**< \brief (ADC_COR) Differential inputs for channel 11 */ |
| 649 | #define ADC_COR_DIFF12 (0x1u << 28) /**< \brief (ADC_COR) Differential inputs for channel 12 */ |
| 650 | #define ADC_COR_DIFF13 (0x1u << 29) /**< \brief (ADC_COR) Differential inputs for channel 13 */ |
| 651 | #define ADC_COR_DIFF14 (0x1u << 30) /**< \brief (ADC_COR) Differential inputs for channel 14 */ |
| 652 | #define ADC_COR_DIFF15 (0x1u << 31) /**< \brief (ADC_COR) Differential inputs for channel 15 */ |
| 653 | /* -------- ADC_CDR[16] : (ADC Offset: 0x50) Channel Data Register -------- */ |
| 654 | #define ADC_CDR_DATA_Pos 0 |
| 655 | #define ADC_CDR_DATA_Msk (0x3ffu << ADC_CDR_DATA_Pos) /**< \brief (ADC_CDR[16]) Converted Data */ |
| 656 | /* -------- ADC_ACR : (ADC Offset: 0x94) Analog Control Register -------- */ |
| 657 | #define ADC_ACR_TSON (0x1u << 4) /**< \brief (ADC_ACR) Temperature Sensor On */ |
| 658 | #define ADC_ACR_IBCTL_Pos 8 |
| 659 | #define ADC_ACR_IBCTL_Msk (0x3u << ADC_ACR_IBCTL_Pos) /**< \brief (ADC_ACR) ADC Bias Current Control */ |
| 660 | #define ADC_ACR_IBCTL(value) ((ADC_ACR_IBCTL_Msk & ((value) << ADC_ACR_IBCTL_Pos))) |
| 661 | /* -------- ADC_WPMR : (ADC Offset: 0xE4) Write Protect Mode Register -------- */ |
| 662 | #define ADC_WPMR_WPEN (0x1u << 0) /**< \brief (ADC_WPMR) Write Protect Enable */ |
| 663 | #define ADC_WPMR_WPKEY_Pos 8 |
| 664 | #define ADC_WPMR_WPKEY_Msk (0xffffffu << ADC_WPMR_WPKEY_Pos) /**< \brief (ADC_WPMR) Write Protect KEY */ |
| 665 | #define ADC_WPMR_WPKEY(value) ((ADC_WPMR_WPKEY_Msk & ((value) << ADC_WPMR_WPKEY_Pos))) |
| 666 | /* -------- ADC_WPSR : (ADC Offset: 0xE8) Write Protect Status Register -------- */ |
| 667 | #define ADC_WPSR_WPVS (0x1u << 0) /**< \brief (ADC_WPSR) Write Protect Violation Status */ |
| 668 | #define ADC_WPSR_WPVSRC_Pos 8 |
| 669 | #define ADC_WPSR_WPVSRC_Msk (0xffffu << ADC_WPSR_WPVSRC_Pos) /**< \brief (ADC_WPSR) Write Protect Violation Source */ |
| 670 | /* -------- ADC_RPR : (ADC Offset: 0x100) Receive Pointer Register -------- */ |
| 671 | #define ADC_RPR_RXPTR_Pos 0 |
| 672 | #define ADC_RPR_RXPTR_Msk (0xffffffffu << ADC_RPR_RXPTR_Pos) /**< \brief (ADC_RPR) Receive Pointer Register */ |
| 673 | #define ADC_RPR_RXPTR(value) ((ADC_RPR_RXPTR_Msk & ((value) << ADC_RPR_RXPTR_Pos))) |
| 674 | /* -------- ADC_RCR : (ADC Offset: 0x104) Receive Counter Register -------- */ |
| 675 | #define ADC_RCR_RXCTR_Pos 0 |
| 676 | #define ADC_RCR_RXCTR_Msk (0xffffu << ADC_RCR_RXCTR_Pos) /**< \brief (ADC_RCR) Receive Counter Register */ |
| 677 | #define ADC_RCR_RXCTR(value) ((ADC_RCR_RXCTR_Msk & ((value) << ADC_RCR_RXCTR_Pos))) |
| 678 | /* -------- ADC_TPR : (ADC Offset: 0x108) Transmit Pointer Register -------- */ |
| 679 | #define ADC_TPR_TXPTR_Pos 0 |
| 680 | #define ADC_TPR_TXPTR_Msk (0xffffffffu << ADC_TPR_TXPTR_Pos) /**< \brief (ADC_TPR) Transmit Counter Register */ |
| 681 | #define ADC_TPR_TXPTR(value) ((ADC_TPR_TXPTR_Msk & ((value) << ADC_TPR_TXPTR_Pos))) |
| 682 | /* -------- ADC_TCR : (ADC Offset: 0x10C) Transmit Counter Register -------- */ |
| 683 | #define ADC_TCR_TXCTR_Pos 0 |
| 684 | #define ADC_TCR_TXCTR_Msk (0xffffu << ADC_TCR_TXCTR_Pos) /**< \brief (ADC_TCR) Transmit Counter Register */ |
| 685 | #define ADC_TCR_TXCTR(value) ((ADC_TCR_TXCTR_Msk & ((value) << ADC_TCR_TXCTR_Pos))) |
| 686 | /* -------- ADC_RNPR : (ADC Offset: 0x110) Receive Next Pointer Register -------- */ |
| 687 | #define ADC_RNPR_RXNPTR_Pos 0 |
| 688 | #define ADC_RNPR_RXNPTR_Msk (0xffffffffu << ADC_RNPR_RXNPTR_Pos) /**< \brief (ADC_RNPR) Receive Next Pointer */ |
| 689 | #define ADC_RNPR_RXNPTR(value) ((ADC_RNPR_RXNPTR_Msk & ((value) << ADC_RNPR_RXNPTR_Pos))) |
| 690 | /* -------- ADC_RNCR : (ADC Offset: 0x114) Receive Next Counter Register -------- */ |
| 691 | #define ADC_RNCR_RXNCTR_Pos 0 |
| 692 | #define ADC_RNCR_RXNCTR_Msk (0xffffu << ADC_RNCR_RXNCTR_Pos) /**< \brief (ADC_RNCR) Receive Next Counter */ |
| 693 | #define ADC_RNCR_RXNCTR(value) ((ADC_RNCR_RXNCTR_Msk & ((value) << ADC_RNCR_RXNCTR_Pos))) |
| 694 | /* -------- ADC_TNPR : (ADC Offset: 0x118) Transmit Next Pointer Register -------- */ |
| 695 | #define ADC_TNPR_TXNPTR_Pos 0 |
| 696 | #define ADC_TNPR_TXNPTR_Msk (0xffffffffu << ADC_TNPR_TXNPTR_Pos) /**< \brief (ADC_TNPR) Transmit Next Pointer */ |
| 697 | #define ADC_TNPR_TXNPTR(value) ((ADC_TNPR_TXNPTR_Msk & ((value) << ADC_TNPR_TXNPTR_Pos))) |
| 698 | /* -------- ADC_TNCR : (ADC Offset: 0x11C) Transmit Next Counter Register -------- */ |
| 699 | #define ADC_TNCR_TXNCTR_Pos 0 |
| 700 | #define ADC_TNCR_TXNCTR_Msk (0xffffu << ADC_TNCR_TXNCTR_Pos) /**< \brief (ADC_TNCR) Transmit Counter Next */ |
| 701 | #define ADC_TNCR_TXNCTR(value) ((ADC_TNCR_TXNCTR_Msk & ((value) << ADC_TNCR_TXNCTR_Pos))) |
| 702 | /* -------- ADC_PTCR : (ADC Offset: 0x120) Transfer Control Register -------- */ |
| 703 | #define ADC_PTCR_RXTEN (0x1u << 0) /**< \brief (ADC_PTCR) Receiver Transfer Enable */ |
| 704 | #define ADC_PTCR_RXTDIS (0x1u << 1) /**< \brief (ADC_PTCR) Receiver Transfer Disable */ |
| 705 | #define ADC_PTCR_TXTEN (0x1u << 8) /**< \brief (ADC_PTCR) Transmitter Transfer Enable */ |
| 706 | #define ADC_PTCR_TXTDIS (0x1u << 9) /**< \brief (ADC_PTCR) Transmitter Transfer Disable */ |
| 707 | /* -------- ADC_PTSR : (ADC Offset: 0x124) Transfer Status Register -------- */ |
| 708 | #define ADC_PTSR_RXTEN (0x1u << 0) /**< \brief (ADC_PTSR) Receiver Transfer Enable */ |
| 709 | #define ADC_PTSR_TXTEN (0x1u << 8) /**< \brief (ADC_PTSR) Transmitter Transfer Enable */ |
| 710 | |
| 711 | /*@}*/ |
| 712 | |
| 713 | /* ============================================================================= */ |
| 714 | /** SOFTWARE API DEFINITION FOR Chip Identifier */ |
| 715 | /* ============================================================================= */ |
| 716 | /** \addtogroup SAM3S_CHIPID Chip Identifier */ |
| 717 | /*@{*/ |
| 718 | |
| 719 | #ifndef __ASSEMBLY__ |
| 720 | /** \brief Chipid hardware registers */ |
| 721 | typedef struct { |
| 722 | RoReg CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */ |
| 723 | RoReg CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */ |
| 724 | } Chipid; |
| 725 | #endif /* __ASSEMBLY__ */ |
| 726 | /* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */ |
| 727 | #define CHIPID_CIDR_VERSION_Pos 0 |
| 728 | #define CHIPID_CIDR_VERSION_Msk (0x1fu << CHIPID_CIDR_VERSION_Pos) /**< \brief (CHIPID_CIDR) Version of the Device */ |
| 729 | #define CHIPID_CIDR_EPROC_Pos 5 |
| 730 | #define CHIPID_CIDR_EPROC_Msk (0x7u << CHIPID_CIDR_EPROC_Pos) /**< \brief (CHIPID_CIDR) Embedded Processor */ |
| 731 | #define CHIPID_CIDR_EPROC_ARM946ES (0x1u << 5) /**< \brief (CHIPID_CIDR) ARM946ES */ |
| 732 | #define CHIPID_CIDR_EPROC_ARM7TDMI (0x2u << 5) /**< \brief (CHIPID_CIDR) ARM7TDMI */ |
| 733 | #define CHIPID_CIDR_EPROC_CM3 (0x3u << 5) /**< \brief (CHIPID_CIDR) Cortex-M3 */ |
| 734 | #define CHIPID_CIDR_EPROC_ARM920T (0x4u << 5) /**< \brief (CHIPID_CIDR) ARM920T */ |
| 735 | #define CHIPID_CIDR_EPROC_ARM926EJS (0x5u << 5) /**< \brief (CHIPID_CIDR) ARM926EJS */ |
| 736 | #define CHIPID_CIDR_EPROC_CA5 (0x6u << 5) /**< \brief (CHIPID_CIDR) Cortex-A5 */ |
| 737 | #define CHIPID_CIDR_NVPSIZ_Pos 8 |
| 738 | #define CHIPID_CIDR_NVPSIZ_Msk (0xfu << CHIPID_CIDR_NVPSIZ_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */ |
| 739 | #define CHIPID_CIDR_NVPSIZ_NONE (0x0u << 8) /**< \brief (CHIPID_CIDR) None */ |
| 740 | #define CHIPID_CIDR_NVPSIZ_8K (0x1u << 8) /**< \brief (CHIPID_CIDR) 8K bytes */ |
| 741 | #define CHIPID_CIDR_NVPSIZ_16K (0x2u << 8) /**< \brief (CHIPID_CIDR) 16K bytes */ |
| 742 | #define CHIPID_CIDR_NVPSIZ_32K (0x3u << 8) /**< \brief (CHIPID_CIDR) 32K bytes */ |
| 743 | #define CHIPID_CIDR_NVPSIZ_64K (0x5u << 8) /**< \brief (CHIPID_CIDR) 64K bytes */ |
| 744 | #define CHIPID_CIDR_NVPSIZ_128K (0x7u << 8) /**< \brief (CHIPID_CIDR) 128K bytes */ |
| 745 | #define CHIPID_CIDR_NVPSIZ_256K (0x9u << 8) /**< \brief (CHIPID_CIDR) 256K bytes */ |
| 746 | #define CHIPID_CIDR_NVPSIZ_512K (0xAu << 8) /**< \brief (CHIPID_CIDR) 512K bytes */ |
| 747 | #define CHIPID_CIDR_NVPSIZ_1024K (0xCu << 8) /**< \brief (CHIPID_CIDR) 1024K bytes */ |
| 748 | #define CHIPID_CIDR_NVPSIZ_2048K (0xEu << 8) /**< \brief (CHIPID_CIDR) 2048K bytes */ |
| 749 | #define CHIPID_CIDR_NVPSIZ2_Pos 12 |
| 750 | #define CHIPID_CIDR_NVPSIZ2_Msk (0xfu << CHIPID_CIDR_NVPSIZ2_Pos) /**< \brief (CHIPID_CIDR) */ |
| 751 | #define CHIPID_CIDR_NVPSIZ2_NONE (0x0u << 12) /**< \brief (CHIPID_CIDR) None */ |
| 752 | #define CHIPID_CIDR_NVPSIZ2_8K (0x1u << 12) /**< \brief (CHIPID_CIDR) 8K bytes */ |
| 753 | #define CHIPID_CIDR_NVPSIZ2_16K (0x2u << 12) /**< \brief (CHIPID_CIDR) 16K bytes */ |
| 754 | #define CHIPID_CIDR_NVPSIZ2_32K (0x3u << 12) /**< \brief (CHIPID_CIDR) 32K bytes */ |
| 755 | #define CHIPID_CIDR_NVPSIZ2_64K (0x5u << 12) /**< \brief (CHIPID_CIDR) 64K bytes */ |
| 756 | #define CHIPID_CIDR_NVPSIZ2_128K (0x7u << 12) /**< \brief (CHIPID_CIDR) 128K bytes */ |
| 757 | #define CHIPID_CIDR_NVPSIZ2_256K (0x9u << 12) /**< \brief (CHIPID_CIDR) 256K bytes */ |
| 758 | #define CHIPID_CIDR_NVPSIZ2_512K (0xAu << 12) /**< \brief (CHIPID_CIDR) 512K bytes */ |
| 759 | #define CHIPID_CIDR_NVPSIZ2_1024K (0xCu << 12) /**< \brief (CHIPID_CIDR) 1024K bytes */ |
| 760 | #define CHIPID_CIDR_NVPSIZ2_2048K (0xEu << 12) /**< \brief (CHIPID_CIDR) 2048K bytes */ |
| 761 | #define CHIPID_CIDR_SRAMSIZ_Pos 16 |
| 762 | #define CHIPID_CIDR_SRAMSIZ_Msk (0xfu << CHIPID_CIDR_SRAMSIZ_Pos) /**< \brief (CHIPID_CIDR) Internal SRAM Size */ |
| 763 | #define CHIPID_CIDR_SRAMSIZ_48K (0x0u << 16) /**< \brief (CHIPID_CIDR) 48K bytes */ |
| 764 | #define CHIPID_CIDR_SRAMSIZ_1K (0x1u << 16) /**< \brief (CHIPID_CIDR) 1K bytes */ |
| 765 | #define CHIPID_CIDR_SRAMSIZ_2K (0x2u << 16) /**< \brief (CHIPID_CIDR) 2K bytes */ |
| 766 | #define CHIPID_CIDR_SRAMSIZ_6K (0x3u << 16) /**< \brief (CHIPID_CIDR) 6K bytes */ |
| 767 | #define CHIPID_CIDR_SRAMSIZ_112K (0x4u << 16) /**< \brief (CHIPID_CIDR) 112K bytes */ |
| 768 | #define CHIPID_CIDR_SRAMSIZ_4K (0x5u << 16) /**< \brief (CHIPID_CIDR) 4K bytes */ |
| 769 | #define CHIPID_CIDR_SRAMSIZ_80K (0x6u << 16) /**< \brief (CHIPID_CIDR) 80K bytes */ |
| 770 | #define CHIPID_CIDR_SRAMSIZ_160K (0x7u << 16) /**< \brief (CHIPID_CIDR) 160K bytes */ |
| 771 | #define CHIPID_CIDR_SRAMSIZ_8K (0x8u << 16) /**< \brief (CHIPID_CIDR) 8K bytes */ |
| 772 | #define CHIPID_CIDR_SRAMSIZ_16K (0x9u << 16) /**< \brief (CHIPID_CIDR) 16K bytes */ |
| 773 | #define CHIPID_CIDR_SRAMSIZ_32K (0xAu << 16) /**< \brief (CHIPID_CIDR) 32K bytes */ |
| 774 | #define CHIPID_CIDR_SRAMSIZ_64K (0xBu << 16) /**< \brief (CHIPID_CIDR) 64K bytes */ |
| 775 | #define CHIPID_CIDR_SRAMSIZ_128K (0xCu << 16) /**< \brief (CHIPID_CIDR) 128K bytes */ |
| 776 | #define CHIPID_CIDR_SRAMSIZ_256K (0xDu << 16) /**< \brief (CHIPID_CIDR) 256K bytes */ |
| 777 | #define CHIPID_CIDR_SRAMSIZ_96K (0xEu << 16) /**< \brief (CHIPID_CIDR) 96K bytes */ |
| 778 | #define CHIPID_CIDR_SRAMSIZ_512K (0xFu << 16) /**< \brief (CHIPID_CIDR) 512K bytes */ |
| 779 | #define CHIPID_CIDR_ARCH_Pos 20 |
| 780 | #define CHIPID_CIDR_ARCH_Msk (0xffu << CHIPID_CIDR_ARCH_Pos) /**< \brief (CHIPID_CIDR) Architecture Identifier */ |
| 781 | #define CHIPID_CIDR_ARCH_AT91SAM9xx (0x19u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9xx Series */ |
| 782 | #define CHIPID_CIDR_ARCH_AT91SAM9XExx (0x29u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9XExx Series */ |
| 783 | #define CHIPID_CIDR_ARCH_AT91x34 (0x34u << 20) /**< \brief (CHIPID_CIDR) AT91x34 Series */ |
| 784 | #define CHIPID_CIDR_ARCH_CAP7 (0x37u << 20) /**< \brief (CHIPID_CIDR) CAP7 Series */ |
| 785 | #define CHIPID_CIDR_ARCH_CAP9 (0x39u << 20) /**< \brief (CHIPID_CIDR) CAP9 Series */ |
| 786 | #define CHIPID_CIDR_ARCH_CAP11 (0x3Bu << 20) /**< \brief (CHIPID_CIDR) CAP11 Series */ |
| 787 | #define CHIPID_CIDR_ARCH_AT91x40 (0x40u << 20) /**< \brief (CHIPID_CIDR) AT91x40 Series */ |
| 788 | #define CHIPID_CIDR_ARCH_AT91x42 (0x42u << 20) /**< \brief (CHIPID_CIDR) AT91x42 Series */ |
| 789 | #define CHIPID_CIDR_ARCH_AT91x55 (0x55u << 20) /**< \brief (CHIPID_CIDR) AT91x55 Series */ |
| 790 | #define CHIPID_CIDR_ARCH_AT91SAM7Axx (0x60u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Axx Series */ |
| 791 | #define CHIPID_CIDR_ARCH_AT91SAM7AQxx (0x61u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7AQxx Series */ |
| 792 | #define CHIPID_CIDR_ARCH_AT91x63 (0x63u << 20) /**< \brief (CHIPID_CIDR) AT91x63 Series */ |
| 793 | #define CHIPID_CIDR_ARCH_AT91SAM7Sxx (0x70u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Sxx Series */ |
| 794 | #define CHIPID_CIDR_ARCH_AT91SAM7XCxx (0x71u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7XCxx Series */ |
| 795 | #define CHIPID_CIDR_ARCH_AT91SAM7SExx (0x72u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SExx Series */ |
| 796 | #define CHIPID_CIDR_ARCH_AT91SAM7Lxx (0x73u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Lxx Series */ |
| 797 | #define CHIPID_CIDR_ARCH_AT91SAM7Xxx (0x75u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Xxx Series */ |
| 798 | #define CHIPID_CIDR_ARCH_AT91SAM7SLxx (0x76u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SLxx Series */ |
| 799 | #define CHIPID_CIDR_ARCH_SAM3UxC (0x80u << 20) /**< \brief (CHIPID_CIDR) SAM3UxC Series (100-pin version) */ |
| 800 | #define CHIPID_CIDR_ARCH_SAM3UxE (0x81u << 20) /**< \brief (CHIPID_CIDR) SAM3UxE Series (144-pin version) */ |
| 801 | #define CHIPID_CIDR_ARCH_SAM3AxC (0x83u << 20) /**< \brief (CHIPID_CIDR) SAM3AxC Series (100-pin version) */ |
| 802 | #define CHIPID_CIDR_ARCH_SAM3XxC (0x84u << 20) /**< \brief (CHIPID_CIDR) SAM3XxC Series (100-pin version) */ |
| 803 | #define CHIPID_CIDR_ARCH_SAM3XxE (0x85u << 20) /**< \brief (CHIPID_CIDR) SAM3XxE Series (144-pin version) */ |
| 804 | #define CHIPID_CIDR_ARCH_SAM3XxG (0x86u << 20) /**< \brief (CHIPID_CIDR) SAM3XxG Series (208/217-pin version) */ |
| 805 | #define CHIPID_CIDR_ARCH_SAM3SxA (0x88u << 20) /**< \brief (CHIPID_CIDR) SAM3SxA Series (48-pin version) */ |
| 806 | #define CHIPID_CIDR_ARCH_SAM3SxB (0x89u << 20) /**< \brief (CHIPID_CIDR) SAM3SxB Series (64-pin version) */ |
| 807 | #define CHIPID_CIDR_ARCH_SAM3SxC (0x8Au << 20) /**< \brief (CHIPID_CIDR) SAM3SxC Series (100-pin version) */ |
| 808 | #define CHIPID_CIDR_ARCH_AT91x92 (0x92u << 20) /**< \brief (CHIPID_CIDR) AT91x92 Series */ |
| 809 | #define CHIPID_CIDR_ARCH_SAM3NxA (0x93u << 20) /**< \brief (CHIPID_CIDR) SAM3NxA Series (48-pin version) */ |
| 810 | #define CHIPID_CIDR_ARCH_SAM3NxB (0x94u << 20) /**< \brief (CHIPID_CIDR) SAM3NxB Series (64-pin version) */ |
| 811 | #define CHIPID_CIDR_ARCH_SAM3NxC (0x95u << 20) /**< \brief (CHIPID_CIDR) SAM3NxC Series (100-pin version) */ |
| 812 | #define CHIPID_CIDR_ARCH_SAM3SDxA (0x98u << 20) /**< \brief (CHIPID_CIDR) SAM3SDxA Series (48-pin version) */ |
| 813 | #define CHIPID_CIDR_ARCH_SAM3SDxB (0x99u << 20) /**< \brief (CHIPID_CIDR) SAM3SDxB Series (64-pin version) */ |
| 814 | #define CHIPID_CIDR_ARCH_SAM3SDxC (0x9Au << 20) /**< \brief (CHIPID_CIDR) SAM3SDxC Series (100-pin version) */ |
| 815 | #define CHIPID_CIDR_ARCH_SAM5A (0xA5u << 20) /**< \brief (CHIPID_CIDR) SAM5A */ |
| 816 | #define CHIPID_CIDR_ARCH_AT75Cxx (0xF0u << 20) /**< \brief (CHIPID_CIDR) AT75Cxx Series */ |
| 817 | #define CHIPID_CIDR_NVPTYP_Pos 28 |
| 818 | #define CHIPID_CIDR_NVPTYP_Msk (0x7u << CHIPID_CIDR_NVPTYP_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */ |
| 819 | #define CHIPID_CIDR_NVPTYP_ROM (0x0u << 28) /**< \brief (CHIPID_CIDR) ROM */ |
| 820 | #define CHIPID_CIDR_NVPTYP_ROMLESS (0x1u << 28) /**< \brief (CHIPID_CIDR) ROMless or on-chip Flash */ |
| 821 | #define CHIPID_CIDR_NVPTYP_FLASH (0x2u << 28) /**< \brief (CHIPID_CIDR) Embedded Flash Memory */ |
| 822 | #define CHIPID_CIDR_NVPTYP_ROM_FLASH (0x3u << 28) /**< \brief (CHIPID_CIDR) ROM and Embedded Flash MemoryNVPSIZ is ROM size NVPSIZ2 is Flash size */ |
| 823 | #define CHIPID_CIDR_NVPTYP_SRAM (0x4u << 28) /**< \brief (CHIPID_CIDR) SRAM emulating ROM */ |
| 824 | #define CHIPID_CIDR_EXT (0x1u << 31) /**< \brief (CHIPID_CIDR) Extension Flag */ |
| 825 | /* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */ |
| 826 | #define CHIPID_EXID_EXID_Pos 0 |
| 827 | #define CHIPID_EXID_EXID_Msk (0xffffffffu << CHIPID_EXID_EXID_Pos) /**< \brief (CHIPID_EXID) Chip ID Extension */ |
| 828 | |
| 829 | /*@}*/ |
| 830 | |
| 831 | /* ============================================================================= */ |
| 832 | /** SOFTWARE API DEFINITION FOR Cyclic Redundancy Check Calculation Unit */ |
| 833 | /* ============================================================================= */ |
| 834 | /** \addtogroup SAM3S_CRCCU Cyclic Redundancy Check Calculation Unit */ |
| 835 | /*@{*/ |
| 836 | |
| 837 | #ifndef __ASSEMBLY__ |
| 838 | /** \brief Crccu hardware registers */ |
| 839 | typedef struct { |
| 840 | RwReg CRCCU_DSCR; /**< \brief (Crccu Offset: 0x00000000) CRCCU Descriptor Base Register */ |
| 841 | RwReg Reserved1[1]; |
| 842 | WoReg CRCCU_DMA_EN; /**< \brief (Crccu Offset: 0x00000008) CRCCU DMA Enable Register */ |
| 843 | WoReg CRCCU_DMA_DIS; /**< \brief (Crccu Offset: 0x0000000C) CRCCU DMA Disable Register */ |
| 844 | RoReg CRCCU_DMA_SR; /**< \brief (Crccu Offset: 0x00000010) CRCCU DMA Status Register */ |
| 845 | WoReg CRCCU_DMA_IER; /**< \brief (Crccu Offset: 0x00000014) CRCCU DMA Interrupt Enable Register */ |
| 846 | WoReg CRCCU_DMA_IDR; /**< \brief (Crccu Offset: 0x00000018) CRCCU DMA Interrupt Disable Register */ |
| 847 | RoReg CRCCU_DMA_IMR; /**< \brief (Crccu Offset: 0x0000001C) CRCCU DMA Interrupt Mask Register */ |
| 848 | RoReg CRCCU_DMA_ISR; /**< \brief (Crccu Offset: 0x00000020) CRCCU DMA Interrupt Status Register */ |
| 849 | RwReg Reserved2[4]; |
| 850 | WoReg CRCCU_CR; /**< \brief (Crccu Offset: 0x00000034) CRCCU Control Register */ |
| 851 | RwReg CRCCU_MR; /**< \brief (Crccu Offset: 0x00000038) CRCCU Mode Register */ |
| 852 | RoReg CRCCU_SR; /**< \brief (Crccu Offset: 0x0000003C) CRCCU Status Register */ |
| 853 | WoReg CRCCU_IER; /**< \brief (Crccu Offset: 0x00000040) CRCCU Interrupt Enable Register */ |
| 854 | WoReg CRCCU_IDR; /**< \brief (Crccu Offset: 0x00000044) CRCCU Interrupt Disable Register */ |
| 855 | RoReg CRCCU_IMR; /**< \brief (Crccu Offset: 0x00000048) CRCCU Interrupt Mask Register */ |
| 856 | RoReg CRCCU_ISR; /**< \brief (Crccu Offset: 0x0000004C) CRCCU Interrupt Status Register */ |
| 857 | } Crccu; |
| 858 | #endif /* __ASSEMBLY__ */ |
| 859 | /* -------- CRCCU_DSCR : (CRCCU Offset: 0x00000000) CRCCU Descriptor Base Register -------- */ |
| 860 | #define CRCCU_DSCR_DSCR_Pos 9 |
| 861 | #define CRCCU_DSCR_DSCR_Msk (0x7fffffu << CRCCU_DSCR_DSCR_Pos) /**< \brief (CRCCU_DSCR) Descriptor Base Address */ |
| 862 | #define CRCCU_DSCR_DSCR(value) ((CRCCU_DSCR_DSCR_Msk & ((value) << CRCCU_DSCR_DSCR_Pos))) |
| 863 | /* -------- CRCCU_DMA_EN : (CRCCU Offset: 0x00000008) CRCCU DMA Enable Register -------- */ |
| 864 | #define CRCCU_DMA_EN_DMAEN (0x1u << 0) /**< \brief (CRCCU_DMA_EN) DMA Enable Register */ |
| 865 | /* -------- CRCCU_DMA_DIS : (CRCCU Offset: 0x0000000C) CRCCU DMA Disable Register -------- */ |
| 866 | #define CRCCU_DMA_DIS_DMADIS (0x1u << 0) /**< \brief (CRCCU_DMA_DIS) DMA Disable Register */ |
| 867 | /* -------- CRCCU_DMA_SR : (CRCCU Offset: 0x00000010) CRCCU DMA Status Register -------- */ |
| 868 | #define CRCCU_DMA_SR_DMASR (0x1u << 0) /**< \brief (CRCCU_DMA_SR) DMA Status Register */ |
| 869 | /* -------- CRCCU_DMA_IER : (CRCCU Offset: 0x00000014) CRCCU DMA Interrupt Enable Register -------- */ |
| 870 | #define CRCCU_DMA_IER_DMAIER (0x1u << 0) /**< \brief (CRCCU_DMA_IER) Interrupt Enable register */ |
| 871 | /* -------- CRCCU_DMA_IDR : (CRCCU Offset: 0x00000018) CRCCU DMA Interrupt Disable Register -------- */ |
| 872 | #define CRCCU_DMA_IDR_DMAIDR (0x1u << 0) /**< \brief (CRCCU_DMA_IDR) Interrupt Disable register */ |
| 873 | /* -------- CRCCU_DMA_IMR : (CRCCU Offset: 0x0000001C) CRCCU DMA Interrupt Mask Register -------- */ |
| 874 | #define CRCCU_DMA_IMR_DMAIMR (0x1u << 0) /**< \brief (CRCCU_DMA_IMR) Interrupt Mask Register */ |
| 875 | /* -------- CRCCU_DMA_ISR : (CRCCU Offset: 0x00000020) CRCCU DMA Interrupt Status Register -------- */ |
| 876 | #define CRCCU_DMA_ISR_DMAISR (0x1u << 0) /**< \brief (CRCCU_DMA_ISR) Interrupt Status register */ |
| 877 | /* -------- CRCCU_CR : (CRCCU Offset: 0x00000034) CRCCU Control Register -------- */ |
| 878 | #define CRCCU_CR_RESET (0x1u << 0) /**< \brief (CRCCU_CR) CRC Computation Reset */ |
| 879 | /* -------- CRCCU_MR : (CRCCU Offset: 0x00000038) CRCCU Mode Register -------- */ |
| 880 | #define CRCCU_MR_ENABLE (0x1u << 0) /**< \brief (CRCCU_MR) CRC Enable */ |
| 881 | #define CRCCU_MR_COMPARE (0x1u << 1) /**< \brief (CRCCU_MR) CRC Compare */ |
| 882 | #define CRCCU_MR_PTYPE_Pos 2 |
| 883 | #define CRCCU_MR_PTYPE_Msk (0x3u << CRCCU_MR_PTYPE_Pos) /**< \brief (CRCCU_MR) Primitive Polynomial */ |
| 884 | #define CRCCU_MR_PTYPE_CCIT8023 (0x0u << 2) /**< \brief (CRCCU_MR) Polynom 0x04C11DB7 */ |
| 885 | #define CRCCU_MR_PTYPE_CASTAGNOLI (0x1u << 2) /**< \brief (CRCCU_MR) Polynom 0x1EDC6F41 */ |
| 886 | #define CRCCU_MR_PTYPE_CCIT16 (0x2u << 2) /**< \brief (CRCCU_MR) Polynom 0x1021 */ |
| 887 | #define CRCCU_MR_DIVIDER_Pos 4 |
| 888 | #define CRCCU_MR_DIVIDER_Msk (0xfu << CRCCU_MR_DIVIDER_Pos) /**< \brief (CRCCU_MR) Request Divider */ |
| 889 | #define CRCCU_MR_DIVIDER(value) ((CRCCU_MR_DIVIDER_Msk & ((value) << CRCCU_MR_DIVIDER_Pos))) |
| 890 | /* -------- CRCCU_SR : (CRCCU Offset: 0x0000003C) CRCCU Status Register -------- */ |
| 891 | #define CRCCU_SR_CRC_Pos 0 |
| 892 | #define CRCCU_SR_CRC_Msk (0xffffffffu << CRCCU_SR_CRC_Pos) /**< \brief (CRCCU_SR) Cyclic Redundancy Check Value */ |
| 893 | /* -------- CRCCU_IER : (CRCCU Offset: 0x00000040) CRCCU Interrupt Enable Register -------- */ |
| 894 | #define CRCCU_IER_ERRIER (0x1u << 0) /**< \brief (CRCCU_IER) CRC Error Interrupt Enable */ |
| 895 | /* -------- CRCCU_IDR : (CRCCU Offset: 0x00000044) CRCCU Interrupt Disable Register -------- */ |
| 896 | #define CRCCU_IDR_ERRIDR (0x1u << 0) /**< \brief (CRCCU_IDR) CRC Error Interrupt Disable */ |
| 897 | /* -------- CRCCU_IMR : (CRCCU Offset: 0x00000048) CRCCU Interrupt Mask Register -------- */ |
| 898 | #define CRCCU_IMR_ERRIMR (0x1u << 0) /**< \brief (CRCCU_IMR) CRC Error Interrupt Mask */ |
| 899 | /* -------- CRCCU_ISR : (CRCCU Offset: 0x0000004C) CRCCU Interrupt Status Register -------- */ |
| 900 | #define CRCCU_ISR_ERRISR (0x1u << 0) /**< \brief (CRCCU_ISR) CRC Error Interrupt Status */ |
| 901 | |
| 902 | /*@}*/ |
| 903 | |
| 904 | /* ============================================================================= */ |
| 905 | /** SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller */ |
| 906 | /* ============================================================================= */ |
| 907 | /** \addtogroup SAM3S_DACC Digital-to-Analog Converter Controller */ |
| 908 | /*@{*/ |
| 909 | |
| 910 | #ifndef __ASSEMBLY__ |
| 911 | /** \brief Dacc hardware registers */ |
| 912 | typedef struct { |
| 913 | WoReg DACC_CR; /**< \brief (Dacc Offset: 0x00) Control Register */ |
| 914 | RwReg DACC_MR; /**< \brief (Dacc Offset: 0x04) Mode Register */ |
| 915 | RwReg Reserved1[2]; |
| 916 | WoReg DACC_CHER; /**< \brief (Dacc Offset: 0x10) Channel Enable Register */ |
| 917 | WoReg DACC_CHDR; /**< \brief (Dacc Offset: 0x14) Channel Disable Register */ |
| 918 | RoReg DACC_CHSR; /**< \brief (Dacc Offset: 0x18) Channel Status Register */ |
| 919 | RwReg Reserved2[1]; |
| 920 | WoReg DACC_CDR; /**< \brief (Dacc Offset: 0x20) Conversion Data Register */ |
| 921 | WoReg DACC_IER; /**< \brief (Dacc Offset: 0x24) Interrupt Enable Register */ |
| 922 | WoReg DACC_IDR; /**< \brief (Dacc Offset: 0x28) Interrupt Disable Register */ |
| 923 | RoReg DACC_IMR; /**< \brief (Dacc Offset: 0x2C) Interrupt Mask Register */ |
| 924 | RoReg DACC_ISR; /**< \brief (Dacc Offset: 0x30) Interrupt Status Register */ |
| 925 | RwReg Reserved3[24]; |
| 926 | RwReg DACC_ACR; /**< \brief (Dacc Offset: 0x94) Analog Current Register */ |
| 927 | RwReg Reserved4[19]; |
| 928 | RwReg DACC_WPMR; /**< \brief (Dacc Offset: 0xE4) Write Protect Mode register */ |
| 929 | RoReg DACC_WPSR; /**< \brief (Dacc Offset: 0xE8) Write Protect Status register */ |
| 930 | RwReg Reserved5[5]; |
| 931 | RwReg DACC_RPR; /**< \brief (Dacc Offset: 0x100) Receive Pointer Register */ |
| 932 | RwReg DACC_RCR; /**< \brief (Dacc Offset: 0x104) Receive Counter Register */ |
| 933 | RwReg DACC_TPR; /**< \brief (Dacc Offset: 0x108) Transmit Pointer Register */ |
| 934 | RwReg DACC_TCR; /**< \brief (Dacc Offset: 0x10C) Transmit Counter Register */ |
| 935 | RwReg DACC_RNPR; /**< \brief (Dacc Offset: 0x110) Receive Next Pointer Register */ |
| 936 | RwReg DACC_RNCR; /**< \brief (Dacc Offset: 0x114) Receive Next Counter Register */ |
| 937 | RwReg DACC_TNPR; /**< \brief (Dacc Offset: 0x118) Transmit Next Pointer Register */ |
| 938 | RwReg DACC_TNCR; /**< \brief (Dacc Offset: 0x11C) Transmit Next Counter Register */ |
| 939 | WoReg DACC_PTCR; /**< \brief (Dacc Offset: 0x120) Transfer Control Register */ |
| 940 | RoReg DACC_PTSR; /**< \brief (Dacc Offset: 0x124) Transfer Status Register */ |
| 941 | } Dacc; |
| 942 | #endif /* __ASSEMBLY__ */ |
| 943 | /* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */ |
| 944 | #define DACC_CR_SWRST (0x1u << 0) /**< \brief (DACC_CR) Software Reset */ |
| 945 | /* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */ |
| 946 | #define DACC_MR_TRGEN (0x1u << 0) /**< \brief (DACC_MR) Trigger Enable */ |
| 947 | #define DACC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (DACC_MR) External trigger mode disabled. DACC in free running mode. */ |
| 948 | #define DACC_MR_TRGEN_EN (0x1u << 0) /**< \brief (DACC_MR) External trigger mode enabled. */ |
| 949 | #define DACC_MR_TRGSEL_Pos 1 |
| 950 | #define DACC_MR_TRGSEL_Msk (0x7u << DACC_MR_TRGSEL_Pos) /**< \brief (DACC_MR) Trigger Selection */ |
| 951 | #define DACC_MR_TRGSEL(value) ((DACC_MR_TRGSEL_Msk & ((value) << DACC_MR_TRGSEL_Pos))) |
| 952 | #define DACC_MR_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer */ |
| 953 | #define DACC_MR_WORD_HALF (0x0u << 4) /**< \brief (DACC_MR) Half-Word transfer */ |
| 954 | #define DACC_MR_WORD_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer */ |
| 955 | #define DACC_MR_SLEEP (0x1u << 5) /**< \brief (DACC_MR) Sleep Mode */ |
| 956 | #define DACC_MR_FASTWKUP (0x1u << 6) /**< \brief (DACC_MR) Fast Wake up Mode */ |
| 957 | #define DACC_MR_REFRESH_Pos 8 |
| 958 | #define DACC_MR_REFRESH_Msk (0xffu << DACC_MR_REFRESH_Pos) /**< \brief (DACC_MR) Refresh Period */ |
| 959 | #define DACC_MR_REFRESH(value) ((DACC_MR_REFRESH_Msk & ((value) << DACC_MR_REFRESH_Pos))) |
| 960 | #define DACC_MR_USER_SEL_Pos 16 |
| 961 | #define DACC_MR_USER_SEL_Msk (0x3u << DACC_MR_USER_SEL_Pos) /**< \brief (DACC_MR) User Channel Selection */ |
| 962 | #define DACC_MR_USER_SEL_CHANNEL0 (0x0u << 16) /**< \brief (DACC_MR) Channel 0 */ |
| 963 | #define DACC_MR_USER_SEL_CHANNEL1 (0x1u << 16) /**< \brief (DACC_MR) Channel 1 */ |
| 964 | #define DACC_MR_TAG (0x1u << 20) /**< \brief (DACC_MR) Tag Selection Mode */ |
| 965 | #define DACC_MR_TAG_DIS (0x0u << 20) /**< \brief (DACC_MR) Tag selection mode disabled. Using USER_SEL to select the channel for the conversion */ |
| 966 | #define DACC_MR_TAG_EN (0x1u << 20) /**< \brief (DACC_MR) Tag selection mode enabled */ |
| 967 | #define DACC_MR_MAXS (0x1u << 21) /**< \brief (DACC_MR) Max Speed Mode */ |
| 968 | #define DACC_MR_STARTUP_Pos 24 |
| 969 | #define DACC_MR_STARTUP_Msk (0x3fu << DACC_MR_STARTUP_Pos) /**< \brief (DACC_MR) Startup Time Selection */ |
| 970 | #define DACC_MR_STARTUP_0 (0x0u << 24) /**< \brief (DACC_MR) 0 periods of DACClock */ |
| 971 | #define DACC_MR_STARTUP_8 (0x1u << 24) /**< \brief (DACC_MR) 8 periods of DACClock */ |
| 972 | #define DACC_MR_STARTUP_16 (0x2u << 24) /**< \brief (DACC_MR) 16 periods of DACClock */ |
| 973 | #define DACC_MR_STARTUP_24 (0x3u << 24) /**< \brief (DACC_MR) 24 periods of DACClock */ |
| 974 | #define DACC_MR_STARTUP_64 (0x4u << 24) /**< \brief (DACC_MR) 64 periods of DACClock */ |
| 975 | #define DACC_MR_STARTUP_80 (0x5u << 24) /**< \brief (DACC_MR) 80 periods of DACClock */ |
| 976 | #define DACC_MR_STARTUP_96 (0x6u << 24) /**< \brief (DACC_MR) 96 periods of DACClock */ |
| 977 | #define DACC_MR_STARTUP_112 (0x7u << 24) /**< \brief (DACC_MR) 112 periods of DACClock */ |
| 978 | #define DACC_MR_STARTUP_512 (0x8u << 24) /**< \brief (DACC_MR) 512 periods of DACClock */ |
| 979 | #define DACC_MR_STARTUP_576 (0x9u << 24) /**< \brief (DACC_MR) 576 periods of DACClock */ |
| 980 | #define DACC_MR_STARTUP_640 (0xAu << 24) /**< \brief (DACC_MR) 640 periods of DACClock */ |
| 981 | #define DACC_MR_STARTUP_704 (0xBu << 24) /**< \brief (DACC_MR) 704 periods of DACClock */ |
| 982 | #define DACC_MR_STARTUP_768 (0xCu << 24) /**< \brief (DACC_MR) 768 periods of DACClock */ |
| 983 | #define DACC_MR_STARTUP_832 (0xDu << 24) /**< \brief (DACC_MR) 832 periods of DACClock */ |
| 984 | #define DACC_MR_STARTUP_896 (0xEu << 24) /**< \brief (DACC_MR) 896 periods of DACClock */ |
| 985 | #define DACC_MR_STARTUP_960 (0xFu << 24) /**< \brief (DACC_MR) 960 periods of DACClock */ |
| 986 | /* -------- DACC_CHER : (DACC Offset: 0x10) Channel Enable Register -------- */ |
| 987 | #define DACC_CHER_CH0 (0x1u << 0) /**< \brief (DACC_CHER) Channel 0 Enable */ |
| 988 | #define DACC_CHER_CH1 (0x1u << 1) /**< \brief (DACC_CHER) Channel 1 Enable */ |
| 989 | /* -------- DACC_CHDR : (DACC Offset: 0x14) Channel Disable Register -------- */ |
| 990 | #define DACC_CHDR_CH0 (0x1u << 0) /**< \brief (DACC_CHDR) Channel 0 Disable */ |
| 991 | #define DACC_CHDR_CH1 (0x1u << 1) /**< \brief (DACC_CHDR) Channel 1 Disable */ |
| 992 | /* -------- DACC_CHSR : (DACC Offset: 0x18) Channel Status Register -------- */ |
| 993 | #define DACC_CHSR_CH0 (0x1u << 0) /**< \brief (DACC_CHSR) Channel 0 Status */ |
| 994 | #define DACC_CHSR_CH1 (0x1u << 1) /**< \brief (DACC_CHSR) Channel 1 Status */ |
| 995 | /* -------- DACC_CDR : (DACC Offset: 0x20) Conversion Data Register -------- */ |
| 996 | #define DACC_CDR_DATA_Pos 0 |
| 997 | #define DACC_CDR_DATA_Msk (0xffffffffu << DACC_CDR_DATA_Pos) /**< \brief (DACC_CDR) Data to Convert */ |
| 998 | #define DACC_CDR_DATA(value) ((DACC_CDR_DATA_Msk & ((value) << DACC_CDR_DATA_Pos))) |
| 999 | /* -------- DACC_IER : (DACC Offset: 0x24) Interrupt Enable Register -------- */ |
| 1000 | #define DACC_IER_TXRDY (0x1u << 0) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable */ |
| 1001 | #define DACC_IER_EOC (0x1u << 1) /**< \brief (DACC_IER) End of Conversion Interrupt Enable */ |
| 1002 | #define DACC_IER_ENDTX (0x1u << 2) /**< \brief (DACC_IER) End of Transmit Buffer Interrupt Enable */ |
| 1003 | #define DACC_IER_TXBUFE (0x1u << 3) /**< \brief (DACC_IER) Transmit Buffer Empty Interrupt Enable */ |
| 1004 | /* -------- DACC_IDR : (DACC Offset: 0x28) Interrupt Disable Register -------- */ |
| 1005 | #define DACC_IDR_TXRDY (0x1u << 0) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable. */ |
| 1006 | #define DACC_IDR_EOC (0x1u << 1) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable */ |
| 1007 | #define DACC_IDR_ENDTX (0x1u << 2) /**< \brief (DACC_IDR) End of Transmit Buffer Interrupt Disable */ |
| 1008 | #define DACC_IDR_TXBUFE (0x1u << 3) /**< \brief (DACC_IDR) Transmit Buffer Empty Interrupt Disable */ |
| 1009 | /* -------- DACC_IMR : (DACC Offset: 0x2C) Interrupt Mask Register -------- */ |
| 1010 | #define DACC_IMR_TXRDY (0x1u << 0) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask */ |
| 1011 | #define DACC_IMR_EOC (0x1u << 1) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask */ |
| 1012 | #define DACC_IMR_ENDTX (0x1u << 2) /**< \brief (DACC_IMR) End of Transmit Buffer Interrupt Mask */ |
| 1013 | #define DACC_IMR_TXBUFE (0x1u << 3) /**< \brief (DACC_IMR) Transmit Buffer Empty Interrupt Mask */ |
| 1014 | /* -------- DACC_ISR : (DACC Offset: 0x30) Interrupt Status Register -------- */ |
| 1015 | #define DACC_ISR_TXRDY (0x1u << 0) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag */ |
| 1016 | #define DACC_ISR_EOC (0x1u << 1) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag */ |
| 1017 | #define DACC_ISR_ENDTX (0x1u << 2) /**< \brief (DACC_ISR) End of DMA Interrupt Flag */ |
| 1018 | #define DACC_ISR_TXBUFE (0x1u << 3) /**< \brief (DACC_ISR) Transmit Buffer Empty */ |
| 1019 | /* -------- DACC_ACR : (DACC Offset: 0x94) Analog Current Register -------- */ |
| 1020 | #define DACC_ACR_IBCTLCH0_Pos 0 |
| 1021 | #define DACC_ACR_IBCTLCH0_Msk (0x3u << DACC_ACR_IBCTLCH0_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */ |
| 1022 | #define DACC_ACR_IBCTLCH0(value) ((DACC_ACR_IBCTLCH0_Msk & ((value) << DACC_ACR_IBCTLCH0_Pos))) |
| 1023 | #define DACC_ACR_IBCTLCH1_Pos 2 |
| 1024 | #define DACC_ACR_IBCTLCH1_Msk (0x3u << DACC_ACR_IBCTLCH1_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */ |
| 1025 | #define DACC_ACR_IBCTLCH1(value) ((DACC_ACR_IBCTLCH1_Msk & ((value) << DACC_ACR_IBCTLCH1_Pos))) |
| 1026 | #define DACC_ACR_IBCTLDACCORE_Pos 8 |
| 1027 | #define DACC_ACR_IBCTLDACCORE_Msk (0x3u << DACC_ACR_IBCTLDACCORE_Pos) /**< \brief (DACC_ACR) Bias Current Control for DAC Core */ |
| 1028 | #define DACC_ACR_IBCTLDACCORE(value) ((DACC_ACR_IBCTLDACCORE_Msk & ((value) << DACC_ACR_IBCTLDACCORE_Pos))) |
| 1029 | /* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protect Mode register -------- */ |
| 1030 | #define DACC_WPMR_WPEN (0x1u << 0) /**< \brief (DACC_WPMR) Write Protect Enable */ |
| 1031 | #define DACC_WPMR_WPKEY_Pos 8 |
| 1032 | #define DACC_WPMR_WPKEY_Msk (0xffffffu << DACC_WPMR_WPKEY_Pos) /**< \brief (DACC_WPMR) Write Protect KEY */ |
| 1033 | #define DACC_WPMR_WPKEY(value) ((DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos))) |
| 1034 | /* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protect Status register -------- */ |
| 1035 | #define DACC_WPSR_WPROTERR (0x1u << 0) /**< \brief (DACC_WPSR) Write protection error */ |
| 1036 | #define DACC_WPSR_WPROTADDR_Pos 8 |
| 1037 | #define DACC_WPSR_WPROTADDR_Msk (0xffu << DACC_WPSR_WPROTADDR_Pos) /**< \brief (DACC_WPSR) Write protection error address */ |
| 1038 | /* -------- DACC_RPR : (DACC Offset: 0x100) Receive Pointer Register -------- */ |
| 1039 | #define DACC_RPR_RXPTR_Pos 0 |
| 1040 | #define DACC_RPR_RXPTR_Msk (0xffffffffu << DACC_RPR_RXPTR_Pos) /**< \brief (DACC_RPR) Receive Pointer Register */ |
| 1041 | #define DACC_RPR_RXPTR(value) ((DACC_RPR_RXPTR_Msk & ((value) << DACC_RPR_RXPTR_Pos))) |
| 1042 | /* -------- DACC_RCR : (DACC Offset: 0x104) Receive Counter Register -------- */ |
| 1043 | #define DACC_RCR_RXCTR_Pos 0 |
| 1044 | #define DACC_RCR_RXCTR_Msk (0xffffu << DACC_RCR_RXCTR_Pos) /**< \brief (DACC_RCR) Receive Counter Register */ |
| 1045 | #define DACC_RCR_RXCTR(value) ((DACC_RCR_RXCTR_Msk & ((value) << DACC_RCR_RXCTR_Pos))) |
| 1046 | /* -------- DACC_TPR : (DACC Offset: 0x108) Transmit Pointer Register -------- */ |
| 1047 | #define DACC_TPR_TXPTR_Pos 0 |
| 1048 | #define DACC_TPR_TXPTR_Msk (0xffffffffu << DACC_TPR_TXPTR_Pos) /**< \brief (DACC_TPR) Transmit Counter Register */ |
| 1049 | #define DACC_TPR_TXPTR(value) ((DACC_TPR_TXPTR_Msk & ((value) << DACC_TPR_TXPTR_Pos))) |
| 1050 | /* -------- DACC_TCR : (DACC Offset: 0x10C) Transmit Counter Register -------- */ |
| 1051 | #define DACC_TCR_TXCTR_Pos 0 |
| 1052 | #define DACC_TCR_TXCTR_Msk (0xffffu << DACC_TCR_TXCTR_Pos) /**< \brief (DACC_TCR) Transmit Counter Register */ |
| 1053 | #define DACC_TCR_TXCTR(value) ((DACC_TCR_TXCTR_Msk & ((value) << DACC_TCR_TXCTR_Pos))) |
| 1054 | /* -------- DACC_RNPR : (DACC Offset: 0x110) Receive Next Pointer Register -------- */ |
| 1055 | #define DACC_RNPR_RXNPTR_Pos 0 |
| 1056 | #define DACC_RNPR_RXNPTR_Msk (0xffffffffu << DACC_RNPR_RXNPTR_Pos) /**< \brief (DACC_RNPR) Receive Next Pointer */ |
| 1057 | #define DACC_RNPR_RXNPTR(value) ((DACC_RNPR_RXNPTR_Msk & ((value) << DACC_RNPR_RXNPTR_Pos))) |
| 1058 | /* -------- DACC_RNCR : (DACC Offset: 0x114) Receive Next Counter Register -------- */ |
| 1059 | #define DACC_RNCR_RXNCTR_Pos 0 |
| 1060 | #define DACC_RNCR_RXNCTR_Msk (0xffffu << DACC_RNCR_RXNCTR_Pos) /**< \brief (DACC_RNCR) Receive Next Counter */ |
| 1061 | #define DACC_RNCR_RXNCTR(value) ((DACC_RNCR_RXNCTR_Msk & ((value) << DACC_RNCR_RXNCTR_Pos))) |
| 1062 | /* -------- DACC_TNPR : (DACC Offset: 0x118) Transmit Next Pointer Register -------- */ |
| 1063 | #define DACC_TNPR_TXNPTR_Pos 0 |
| 1064 | #define DACC_TNPR_TXNPTR_Msk (0xffffffffu << DACC_TNPR_TXNPTR_Pos) /**< \brief (DACC_TNPR) Transmit Next Pointer */ |
| 1065 | #define DACC_TNPR_TXNPTR(value) ((DACC_TNPR_TXNPTR_Msk & ((value) << DACC_TNPR_TXNPTR_Pos))) |
| 1066 | /* -------- DACC_TNCR : (DACC Offset: 0x11C) Transmit Next Counter Register -------- */ |
| 1067 | #define DACC_TNCR_TXNCTR_Pos 0 |
| 1068 | #define DACC_TNCR_TXNCTR_Msk (0xffffu << DACC_TNCR_TXNCTR_Pos) /**< \brief (DACC_TNCR) Transmit Counter Next */ |
| 1069 | #define DACC_TNCR_TXNCTR(value) ((DACC_TNCR_TXNCTR_Msk & ((value) << DACC_TNCR_TXNCTR_Pos))) |
| 1070 | /* -------- DACC_PTCR : (DACC Offset: 0x120) Transfer Control Register -------- */ |
| 1071 | #define DACC_PTCR_RXTEN (0x1u << 0) /**< \brief (DACC_PTCR) Receiver Transfer Enable */ |
| 1072 | #define DACC_PTCR_RXTDIS (0x1u << 1) /**< \brief (DACC_PTCR) Receiver Transfer Disable */ |
| 1073 | #define DACC_PTCR_TXTEN (0x1u << 8) /**< \brief (DACC_PTCR) Transmitter Transfer Enable */ |
| 1074 | #define DACC_PTCR_TXTDIS (0x1u << 9) /**< \brief (DACC_PTCR) Transmitter Transfer Disable */ |
| 1075 | /* -------- DACC_PTSR : (DACC Offset: 0x124) Transfer Status Register -------- */ |
| 1076 | #define DACC_PTSR_RXTEN (0x1u << 0) /**< \brief (DACC_PTSR) Receiver Transfer Enable */ |
| 1077 | #define DACC_PTSR_TXTEN (0x1u << 8) /**< \brief (DACC_PTSR) Transmitter Transfer Enable */ |
| 1078 | |
| 1079 | /*@}*/ |
| 1080 | |
| 1081 | /* ============================================================================= */ |
| 1082 | /** SOFTWARE API DEFINITION FOR Embedded Flash Controller */ |
| 1083 | /* ============================================================================= */ |
| 1084 | /** \addtogroup SAM3S_EFC Embedded Flash Controller */ |
| 1085 | /*@{*/ |
| 1086 | |
| 1087 | #ifndef __ASSEMBLY__ |
| 1088 | /** \brief Efc hardware registers */ |
| 1089 | typedef struct { |
| 1090 | RwReg EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */ |
| 1091 | WoReg EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */ |
| 1092 | RoReg EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */ |
| 1093 | RoReg EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */ |
| 1094 | } Efc; |
| 1095 | #endif /* __ASSEMBLY__ */ |
| 1096 | /* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */ |
| 1097 | #define EEFC_FMR_FRDY (0x1u << 0) /**< \brief (EEFC_FMR) Ready Interrupt Enable */ |
| 1098 | #define EEFC_FMR_FWS_Pos 8 |
| 1099 | #define EEFC_FMR_FWS_Msk (0xfu << EEFC_FMR_FWS_Pos) /**< \brief (EEFC_FMR) Flash Wait State */ |
| 1100 | #define EEFC_FMR_FWS(value) ((EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos))) |
| 1101 | #define EEFC_FMR_FAM (0x1u << 24) /**< \brief (EEFC_FMR) Flash Access Mode */ |
| 1102 | /* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */ |
| 1103 | #define EEFC_FCR_FCMD_Pos 0 |
| 1104 | #define EEFC_FCR_FCMD_Msk (0xffu << EEFC_FCR_FCMD_Pos) /**< \brief (EEFC_FCR) Flash Command */ |
| 1105 | #define EEFC_FCR_FCMD(value) ((EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos))) |
| 1106 | #define EEFC_FCR_FARG_Pos 8 |
| 1107 | #define EEFC_FCR_FARG_Msk (0xffffu << EEFC_FCR_FARG_Pos) /**< \brief (EEFC_FCR) Flash Command Argument */ |
| 1108 | #define EEFC_FCR_FARG(value) ((EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos))) |
| 1109 | #define EEFC_FCR_FKEY_Pos 24 |
| 1110 | #define EEFC_FCR_FKEY_Msk (0xffu << EEFC_FCR_FKEY_Pos) /**< \brief (EEFC_FCR) Flash Writing Protection Key */ |
| 1111 | #define EEFC_FCR_FKEY(value) ((EEFC_FCR_FKEY_Msk & ((value) << EEFC_FCR_FKEY_Pos))) |
| 1112 | /* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */ |
| 1113 | #define EEFC_FSR_FRDY (0x1u << 0) /**< \brief (EEFC_FSR) Flash Ready Status */ |
| 1114 | #define EEFC_FSR_FCMDE (0x1u << 1) /**< \brief (EEFC_FSR) Flash Command Error Status */ |
| 1115 | #define EEFC_FSR_FLOCKE (0x1u << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status */ |
| 1116 | /* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */ |
| 1117 | #define EEFC_FRR_FVALUE_Pos 0 |
| 1118 | #define EEFC_FRR_FVALUE_Msk (0xffffffffu << EEFC_FRR_FVALUE_Pos) /**< \brief (EEFC_FRR) Flash Result Value */ |
| 1119 | |
| 1120 | /*@}*/ |
| 1121 | |
| 1122 | /* ============================================================================= */ |
| 1123 | /** SOFTWARE API DEFINITION FOR General Purpose Backup Register */ |
| 1124 | /* ============================================================================= */ |
| 1125 | /** \addtogroup SAM3S_GPBR General Purpose Backup Register */ |
| 1126 | /*@{*/ |
| 1127 | |
| 1128 | #ifndef __ASSEMBLY__ |
| 1129 | /** \brief Gpbr hardware registers */ |
| 1130 | typedef struct { |
| 1131 | RwReg SYS_GPBR0; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register 0 */ |
| 1132 | RwReg SYS_GPBR1; /**< \brief (Gpbr Offset: 0x4) General Purpose Backup Register 1 */ |
| 1133 | RwReg SYS_GPBR2; /**< \brief (Gpbr Offset: 0x8) General Purpose Backup Register 2 */ |
| 1134 | RwReg SYS_GPBR3; /**< \brief (Gpbr Offset: 0xC) General Purpose Backup Register 3 */ |
| 1135 | RwReg SYS_GPBR4; /**< \brief (Gpbr Offset: 0x10) General Purpose Backup Register 4 */ |
| 1136 | RwReg SYS_GPBR5; /**< \brief (Gpbr Offset: 0x14) General Purpose Backup Register 5 */ |
| 1137 | RwReg SYS_GPBR6; /**< \brief (Gpbr Offset: 0x18) General Purpose Backup Register 6 */ |
| 1138 | RwReg SYS_GPBR7; /**< \brief (Gpbr Offset: 0x1C) General Purpose Backup Register 7 */ |
| 1139 | } Gpbr; |
| 1140 | #endif /* __ASSEMBLY__ */ |
| 1141 | /* -------- SYS_GPBR0 : (GPBR Offset: 0x0) General Purpose Backup Register 0 -------- */ |
| 1142 | #define SYS_GPBR0_GPBR_VALUE0_Pos 0 |
| 1143 | #define SYS_GPBR0_GPBR_VALUE0_Msk (0xffffffffu << SYS_GPBR0_GPBR_VALUE0_Pos) /**< \brief (SYS_GPBR0) Value of GPBR x */ |
| 1144 | #define SYS_GPBR0_GPBR_VALUE0(value) ((SYS_GPBR0_GPBR_VALUE0_Msk & ((value) << SYS_GPBR0_GPBR_VALUE0_Pos))) |
| 1145 | /* -------- SYS_GPBR1 : (GPBR Offset: 0x4) General Purpose Backup Register 1 -------- */ |
| 1146 | #define SYS_GPBR1_GPBR_VALUE1_Pos 0 |
| 1147 | #define SYS_GPBR1_GPBR_VALUE1_Msk (0xffffffffu << SYS_GPBR1_GPBR_VALUE1_Pos) /**< \brief (SYS_GPBR1) Value of GPBR x */ |
| 1148 | #define SYS_GPBR1_GPBR_VALUE1(value) ((SYS_GPBR1_GPBR_VALUE1_Msk & ((value) << SYS_GPBR1_GPBR_VALUE1_Pos))) |
| 1149 | /* -------- SYS_GPBR2 : (GPBR Offset: 0x8) General Purpose Backup Register 2 -------- */ |
| 1150 | #define SYS_GPBR2_GPBR_VALUE2_Pos 0 |
| 1151 | #define SYS_GPBR2_GPBR_VALUE2_Msk (0xffffffffu << SYS_GPBR2_GPBR_VALUE2_Pos) /**< \brief (SYS_GPBR2) Value of GPBR x */ |
| 1152 | #define SYS_GPBR2_GPBR_VALUE2(value) ((SYS_GPBR2_GPBR_VALUE2_Msk & ((value) << SYS_GPBR2_GPBR_VALUE2_Pos))) |
| 1153 | /* -------- SYS_GPBR3 : (GPBR Offset: 0xC) General Purpose Backup Register 3 -------- */ |
| 1154 | #define SYS_GPBR3_GPBR_VALUE3_Pos 0 |
| 1155 | #define SYS_GPBR3_GPBR_VALUE3_Msk (0xffffffffu << SYS_GPBR3_GPBR_VALUE3_Pos) /**< \brief (SYS_GPBR3) Value of GPBR x */ |
| 1156 | #define SYS_GPBR3_GPBR_VALUE3(value) ((SYS_GPBR3_GPBR_VALUE3_Msk & ((value) << SYS_GPBR3_GPBR_VALUE3_Pos))) |
| 1157 | /* -------- SYS_GPBR4 : (GPBR Offset: 0x10) General Purpose Backup Register 4 -------- */ |
| 1158 | #define SYS_GPBR4_GPBR_VALUE4_Pos 0 |
| 1159 | #define SYS_GPBR4_GPBR_VALUE4_Msk (0xffffffffu << SYS_GPBR4_GPBR_VALUE4_Pos) /**< \brief (SYS_GPBR4) Value of GPBR x */ |
| 1160 | #define SYS_GPBR4_GPBR_VALUE4(value) ((SYS_GPBR4_GPBR_VALUE4_Msk & ((value) << SYS_GPBR4_GPBR_VALUE4_Pos))) |
| 1161 | /* -------- SYS_GPBR5 : (GPBR Offset: 0x14) General Purpose Backup Register 5 -------- */ |
| 1162 | #define SYS_GPBR5_GPBR_VALUE5_Pos 0 |
| 1163 | #define SYS_GPBR5_GPBR_VALUE5_Msk (0xffffffffu << SYS_GPBR5_GPBR_VALUE5_Pos) /**< \brief (SYS_GPBR5) Value of GPBR x */ |
| 1164 | #define SYS_GPBR5_GPBR_VALUE5(value) ((SYS_GPBR5_GPBR_VALUE5_Msk & ((value) << SYS_GPBR5_GPBR_VALUE5_Pos))) |
| 1165 | /* -------- SYS_GPBR6 : (GPBR Offset: 0x18) General Purpose Backup Register 6 -------- */ |
| 1166 | #define SYS_GPBR6_GPBR_VALUE6_Pos 0 |
| 1167 | #define SYS_GPBR6_GPBR_VALUE6_Msk (0xffffffffu << SYS_GPBR6_GPBR_VALUE6_Pos) /**< \brief (SYS_GPBR6) Value of GPBR x */ |
| 1168 | #define SYS_GPBR6_GPBR_VALUE6(value) ((SYS_GPBR6_GPBR_VALUE6_Msk & ((value) << SYS_GPBR6_GPBR_VALUE6_Pos))) |
| 1169 | /* -------- SYS_GPBR7 : (GPBR Offset: 0x1C) General Purpose Backup Register 7 -------- */ |
| 1170 | #define SYS_GPBR7_GPBR_VALUE7_Pos 0 |
| 1171 | #define SYS_GPBR7_GPBR_VALUE7_Msk (0xffffffffu << SYS_GPBR7_GPBR_VALUE7_Pos) /**< \brief (SYS_GPBR7) Value of GPBR x */ |
| 1172 | #define SYS_GPBR7_GPBR_VALUE7(value) ((SYS_GPBR7_GPBR_VALUE7_Msk & ((value) << SYS_GPBR7_GPBR_VALUE7_Pos))) |
| 1173 | |
| 1174 | /*@}*/ |
| 1175 | |
| 1176 | /* ============================================================================= */ |
| 1177 | /** SOFTWARE API DEFINITION FOR High Speed MultiMedia Card Interface */ |
| 1178 | /* ============================================================================= */ |
| 1179 | /** \addtogroup SAM3S_HSMCI High Speed MultiMedia Card Interface */ |
| 1180 | /*@{*/ |
| 1181 | |
| 1182 | #ifndef __ASSEMBLY__ |
| 1183 | /** \brief Hsmci hardware registers */ |
| 1184 | typedef struct { |
| 1185 | WoReg HSMCI_CR; /**< \brief (Hsmci Offset: 0x00) Control Register */ |
| 1186 | RwReg HSMCI_MR; /**< \brief (Hsmci Offset: 0x04) Mode Register */ |
| 1187 | RwReg HSMCI_DTOR; /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */ |
| 1188 | RwReg HSMCI_SDCR; /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */ |
| 1189 | RwReg HSMCI_ARGR; /**< \brief (Hsmci Offset: 0x10) Argument Register */ |
| 1190 | WoReg HSMCI_CMDR; /**< \brief (Hsmci Offset: 0x14) Command Register */ |
| 1191 | RwReg HSMCI_BLKR; /**< \brief (Hsmci Offset: 0x18) Block Register */ |
| 1192 | RwReg HSMCI_CSTOR; /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */ |
| 1193 | RoReg HSMCI_RSPR[4]; /**< \brief (Hsmci Offset: 0x20) Response Register */ |
| 1194 | RoReg HSMCI_RDR; /**< \brief (Hsmci Offset: 0x30) Receive Data Register */ |
| 1195 | WoReg HSMCI_TDR; /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */ |
| 1196 | RwReg Reserved1[2]; |
| 1197 | RoReg HSMCI_SR; /**< \brief (Hsmci Offset: 0x40) Status Register */ |
| 1198 | WoReg HSMCI_IER; /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */ |
| 1199 | WoReg HSMCI_IDR; /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */ |
| 1200 | RoReg HSMCI_IMR; /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */ |
| 1201 | RwReg Reserved2[1]; |
| 1202 | RwReg HSMCI_CFG; /**< \brief (Hsmci Offset: 0x54) Configuration Register */ |
| 1203 | RwReg Reserved3[35]; |
| 1204 | RwReg HSMCI_WPMR; /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */ |
| 1205 | RoReg HSMCI_WPSR; /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */ |
| 1206 | RwReg Reserved4[5]; |
| 1207 | RwReg HSMCI_RPR; /**< \brief (Hsmci Offset: 0x100) Receive Pointer Register */ |
| 1208 | RwReg HSMCI_RCR; /**< \brief (Hsmci Offset: 0x104) Receive Counter Register */ |
| 1209 | RwReg HSMCI_TPR; /**< \brief (Hsmci Offset: 0x108) Transmit Pointer Register */ |
| 1210 | RwReg HSMCI_TCR; /**< \brief (Hsmci Offset: 0x10C) Transmit Counter Register */ |
| 1211 | RwReg HSMCI_RNPR; /**< \brief (Hsmci Offset: 0x110) Receive Next Pointer Register */ |
| 1212 | RwReg HSMCI_RNCR; /**< \brief (Hsmci Offset: 0x114) Receive Next Counter Register */ |
| 1213 | RwReg HSMCI_TNPR; /**< \brief (Hsmci Offset: 0x118) Transmit Next Pointer Register */ |
| 1214 | RwReg HSMCI_TNCR; /**< \brief (Hsmci Offset: 0x11C) Transmit Next Counter Register */ |
| 1215 | WoReg HSMCI_PTCR; /**< \brief (Hsmci Offset: 0x120) Transfer Control Register */ |
| 1216 | RoReg HSMCI_PTSR; /**< \brief (Hsmci Offset: 0x124) Transfer Status Register */ |
| 1217 | RwReg Reserved5[54]; |
| 1218 | RwReg HSMCI_FIFO[256]; /**< \brief (Hsmci Offset: 0x200) FIFO Memory Aperture0 */ |
| 1219 | } Hsmci; |
| 1220 | #endif /* __ASSEMBLY__ */ |
| 1221 | /* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */ |
| 1222 | #define HSMCI_CR_MCIEN (0x1u << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */ |
| 1223 | #define HSMCI_CR_MCIDIS (0x1u << 1) /**< \brief (HSMCI_CR) Multi-Media Interface Disable */ |
| 1224 | #define HSMCI_CR_PWSEN (0x1u << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */ |
| 1225 | #define HSMCI_CR_PWSDIS (0x1u << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */ |
| 1226 | #define HSMCI_CR_SWRST (0x1u << 7) /**< \brief (HSMCI_CR) Software Reset */ |
| 1227 | /* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */ |
| 1228 | #define HSMCI_MR_CLKDIV_Pos 0 |
| 1229 | #define HSMCI_MR_CLKDIV_Msk (0xffu << HSMCI_MR_CLKDIV_Pos) /**< \brief (HSMCI_MR) Clock Divider */ |
| 1230 | #define HSMCI_MR_CLKDIV(value) ((HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos))) |
| 1231 | #define HSMCI_MR_PWSDIV_Pos 8 |
| 1232 | #define HSMCI_MR_PWSDIV_Msk (0x7u << HSMCI_MR_PWSDIV_Pos) /**< \brief (HSMCI_MR) Power Saving Divider */ |
| 1233 | #define HSMCI_MR_PWSDIV(value) ((HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos))) |
| 1234 | #define HSMCI_MR_RDPROOF (0x1u << 11) /**< \brief (HSMCI_MR) */ |
| 1235 | #define HSMCI_MR_WRPROOF (0x1u << 12) /**< \brief (HSMCI_MR) */ |
| 1236 | #define HSMCI_MR_FBYTE (0x1u << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */ |
| 1237 | #define HSMCI_MR_PADV (0x1u << 14) /**< \brief (HSMCI_MR) Padding Value */ |
| 1238 | #define HSMCI_MR_PDCMODE (0x1u << 15) /**< \brief (HSMCI_MR) PDC-oriented Mode */ |
| 1239 | #define HSMCI_MR_BLKLEN_Pos 16 |
| 1240 | #define HSMCI_MR_BLKLEN_Msk (0xffffu << HSMCI_MR_BLKLEN_Pos) /**< \brief (HSMCI_MR) Data Block Length */ |
| 1241 | #define HSMCI_MR_BLKLEN(value) ((HSMCI_MR_BLKLEN_Msk & ((value) << HSMCI_MR_BLKLEN_Pos))) |
| 1242 | /* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */ |
| 1243 | #define HSMCI_DTOR_DTOCYC_Pos 0 |
| 1244 | #define HSMCI_DTOR_DTOCYC_Msk (0xfu << HSMCI_DTOR_DTOCYC_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */ |
| 1245 | #define HSMCI_DTOR_DTOCYC(value) ((HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos))) |
| 1246 | #define HSMCI_DTOR_DTOMUL_Pos 4 |
| 1247 | #define HSMCI_DTOR_DTOMUL_Msk (0x7u << HSMCI_DTOR_DTOMUL_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */ |
| 1248 | #define HSMCI_DTOR_DTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_DTOR) DTOCYC */ |
| 1249 | #define HSMCI_DTOR_DTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 16 */ |
| 1250 | #define HSMCI_DTOR_DTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 128 */ |
| 1251 | #define HSMCI_DTOR_DTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 256 */ |
| 1252 | #define HSMCI_DTOR_DTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1024 */ |
| 1253 | #define HSMCI_DTOR_DTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 4096 */ |
| 1254 | #define HSMCI_DTOR_DTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 65536 */ |
| 1255 | #define HSMCI_DTOR_DTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1048576 */ |
| 1256 | /* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */ |
| 1257 | #define HSMCI_SDCR_SDCSEL_Pos 0 |
| 1258 | #define HSMCI_SDCR_SDCSEL_Msk (0x3u << HSMCI_SDCR_SDCSEL_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */ |
| 1259 | #define HSMCI_SDCR_SDCSEL_SLOTA (0x0u << 0) /**< \brief (HSMCI_SDCR) Slot A is selected. */ |
| 1260 | #define HSMCI_SDCR_SDCSEL_SLOTB (0x1u << 0) /**< \brief (HSMCI_SDCR) - */ |
| 1261 | #define HSMCI_SDCR_SDCSEL_SLOTC (0x2u << 0) /**< \brief (HSMCI_SDCR) - */ |
| 1262 | #define HSMCI_SDCR_SDCSEL_SLOTD (0x3u << 0) /**< \brief (HSMCI_SDCR) - */ |
| 1263 | #define HSMCI_SDCR_SDCBUS_Pos 6 |
| 1264 | #define HSMCI_SDCR_SDCBUS_Msk (0x3u << HSMCI_SDCR_SDCBUS_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */ |
| 1265 | #define HSMCI_SDCR_SDCBUS_1 (0x0u << 6) /**< \brief (HSMCI_SDCR) 1 bit */ |
| 1266 | #define HSMCI_SDCR_SDCBUS_4 (0x2u << 6) /**< \brief (HSMCI_SDCR) 4 bit */ |
| 1267 | #define HSMCI_SDCR_SDCBUS_8 (0x3u << 6) /**< \brief (HSMCI_SDCR) 8 bit */ |
| 1268 | /* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */ |
| 1269 | #define HSMCI_ARGR_ARG_Pos 0 |
| 1270 | #define HSMCI_ARGR_ARG_Msk (0xffffffffu << HSMCI_ARGR_ARG_Pos) /**< \brief (HSMCI_ARGR) Command Argument */ |
| 1271 | #define HSMCI_ARGR_ARG(value) ((HSMCI_ARGR_ARG_Msk & ((value) << HSMCI_ARGR_ARG_Pos))) |
| 1272 | /* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */ |
| 1273 | #define HSMCI_CMDR_CMDNB_Pos 0 |
| 1274 | #define HSMCI_CMDR_CMDNB_Msk (0x3fu << HSMCI_CMDR_CMDNB_Pos) /**< \brief (HSMCI_CMDR) Command Number */ |
| 1275 | #define HSMCI_CMDR_CMDNB(value) ((HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos))) |
| 1276 | #define HSMCI_CMDR_RSPTYP_Pos 6 |
| 1277 | #define HSMCI_CMDR_RSPTYP_Msk (0x3u << HSMCI_CMDR_RSPTYP_Pos) /**< \brief (HSMCI_CMDR) Response Type */ |
| 1278 | #define HSMCI_CMDR_RSPTYP_NORESP (0x0u << 6) /**< \brief (HSMCI_CMDR) No response. */ |
| 1279 | #define HSMCI_CMDR_RSPTYP_48_BIT (0x1u << 6) /**< \brief (HSMCI_CMDR) 48-bit response. */ |
| 1280 | #define HSMCI_CMDR_RSPTYP_136_BIT (0x2u << 6) /**< \brief (HSMCI_CMDR) 136-bit response. */ |
| 1281 | #define HSMCI_CMDR_RSPTYP_R1B (0x3u << 6) /**< \brief (HSMCI_CMDR) R1b response type */ |
| 1282 | #define HSMCI_CMDR_SPCMD_Pos 8 |
| 1283 | #define HSMCI_CMDR_SPCMD_Msk (0x7u << HSMCI_CMDR_SPCMD_Pos) /**< \brief (HSMCI_CMDR) Special Command */ |
| 1284 | #define HSMCI_CMDR_SPCMD_STD (0x0u << 8) /**< \brief (HSMCI_CMDR) Not a special CMD. */ |
| 1285 | #define HSMCI_CMDR_SPCMD_INIT (0x1u << 8) /**< \brief (HSMCI_CMDR) Initialization CMD:74 clock cycles for initialization sequence. */ |
| 1286 | #define HSMCI_CMDR_SPCMD_SYNC (0x2u << 8) /**< \brief (HSMCI_CMDR) Synchronized CMD:Wait for the end of the current data block transfer before sending the pending command. */ |
| 1287 | #define HSMCI_CMDR_SPCMD_CE_ATA (0x3u << 8) /**< \brief (HSMCI_CMDR) CE-ATA Completion Signal disable Command.The host cancels the ability for the device to return a command completion signal on the command line. */ |
| 1288 | #define HSMCI_CMDR_SPCMD_IT_CMD (0x4u << 8) /**< \brief (HSMCI_CMDR) Interrupt command:Corresponds to the Interrupt Mode (CMD40). */ |
| 1289 | #define HSMCI_CMDR_SPCMD_IT_RESP (0x5u << 8) /**< \brief (HSMCI_CMDR) Interrupt response:Corresponds to the Interrupt Mode (CMD40). */ |
| 1290 | #define HSMCI_CMDR_SPCMD_BOR (0x6u << 8) /**< \brief (HSMCI_CMDR) Boot Operation Request.Start a boot operation mode, the host processor can read boot data from the MMC device directly. */ |
| 1291 | #define HSMCI_CMDR_SPCMD_EBO (0x7u << 8) /**< \brief (HSMCI_CMDR) End Boot Operation.This command allows the host processor to terminate the boot operation mode. */ |
| 1292 | #define HSMCI_CMDR_OPDCMD (0x1u << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */ |
| 1293 | #define HSMCI_CMDR_OPDCMD_PUSHPULL (0x0u << 11) /**< \brief (HSMCI_CMDR) Push pull command. */ |
| 1294 | #define HSMCI_CMDR_OPDCMD_OPENDRAIN (0x1u << 11) /**< \brief (HSMCI_CMDR) Open drain command. */ |
| 1295 | #define HSMCI_CMDR_MAXLAT (0x1u << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */ |
| 1296 | #define HSMCI_CMDR_MAXLAT_5 (0x0u << 12) /**< \brief (HSMCI_CMDR) 5-cycle max latency. */ |
| 1297 | #define HSMCI_CMDR_MAXLAT_64 (0x1u << 12) /**< \brief (HSMCI_CMDR) 64-cycle max latency. */ |
| 1298 | #define HSMCI_CMDR_TRCMD_Pos 16 |
| 1299 | #define HSMCI_CMDR_TRCMD_Msk (0x3u << HSMCI_CMDR_TRCMD_Pos) /**< \brief (HSMCI_CMDR) Transfer Command */ |
| 1300 | #define HSMCI_CMDR_TRCMD_NO_DATA (0x0u << 16) /**< \brief (HSMCI_CMDR) No data transfer */ |
| 1301 | #define HSMCI_CMDR_TRCMD_START_DATA (0x1u << 16) /**< \brief (HSMCI_CMDR) Start data transfer */ |
| 1302 | #define HSMCI_CMDR_TRCMD_STOP_DATA (0x2u << 16) /**< \brief (HSMCI_CMDR) Stop data transfer */ |
| 1303 | #define HSMCI_CMDR_TRDIR (0x1u << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */ |
| 1304 | #define HSMCI_CMDR_TRDIR_WRITE (0x0u << 18) /**< \brief (HSMCI_CMDR) Write. */ |
| 1305 | #define HSMCI_CMDR_TRDIR_READ (0x1u << 18) /**< \brief (HSMCI_CMDR) Read. */ |
| 1306 | #define HSMCI_CMDR_TRTYP_Pos 19 |
| 1307 | #define HSMCI_CMDR_TRTYP_Msk (0x7u << HSMCI_CMDR_TRTYP_Pos) /**< \brief (HSMCI_CMDR) Transfer Type */ |
| 1308 | #define HSMCI_CMDR_TRTYP_SINGLE (0x0u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Single Block */ |
| 1309 | #define HSMCI_CMDR_TRTYP_MULTIPLE (0x1u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Multiple Block */ |
| 1310 | #define HSMCI_CMDR_TRTYP_STREAM (0x2u << 19) /**< \brief (HSMCI_CMDR) MMC Stream */ |
| 1311 | #define HSMCI_CMDR_TRTYP_BYTE (0x4u << 19) /**< \brief (HSMCI_CMDR) SDIO Byte */ |
| 1312 | #define HSMCI_CMDR_TRTYP_BLOCK (0x5u << 19) /**< \brief (HSMCI_CMDR) SDIO Block */ |
| 1313 | #define HSMCI_CMDR_IOSPCMD_Pos 24 |
| 1314 | #define HSMCI_CMDR_IOSPCMD_Msk (0x3u << HSMCI_CMDR_IOSPCMD_Pos) /**< \brief (HSMCI_CMDR) SDIO Special Command */ |
| 1315 | #define HSMCI_CMDR_IOSPCMD_STD (0x0u << 24) /**< \brief (HSMCI_CMDR) Not an SDIO Special Command */ |
| 1316 | #define HSMCI_CMDR_IOSPCMD_SUSPEND (0x1u << 24) /**< \brief (HSMCI_CMDR) SDIO Suspend Command */ |
| 1317 | #define HSMCI_CMDR_IOSPCMD_RESUME (0x2u << 24) /**< \brief (HSMCI_CMDR) SDIO Resume Command */ |
| 1318 | #define HSMCI_CMDR_ATACS (0x1u << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */ |
| 1319 | #define HSMCI_CMDR_ATACS_NORMAL (0x0u << 26) /**< \brief (HSMCI_CMDR) Normal operation mode. */ |
| 1320 | #define HSMCI_CMDR_ATACS_COMPLETION (0x1u << 26) /**< \brief (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). */ |
| 1321 | #define HSMCI_CMDR_BOOT_ACK (0x1u << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge. */ |
| 1322 | /* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */ |
| 1323 | #define HSMCI_BLKR_BCNT_Pos 0 |
| 1324 | #define HSMCI_BLKR_BCNT_Msk (0xffffu << HSMCI_BLKR_BCNT_Pos) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */ |
| 1325 | #define HSMCI_BLKR_BCNT_MULTIPLE (0x0u << 0) /**< \brief (HSMCI_BLKR) MMC/SDCARD Multiple BlockFrom 1 to 65635: Value 0 corresponds to an infinite block transfer. */ |
| 1326 | #define HSMCI_BLKR_BCNT_BYTE (0x4u << 0) /**< \brief (HSMCI_BLKR) SDIO ByteFrom 1 to 512 bytes: Value 0 corresponds to a 512-byte transfer.Values from 0x200 to 0xFFFF are forbidden. */ |
| 1327 | #define HSMCI_BLKR_BCNT_BLOCK (0x5u << 0) /**< \brief (HSMCI_BLKR) SDIO BlockFrom 1 to 511 blocks: Value 0 corresponds to an infinite block transfer.Values from 0x200 to 0xFFFF are forbidden. */ |
| 1328 | #define HSMCI_BLKR_BLKLEN_Pos 16 |
| 1329 | #define HSMCI_BLKR_BLKLEN_Msk (0xffffu << HSMCI_BLKR_BLKLEN_Pos) /**< \brief (HSMCI_BLKR) Data Block Length */ |
| 1330 | #define HSMCI_BLKR_BLKLEN(value) ((HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos))) |
| 1331 | /* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */ |
| 1332 | #define HSMCI_CSTOR_CSTOCYC_Pos 0 |
| 1333 | #define HSMCI_CSTOR_CSTOCYC_Msk (0xfu << HSMCI_CSTOR_CSTOCYC_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */ |
| 1334 | #define HSMCI_CSTOR_CSTOCYC(value) ((HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos))) |
| 1335 | #define HSMCI_CSTOR_CSTOMUL_Pos 4 |
| 1336 | #define HSMCI_CSTOR_CSTOMUL_Msk (0x7u << HSMCI_CSTOR_CSTOMUL_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */ |
| 1337 | #define HSMCI_CSTOR_CSTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1 */ |
| 1338 | #define HSMCI_CSTOR_CSTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 16 */ |
| 1339 | #define HSMCI_CSTOR_CSTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 128 */ |
| 1340 | #define HSMCI_CSTOR_CSTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 256 */ |
| 1341 | #define HSMCI_CSTOR_CSTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1024 */ |
| 1342 | #define HSMCI_CSTOR_CSTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 4096 */ |
| 1343 | #define HSMCI_CSTOR_CSTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 65536 */ |
| 1344 | #define HSMCI_CSTOR_CSTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1048576 */ |
| 1345 | /* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */ |
| 1346 | #define HSMCI_RSPR_RSP_Pos 0 |
| 1347 | #define HSMCI_RSPR_RSP_Msk (0xffffffffu << HSMCI_RSPR_RSP_Pos) /**< \brief (HSMCI_RSPR[4]) Response */ |
| 1348 | /* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */ |
| 1349 | #define HSMCI_RDR_DATA_Pos 0 |
| 1350 | #define HSMCI_RDR_DATA_Msk (0xffffffffu << HSMCI_RDR_DATA_Pos) /**< \brief (HSMCI_RDR) Data to Read */ |
| 1351 | /* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */ |
| 1352 | #define HSMCI_TDR_DATA_Pos 0 |
| 1353 | #define HSMCI_TDR_DATA_Msk (0xffffffffu << HSMCI_TDR_DATA_Pos) /**< \brief (HSMCI_TDR) Data to Write */ |
| 1354 | #define HSMCI_TDR_DATA(value) ((HSMCI_TDR_DATA_Msk & ((value) << HSMCI_TDR_DATA_Pos))) |
| 1355 | /* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */ |
| 1356 | #define HSMCI_SR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_SR) Command Ready */ |
| 1357 | #define HSMCI_SR_RXRDY (0x1u << 1) /**< \brief (HSMCI_SR) Receiver Ready */ |
| 1358 | #define HSMCI_SR_TXRDY (0x1u << 2) /**< \brief (HSMCI_SR) Transmit Ready */ |
| 1359 | #define HSMCI_SR_BLKE (0x1u << 3) /**< \brief (HSMCI_SR) Data Block Ended */ |
| 1360 | #define HSMCI_SR_DTIP (0x1u << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress */ |
| 1361 | #define HSMCI_SR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */ |
| 1362 | #define HSMCI_SR_ENDRX (0x1u << 6) /**< \brief (HSMCI_SR) End of RX Buffer */ |
| 1363 | #define HSMCI_SR_ENDTX (0x1u << 7) /**< \brief (HSMCI_SR) End of TX Buffer */ |
| 1364 | #define HSMCI_SR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_SR) SDIO Interrupt for Slot A */ |
| 1365 | #define HSMCI_SR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */ |
| 1366 | #define HSMCI_SR_CSRCV (0x1u << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received */ |
| 1367 | #define HSMCI_SR_RXBUFF (0x1u << 14) /**< \brief (HSMCI_SR) RX Buffer Full */ |
| 1368 | #define HSMCI_SR_TXBUFE (0x1u << 15) /**< \brief (HSMCI_SR) TX Buffer Empty */ |
| 1369 | #define HSMCI_SR_RINDE (0x1u << 16) /**< \brief (HSMCI_SR) Response Index Error */ |
| 1370 | #define HSMCI_SR_RDIRE (0x1u << 17) /**< \brief (HSMCI_SR) Response Direction Error */ |
| 1371 | #define HSMCI_SR_RCRCE (0x1u << 18) /**< \brief (HSMCI_SR) Response CRC Error */ |
| 1372 | #define HSMCI_SR_RENDE (0x1u << 19) /**< \brief (HSMCI_SR) Response End Bit Error */ |
| 1373 | #define HSMCI_SR_RTOE (0x1u << 20) /**< \brief (HSMCI_SR) Response Time-out Error */ |
| 1374 | #define HSMCI_SR_DCRCE (0x1u << 21) /**< \brief (HSMCI_SR) Data CRC Error */ |
| 1375 | #define HSMCI_SR_DTOE (0x1u << 22) /**< \brief (HSMCI_SR) Data Time-out Error */ |
| 1376 | #define HSMCI_SR_CSTOE (0x1u << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error */ |
| 1377 | #define HSMCI_SR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_SR) FIFO empty flag */ |
| 1378 | #define HSMCI_SR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_SR) Transfer Done flag */ |
| 1379 | #define HSMCI_SR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received */ |
| 1380 | #define HSMCI_SR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error */ |
| 1381 | #define HSMCI_SR_OVRE (0x1u << 30) /**< \brief (HSMCI_SR) Overrun */ |
| 1382 | #define HSMCI_SR_UNRE (0x1u << 31) /**< \brief (HSMCI_SR) Underrun */ |
| 1383 | /* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */ |
| 1384 | #define HSMCI_IER_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */ |
| 1385 | #define HSMCI_IER_RXRDY (0x1u << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */ |
| 1386 | #define HSMCI_IER_TXRDY (0x1u << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */ |
| 1387 | #define HSMCI_IER_BLKE (0x1u << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */ |
| 1388 | #define HSMCI_IER_DTIP (0x1u << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */ |
| 1389 | #define HSMCI_IER_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */ |
| 1390 | #define HSMCI_IER_ENDRX (0x1u << 6) /**< \brief (HSMCI_IER) End of Receive Buffer Interrupt Enable */ |
| 1391 | #define HSMCI_IER_ENDTX (0x1u << 7) /**< \brief (HSMCI_IER) End of Transmit Buffer Interrupt Enable */ |
| 1392 | #define HSMCI_IER_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IER) SDIO Interrupt for Slot A Interrupt Enable */ |
| 1393 | #define HSMCI_IER_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */ |
| 1394 | #define HSMCI_IER_CSRCV (0x1u << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */ |
| 1395 | #define HSMCI_IER_RXBUFF (0x1u << 14) /**< \brief (HSMCI_IER) Receive Buffer Full Interrupt Enable */ |
| 1396 | #define HSMCI_IER_TXBUFE (0x1u << 15) /**< \brief (HSMCI_IER) Transmit Buffer Empty Interrupt Enable */ |
| 1397 | #define HSMCI_IER_RINDE (0x1u << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */ |
| 1398 | #define HSMCI_IER_RDIRE (0x1u << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */ |
| 1399 | #define HSMCI_IER_RCRCE (0x1u << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */ |
| 1400 | #define HSMCI_IER_RENDE (0x1u << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */ |
| 1401 | #define HSMCI_IER_RTOE (0x1u << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */ |
| 1402 | #define HSMCI_IER_DCRCE (0x1u << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */ |
| 1403 | #define HSMCI_IER_DTOE (0x1u << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */ |
| 1404 | #define HSMCI_IER_CSTOE (0x1u << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */ |
| 1405 | #define HSMCI_IER_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */ |
| 1406 | #define HSMCI_IER_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */ |
| 1407 | #define HSMCI_IER_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */ |
| 1408 | #define HSMCI_IER_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */ |
| 1409 | #define HSMCI_IER_OVRE (0x1u << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */ |
| 1410 | #define HSMCI_IER_UNRE (0x1u << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */ |
| 1411 | /* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */ |
| 1412 | #define HSMCI_IDR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */ |
| 1413 | #define HSMCI_IDR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */ |
| 1414 | #define HSMCI_IDR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */ |
| 1415 | #define HSMCI_IDR_BLKE (0x1u << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */ |
| 1416 | #define HSMCI_IDR_DTIP (0x1u << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */ |
| 1417 | #define HSMCI_IDR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */ |
| 1418 | #define HSMCI_IDR_ENDRX (0x1u << 6) /**< \brief (HSMCI_IDR) End of Receive Buffer Interrupt Disable */ |
| 1419 | #define HSMCI_IDR_ENDTX (0x1u << 7) /**< \brief (HSMCI_IDR) End of Transmit Buffer Interrupt Disable */ |
| 1420 | #define HSMCI_IDR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IDR) SDIO Interrupt for Slot A Interrupt Disable */ |
| 1421 | #define HSMCI_IDR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */ |
| 1422 | #define HSMCI_IDR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt Disable */ |
| 1423 | #define HSMCI_IDR_RXBUFF (0x1u << 14) /**< \brief (HSMCI_IDR) Receive Buffer Full Interrupt Disable */ |
| 1424 | #define HSMCI_IDR_TXBUFE (0x1u << 15) /**< \brief (HSMCI_IDR) Transmit Buffer Empty Interrupt Disable */ |
| 1425 | #define HSMCI_IDR_RINDE (0x1u << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */ |
| 1426 | #define HSMCI_IDR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */ |
| 1427 | #define HSMCI_IDR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */ |
| 1428 | #define HSMCI_IDR_RENDE (0x1u << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */ |
| 1429 | #define HSMCI_IDR_RTOE (0x1u << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */ |
| 1430 | #define HSMCI_IDR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */ |
| 1431 | #define HSMCI_IDR_DTOE (0x1u << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */ |
| 1432 | #define HSMCI_IDR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */ |
| 1433 | #define HSMCI_IDR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */ |
| 1434 | #define HSMCI_IDR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */ |
| 1435 | #define HSMCI_IDR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */ |
| 1436 | #define HSMCI_IDR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */ |
| 1437 | #define HSMCI_IDR_OVRE (0x1u << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */ |
| 1438 | #define HSMCI_IDR_UNRE (0x1u << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */ |
| 1439 | /* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */ |
| 1440 | #define HSMCI_IMR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */ |
| 1441 | #define HSMCI_IMR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */ |
| 1442 | #define HSMCI_IMR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */ |
| 1443 | #define HSMCI_IMR_BLKE (0x1u << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */ |
| 1444 | #define HSMCI_IMR_DTIP (0x1u << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */ |
| 1445 | #define HSMCI_IMR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */ |
| 1446 | #define HSMCI_IMR_ENDRX (0x1u << 6) /**< \brief (HSMCI_IMR) End of Receive Buffer Interrupt Mask */ |
| 1447 | #define HSMCI_IMR_ENDTX (0x1u << 7) /**< \brief (HSMCI_IMR) End of Transmit Buffer Interrupt Mask */ |
| 1448 | #define HSMCI_IMR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IMR) SDIO Interrupt for Slot A Interrupt Mask */ |
| 1449 | #define HSMCI_IMR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */ |
| 1450 | #define HSMCI_IMR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */ |
| 1451 | #define HSMCI_IMR_RXBUFF (0x1u << 14) /**< \brief (HSMCI_IMR) Receive Buffer Full Interrupt Mask */ |
| 1452 | #define HSMCI_IMR_TXBUFE (0x1u << 15) /**< \brief (HSMCI_IMR) Transmit Buffer Empty Interrupt Mask */ |
| 1453 | #define HSMCI_IMR_RINDE (0x1u << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */ |
| 1454 | #define HSMCI_IMR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */ |
| 1455 | #define HSMCI_IMR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */ |
| 1456 | #define HSMCI_IMR_RENDE (0x1u << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */ |
| 1457 | #define HSMCI_IMR_RTOE (0x1u << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */ |
| 1458 | #define HSMCI_IMR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */ |
| 1459 | #define HSMCI_IMR_DTOE (0x1u << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */ |
| 1460 | #define HSMCI_IMR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */ |
| 1461 | #define HSMCI_IMR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */ |
| 1462 | #define HSMCI_IMR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */ |
| 1463 | #define HSMCI_IMR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */ |
| 1464 | #define HSMCI_IMR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */ |
| 1465 | #define HSMCI_IMR_OVRE (0x1u << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */ |
| 1466 | #define HSMCI_IMR_UNRE (0x1u << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */ |
| 1467 | /* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */ |
| 1468 | #define HSMCI_CFG_FIFOMODE (0x1u << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */ |
| 1469 | #define HSMCI_CFG_FERRCTRL (0x1u << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */ |
| 1470 | #define HSMCI_CFG_HSMODE (0x1u << 8) /**< \brief (HSMCI_CFG) High Speed Mode */ |
| 1471 | #define HSMCI_CFG_LSYNC (0x1u << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */ |
| 1472 | /* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */ |
| 1473 | #define HSMCI_WPMR_WP_EN (0x1u << 0) /**< \brief (HSMCI_WPMR) Write Protection Enable */ |
| 1474 | #define HSMCI_WPMR_WP_KEY_Pos 8 |
| 1475 | #define HSMCI_WPMR_WP_KEY_Msk (0xffffffu << HSMCI_WPMR_WP_KEY_Pos) /**< \brief (HSMCI_WPMR) Write Protection Key password */ |
| 1476 | #define HSMCI_WPMR_WP_KEY(value) ((HSMCI_WPMR_WP_KEY_Msk & ((value) << HSMCI_WPMR_WP_KEY_Pos))) |
| 1477 | /* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */ |
| 1478 | #define HSMCI_WPSR_WP_VS_Pos 0 |
| 1479 | #define HSMCI_WPSR_WP_VS_Msk (0xfu << HSMCI_WPSR_WP_VS_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */ |
| 1480 | #define HSMCI_WPSR_WP_VS_NONE (0x0u << 0) /**< \brief (HSMCI_WPSR) No Write Protection Violation occurred since the last read of this register (WP_SR) */ |
| 1481 | #define HSMCI_WPSR_WP_VS_WRITE (0x1u << 0) /**< \brief (HSMCI_WPSR) Write Protection detected unauthorized attempt to write a control register had occurred (since the last read.) */ |
| 1482 | #define HSMCI_WPSR_WP_VS_RESET (0x2u << 0) /**< \brief (HSMCI_WPSR) Software reset had been performed while Write Protection was enabled (since the last read). */ |
| 1483 | #define HSMCI_WPSR_WP_VS_BOTH (0x3u << 0) /**< \brief (HSMCI_WPSR) Both Write Protection violation and software reset with Write Protection enabled have occurred since the last read. */ |
| 1484 | #define HSMCI_WPSR_WP_VSRC_Pos 8 |
| 1485 | #define HSMCI_WPSR_WP_VSRC_Msk (0xffffu << HSMCI_WPSR_WP_VSRC_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation SouRCe */ |
| 1486 | /* -------- HSMCI_RPR : (HSMCI Offset: 0x100) Receive Pointer Register -------- */ |
| 1487 | #define HSMCI_RPR_RXPTR_Pos 0 |
| 1488 | #define HSMCI_RPR_RXPTR_Msk (0xffffffffu << HSMCI_RPR_RXPTR_Pos) /**< \brief (HSMCI_RPR) Receive Pointer Register */ |
| 1489 | #define HSMCI_RPR_RXPTR(value) ((HSMCI_RPR_RXPTR_Msk & ((value) << HSMCI_RPR_RXPTR_Pos))) |
| 1490 | /* -------- HSMCI_RCR : (HSMCI Offset: 0x104) Receive Counter Register -------- */ |
| 1491 | #define HSMCI_RCR_RXCTR_Pos 0 |
| 1492 | #define HSMCI_RCR_RXCTR_Msk (0xffffu << HSMCI_RCR_RXCTR_Pos) /**< \brief (HSMCI_RCR) Receive Counter Register */ |
| 1493 | #define HSMCI_RCR_RXCTR(value) ((HSMCI_RCR_RXCTR_Msk & ((value) << HSMCI_RCR_RXCTR_Pos))) |
| 1494 | /* -------- HSMCI_TPR : (HSMCI Offset: 0x108) Transmit Pointer Register -------- */ |
| 1495 | #define HSMCI_TPR_TXPTR_Pos 0 |
| 1496 | #define HSMCI_TPR_TXPTR_Msk (0xffffffffu << HSMCI_TPR_TXPTR_Pos) /**< \brief (HSMCI_TPR) Transmit Counter Register */ |
| 1497 | #define HSMCI_TPR_TXPTR(value) ((HSMCI_TPR_TXPTR_Msk & ((value) << HSMCI_TPR_TXPTR_Pos))) |
| 1498 | /* -------- HSMCI_TCR : (HSMCI Offset: 0x10C) Transmit Counter Register -------- */ |
| 1499 | #define HSMCI_TCR_TXCTR_Pos 0 |
| 1500 | #define HSMCI_TCR_TXCTR_Msk (0xffffu << HSMCI_TCR_TXCTR_Pos) /**< \brief (HSMCI_TCR) Transmit Counter Register */ |
| 1501 | #define HSMCI_TCR_TXCTR(value) ((HSMCI_TCR_TXCTR_Msk & ((value) << HSMCI_TCR_TXCTR_Pos))) |
| 1502 | /* -------- HSMCI_RNPR : (HSMCI Offset: 0x110) Receive Next Pointer Register -------- */ |
| 1503 | #define HSMCI_RNPR_RXNPTR_Pos 0 |
| 1504 | #define HSMCI_RNPR_RXNPTR_Msk (0xffffffffu << HSMCI_RNPR_RXNPTR_Pos) /**< \brief (HSMCI_RNPR) Receive Next Pointer */ |
| 1505 | #define HSMCI_RNPR_RXNPTR(value) ((HSMCI_RNPR_RXNPTR_Msk & ((value) << HSMCI_RNPR_RXNPTR_Pos))) |
| 1506 | /* -------- HSMCI_RNCR : (HSMCI Offset: 0x114) Receive Next Counter Register -------- */ |
| 1507 | #define HSMCI_RNCR_RXNCTR_Pos 0 |
| 1508 | #define HSMCI_RNCR_RXNCTR_Msk (0xffffu << HSMCI_RNCR_RXNCTR_Pos) /**< \brief (HSMCI_RNCR) Receive Next Counter */ |
| 1509 | #define HSMCI_RNCR_RXNCTR(value) ((HSMCI_RNCR_RXNCTR_Msk & ((value) << HSMCI_RNCR_RXNCTR_Pos))) |
| 1510 | /* -------- HSMCI_TNPR : (HSMCI Offset: 0x118) Transmit Next Pointer Register -------- */ |
| 1511 | #define HSMCI_TNPR_TXNPTR_Pos 0 |
| 1512 | #define HSMCI_TNPR_TXNPTR_Msk (0xffffffffu << HSMCI_TNPR_TXNPTR_Pos) /**< \brief (HSMCI_TNPR) Transmit Next Pointer */ |
| 1513 | #define HSMCI_TNPR_TXNPTR(value) ((HSMCI_TNPR_TXNPTR_Msk & ((value) << HSMCI_TNPR_TXNPTR_Pos))) |
| 1514 | /* -------- HSMCI_TNCR : (HSMCI Offset: 0x11C) Transmit Next Counter Register -------- */ |
| 1515 | #define HSMCI_TNCR_TXNCTR_Pos 0 |
| 1516 | #define HSMCI_TNCR_TXNCTR_Msk (0xffffu << HSMCI_TNCR_TXNCTR_Pos) /**< \brief (HSMCI_TNCR) Transmit Counter Next */ |
| 1517 | #define HSMCI_TNCR_TXNCTR(value) ((HSMCI_TNCR_TXNCTR_Msk & ((value) << HSMCI_TNCR_TXNCTR_Pos))) |
| 1518 | /* -------- HSMCI_PTCR : (HSMCI Offset: 0x120) Transfer Control Register -------- */ |
| 1519 | #define HSMCI_PTCR_RXTEN (0x1u << 0) /**< \brief (HSMCI_PTCR) Receiver Transfer Enable */ |
| 1520 | #define HSMCI_PTCR_RXTDIS (0x1u << 1) /**< \brief (HSMCI_PTCR) Receiver Transfer Disable */ |
| 1521 | #define HSMCI_PTCR_TXTEN (0x1u << 8) /**< \brief (HSMCI_PTCR) Transmitter Transfer Enable */ |
| 1522 | #define HSMCI_PTCR_TXTDIS (0x1u << 9) /**< \brief (HSMCI_PTCR) Transmitter Transfer Disable */ |
| 1523 | /* -------- HSMCI_PTSR : (HSMCI Offset: 0x124) Transfer Status Register -------- */ |
| 1524 | #define HSMCI_PTSR_RXTEN (0x1u << 0) /**< \brief (HSMCI_PTSR) Receiver Transfer Enable */ |
| 1525 | #define HSMCI_PTSR_TXTEN (0x1u << 8) /**< \brief (HSMCI_PTSR) Transmitter Transfer Enable */ |
| 1526 | /* -------- HSMCI_FIFO[256] : (HSMCI Offset: 0x200) FIFO Memory Aperture0 -------- */ |
| 1527 | #define HSMCI_FIFO_DATA_Pos 0 |
| 1528 | #define HSMCI_FIFO_DATA_Msk (0xffffffffu << HSMCI_FIFO_DATA_Pos) /**< \brief (HSMCI_FIFO[256]) Data to Read or Data to Write */ |
| 1529 | #define HSMCI_FIFO_DATA(value) ((HSMCI_FIFO_DATA_Msk & ((value) << HSMCI_FIFO_DATA_Pos))) |
| 1530 | |
| 1531 | /*@}*/ |
| 1532 | |
| 1533 | /* ============================================================================= */ |
| 1534 | /** SOFTWARE API DEFINITION FOR AHB Bus Matrix */ |
| 1535 | /* ============================================================================= */ |
| 1536 | /** \addtogroup SAM3S_MATRIX AHB Bus Matrix */ |
| 1537 | /*@{*/ |
| 1538 | |
| 1539 | #ifndef __ASSEMBLY__ |
| 1540 | /** \brief Matrix hardware registers */ |
| 1541 | typedef struct { |
| 1542 | RwReg MATRIX_MCFG[4]; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register */ |
| 1543 | RwReg Reserved1[12]; |
| 1544 | RwReg MATRIX_SCFG[5]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */ |
| 1545 | RwReg Reserved2[11]; |
| 1546 | RwReg MATRIX_PRAS0; /**< \brief (Matrix Offset: 0x0080) Priority Register A for Slave 0 */ |
| 1547 | RwReg Reserved3[1]; |
| 1548 | RwReg MATRIX_PRAS1; /**< \brief (Matrix Offset: 0x0088) Priority Register A for Slave 1 */ |
| 1549 | RwReg Reserved4[1]; |
| 1550 | RwReg MATRIX_PRAS2; /**< \brief (Matrix Offset: 0x0090) Priority Register A for Slave 2 */ |
| 1551 | RwReg Reserved5[1]; |
| 1552 | RwReg MATRIX_PRAS3; /**< \brief (Matrix Offset: 0x0098) Priority Register A for Slave 3 */ |
| 1553 | RwReg Reserved6[1]; |
| 1554 | RwReg MATRIX_PRAS4; /**< \brief (Matrix Offset: 0x00A0) Priority Register A for Slave 4 */ |
| 1555 | RwReg Reserved7[1]; |
| 1556 | RwReg Reserved8[27]; |
| 1557 | RwReg CCFG_SYSIO; /**< \brief (Matrix Offset: 0x0114) System I/O Configuration register */ |
| 1558 | RwReg Reserved9[1]; |
| 1559 | RwReg CCFG_SMCNFCS; /**< \brief (Matrix Offset: 0x011C) SMC Chip Select NAND Flash Assignment Register */ |
| 1560 | RwReg Reserved10[49]; |
| 1561 | RwReg MATRIX_WPMR; /**< \brief (Matrix Offset: 0x1E4) Write Protect Mode Register */ |
| 1562 | RoReg MATRIX_WPSR; /**< \brief (Matrix Offset: 0x1E8) Write Protect Status Register */ |
| 1563 | } Matrix; |
| 1564 | #endif /* __ASSEMBLY__ */ |
| 1565 | /* -------- MATRIX_MCFG[4] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */ |
| 1566 | #define MATRIX_MCFG_ULBT_Pos 0 |
| 1567 | #define MATRIX_MCFG_ULBT_Msk (0x7u << MATRIX_MCFG_ULBT_Pos) /**< \brief (MATRIX_MCFG[4]) Undefined Length Burst Type */ |
| 1568 | #define MATRIX_MCFG_ULBT(value) ((MATRIX_MCFG_ULBT_Msk & ((value) << MATRIX_MCFG_ULBT_Pos))) |
| 1569 | /* -------- MATRIX_SCFG[5] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */ |
| 1570 | #define MATRIX_SCFG_SLOT_CYCLE_Pos 0 |
| 1571 | #define MATRIX_SCFG_SLOT_CYCLE_Msk (0xffu << MATRIX_SCFG_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG[5]) Maximum Number of Allowed Cycles for a Burst */ |
| 1572 | #define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos))) |
| 1573 | #define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16 |
| 1574 | #define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG[5]) Default Master Type */ |
| 1575 | #define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos))) |
| 1576 | #define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18 |
| 1577 | #define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0x7u << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG[5]) Fixed Default Master */ |
| 1578 | #define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos))) |
| 1579 | #define MATRIX_SCFG_ARBT_Pos 24 |
| 1580 | #define MATRIX_SCFG_ARBT_Msk (0x3u << MATRIX_SCFG_ARBT_Pos) /**< \brief (MATRIX_SCFG[5]) Arbitration Type */ |
| 1581 | #define MATRIX_SCFG_ARBT(value) ((MATRIX_SCFG_ARBT_Msk & ((value) << MATRIX_SCFG_ARBT_Pos))) |
| 1582 | /* -------- MATRIX_PRAS0 : (MATRIX Offset: 0x0080) Priority Register A for Slave 0 -------- */ |
| 1583 | #define MATRIX_PRAS0_M0PR_Pos 0 |
| 1584 | #define MATRIX_PRAS0_M0PR_Msk (0x3u << MATRIX_PRAS0_M0PR_Pos) /**< \brief (MATRIX_PRAS0) Master 0 Priority */ |
| 1585 | #define MATRIX_PRAS0_M0PR(value) ((MATRIX_PRAS0_M0PR_Msk & ((value) << MATRIX_PRAS0_M0PR_Pos))) |
| 1586 | #define MATRIX_PRAS0_M1PR_Pos 4 |
| 1587 | #define MATRIX_PRAS0_M1PR_Msk (0x3u << MATRIX_PRAS0_M1PR_Pos) /**< \brief (MATRIX_PRAS0) Master 1 Priority */ |
| 1588 | #define MATRIX_PRAS0_M1PR(value) ((MATRIX_PRAS0_M1PR_Msk & ((value) << MATRIX_PRAS0_M1PR_Pos))) |
| 1589 | #define MATRIX_PRAS0_M2PR_Pos 8 |
| 1590 | #define MATRIX_PRAS0_M2PR_Msk (0x3u << MATRIX_PRAS0_M2PR_Pos) /**< \brief (MATRIX_PRAS0) Master 2 Priority */ |
| 1591 | #define MATRIX_PRAS0_M2PR(value) ((MATRIX_PRAS0_M2PR_Msk & ((value) << MATRIX_PRAS0_M2PR_Pos))) |
| 1592 | #define MATRIX_PRAS0_M3PR_Pos 12 |
| 1593 | #define MATRIX_PRAS0_M3PR_Msk (0x3u << MATRIX_PRAS0_M3PR_Pos) /**< \brief (MATRIX_PRAS0) Master 3 Priority */ |
| 1594 | #define MATRIX_PRAS0_M3PR(value) ((MATRIX_PRAS0_M3PR_Msk & ((value) << MATRIX_PRAS0_M3PR_Pos))) |
| 1595 | #define MATRIX_PRAS0_M4PR_Pos 16 |
| 1596 | #define MATRIX_PRAS0_M4PR_Msk (0x3u << MATRIX_PRAS0_M4PR_Pos) /**< \brief (MATRIX_PRAS0) Master 4 Priority */ |
| 1597 | #define MATRIX_PRAS0_M4PR(value) ((MATRIX_PRAS0_M4PR_Msk & ((value) << MATRIX_PRAS0_M4PR_Pos))) |
| 1598 | /* -------- MATRIX_PRAS1 : (MATRIX Offset: 0x0088) Priority Register A for Slave 1 -------- */ |
| 1599 | #define MATRIX_PRAS1_M0PR_Pos 0 |
| 1600 | #define MATRIX_PRAS1_M0PR_Msk (0x3u << MATRIX_PRAS1_M0PR_Pos) /**< \brief (MATRIX_PRAS1) Master 0 Priority */ |
| 1601 | #define MATRIX_PRAS1_M0PR(value) ((MATRIX_PRAS1_M0PR_Msk & ((value) << MATRIX_PRAS1_M0PR_Pos))) |
| 1602 | #define MATRIX_PRAS1_M1PR_Pos 4 |
| 1603 | #define MATRIX_PRAS1_M1PR_Msk (0x3u << MATRIX_PRAS1_M1PR_Pos) /**< \brief (MATRIX_PRAS1) Master 1 Priority */ |
| 1604 | #define MATRIX_PRAS1_M1PR(value) ((MATRIX_PRAS1_M1PR_Msk & ((value) << MATRIX_PRAS1_M1PR_Pos))) |
| 1605 | #define MATRIX_PRAS1_M2PR_Pos 8 |
| 1606 | #define MATRIX_PRAS1_M2PR_Msk (0x3u << MATRIX_PRAS1_M2PR_Pos) /**< \brief (MATRIX_PRAS1) Master 2 Priority */ |
| 1607 | #define MATRIX_PRAS1_M2PR(value) ((MATRIX_PRAS1_M2PR_Msk & ((value) << MATRIX_PRAS1_M2PR_Pos))) |
| 1608 | #define MATRIX_PRAS1_M3PR_Pos 12 |
| 1609 | #define MATRIX_PRAS1_M3PR_Msk (0x3u << MATRIX_PRAS1_M3PR_Pos) /**< \brief (MATRIX_PRAS1) Master 3 Priority */ |
| 1610 | #define MATRIX_PRAS1_M3PR(value) ((MATRIX_PRAS1_M3PR_Msk & ((value) << MATRIX_PRAS1_M3PR_Pos))) |
| 1611 | #define MATRIX_PRAS1_M4PR_Pos 16 |
| 1612 | #define MATRIX_PRAS1_M4PR_Msk (0x3u << MATRIX_PRAS1_M4PR_Pos) /**< \brief (MATRIX_PRAS1) Master 4 Priority */ |
| 1613 | #define MATRIX_PRAS1_M4PR(value) ((MATRIX_PRAS1_M4PR_Msk & ((value) << MATRIX_PRAS1_M4PR_Pos))) |
| 1614 | /* -------- MATRIX_PRAS2 : (MATRIX Offset: 0x0090) Priority Register A for Slave 2 -------- */ |
| 1615 | #define MATRIX_PRAS2_M0PR_Pos 0 |
| 1616 | #define MATRIX_PRAS2_M0PR_Msk (0x3u << MATRIX_PRAS2_M0PR_Pos) /**< \brief (MATRIX_PRAS2) Master 0 Priority */ |
| 1617 | #define MATRIX_PRAS2_M0PR(value) ((MATRIX_PRAS2_M0PR_Msk & ((value) << MATRIX_PRAS2_M0PR_Pos))) |
| 1618 | #define MATRIX_PRAS2_M1PR_Pos 4 |
| 1619 | #define MATRIX_PRAS2_M1PR_Msk (0x3u << MATRIX_PRAS2_M1PR_Pos) /**< \brief (MATRIX_PRAS2) Master 1 Priority */ |
| 1620 | #define MATRIX_PRAS2_M1PR(value) ((MATRIX_PRAS2_M1PR_Msk & ((value) << MATRIX_PRAS2_M1PR_Pos))) |
| 1621 | #define MATRIX_PRAS2_M2PR_Pos 8 |
| 1622 | #define MATRIX_PRAS2_M2PR_Msk (0x3u << MATRIX_PRAS2_M2PR_Pos) /**< \brief (MATRIX_PRAS2) Master 2 Priority */ |
| 1623 | #define MATRIX_PRAS2_M2PR(value) ((MATRIX_PRAS2_M2PR_Msk & ((value) << MATRIX_PRAS2_M2PR_Pos))) |
| 1624 | #define MATRIX_PRAS2_M3PR_Pos 12 |
| 1625 | #define MATRIX_PRAS2_M3PR_Msk (0x3u << MATRIX_PRAS2_M3PR_Pos) /**< \brief (MATRIX_PRAS2) Master 3 Priority */ |
| 1626 | #define MATRIX_PRAS2_M3PR(value) ((MATRIX_PRAS2_M3PR_Msk & ((value) << MATRIX_PRAS2_M3PR_Pos))) |
| 1627 | #define MATRIX_PRAS2_M4PR_Pos 16 |
| 1628 | #define MATRIX_PRAS2_M4PR_Msk (0x3u << MATRIX_PRAS2_M4PR_Pos) /**< \brief (MATRIX_PRAS2) Master 4 Priority */ |
| 1629 | #define MATRIX_PRAS2_M4PR(value) ((MATRIX_PRAS2_M4PR_Msk & ((value) << MATRIX_PRAS2_M4PR_Pos))) |
| 1630 | /* -------- MATRIX_PRAS3 : (MATRIX Offset: 0x0098) Priority Register A for Slave 3 -------- */ |
| 1631 | #define MATRIX_PRAS3_M0PR_Pos 0 |
| 1632 | #define MATRIX_PRAS3_M0PR_Msk (0x3u << MATRIX_PRAS3_M0PR_Pos) /**< \brief (MATRIX_PRAS3) Master 0 Priority */ |
| 1633 | #define MATRIX_PRAS3_M0PR(value) ((MATRIX_PRAS3_M0PR_Msk & ((value) << MATRIX_PRAS3_M0PR_Pos))) |
| 1634 | #define MATRIX_PRAS3_M1PR_Pos 4 |
| 1635 | #define MATRIX_PRAS3_M1PR_Msk (0x3u << MATRIX_PRAS3_M1PR_Pos) /**< \brief (MATRIX_PRAS3) Master 1 Priority */ |
| 1636 | #define MATRIX_PRAS3_M1PR(value) ((MATRIX_PRAS3_M1PR_Msk & ((value) << MATRIX_PRAS3_M1PR_Pos))) |
| 1637 | #define MATRIX_PRAS3_M2PR_Pos 8 |
| 1638 | #define MATRIX_PRAS3_M2PR_Msk (0x3u << MATRIX_PRAS3_M2PR_Pos) /**< \brief (MATRIX_PRAS3) Master 2 Priority */ |
| 1639 | #define MATRIX_PRAS3_M2PR(value) ((MATRIX_PRAS3_M2PR_Msk & ((value) << MATRIX_PRAS3_M2PR_Pos))) |
| 1640 | #define MATRIX_PRAS3_M3PR_Pos 12 |
| 1641 | #define MATRIX_PRAS3_M3PR_Msk (0x3u << MATRIX_PRAS3_M3PR_Pos) /**< \brief (MATRIX_PRAS3) Master 3 Priority */ |
| 1642 | #define MATRIX_PRAS3_M3PR(value) ((MATRIX_PRAS3_M3PR_Msk & ((value) << MATRIX_PRAS3_M3PR_Pos))) |
| 1643 | #define MATRIX_PRAS3_M4PR_Pos 16 |
| 1644 | #define MATRIX_PRAS3_M4PR_Msk (0x3u << MATRIX_PRAS3_M4PR_Pos) /**< \brief (MATRIX_PRAS3) Master 4 Priority */ |
| 1645 | #define MATRIX_PRAS3_M4PR(value) ((MATRIX_PRAS3_M4PR_Msk & ((value) << MATRIX_PRAS3_M4PR_Pos))) |
| 1646 | /* -------- MATRIX_PRAS4 : (MATRIX Offset: 0x00A0) Priority Register A for Slave 4 -------- */ |
| 1647 | #define MATRIX_PRAS4_M0PR_Pos 0 |
| 1648 | #define MATRIX_PRAS4_M0PR_Msk (0x3u << MATRIX_PRAS4_M0PR_Pos) /**< \brief (MATRIX_PRAS4) Master 0 Priority */ |
| 1649 | #define MATRIX_PRAS4_M0PR(value) ((MATRIX_PRAS4_M0PR_Msk & ((value) << MATRIX_PRAS4_M0PR_Pos))) |
| 1650 | #define MATRIX_PRAS4_M1PR_Pos 4 |
| 1651 | #define MATRIX_PRAS4_M1PR_Msk (0x3u << MATRIX_PRAS4_M1PR_Pos) /**< \brief (MATRIX_PRAS4) Master 1 Priority */ |
| 1652 | #define MATRIX_PRAS4_M1PR(value) ((MATRIX_PRAS4_M1PR_Msk & ((value) << MATRIX_PRAS4_M1PR_Pos))) |
| 1653 | #define MATRIX_PRAS4_M2PR_Pos 8 |
| 1654 | #define MATRIX_PRAS4_M2PR_Msk (0x3u << MATRIX_PRAS4_M2PR_Pos) /**< \brief (MATRIX_PRAS4) Master 2 Priority */ |
| 1655 | #define MATRIX_PRAS4_M2PR(value) ((MATRIX_PRAS4_M2PR_Msk & ((value) << MATRIX_PRAS4_M2PR_Pos))) |
| 1656 | #define MATRIX_PRAS4_M3PR_Pos 12 |
| 1657 | #define MATRIX_PRAS4_M3PR_Msk (0x3u << MATRIX_PRAS4_M3PR_Pos) /**< \brief (MATRIX_PRAS4) Master 3 Priority */ |
| 1658 | #define MATRIX_PRAS4_M3PR(value) ((MATRIX_PRAS4_M3PR_Msk & ((value) << MATRIX_PRAS4_M3PR_Pos))) |
| 1659 | #define MATRIX_PRAS4_M4PR_Pos 16 |
| 1660 | #define MATRIX_PRAS4_M4PR_Msk (0x3u << MATRIX_PRAS4_M4PR_Pos) /**< \brief (MATRIX_PRAS4) Master 4 Priority */ |
| 1661 | #define MATRIX_PRAS4_M4PR(value) ((MATRIX_PRAS4_M4PR_Msk & ((value) << MATRIX_PRAS4_M4PR_Pos))) |
| 1662 | /* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System I/O Configuration register -------- */ |
| 1663 | #define CCFG_SYSIO_SYSIO4 (0x1u << 4) /**< \brief (CCFG_SYSIO) PB4 or TDI Assignment */ |
| 1664 | #define CCFG_SYSIO_SYSIO5 (0x1u << 5) /**< \brief (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment */ |
| 1665 | #define CCFG_SYSIO_SYSIO6 (0x1u << 6) /**< \brief (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment */ |
| 1666 | #define CCFG_SYSIO_SYSIO7 (0x1u << 7) /**< \brief (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment */ |
| 1667 | #define CCFG_SYSIO_SYSIO10 (0x1u << 10) /**< \brief (CCFG_SYSIO) PB10 or DDM Assignment */ |
| 1668 | #define CCFG_SYSIO_SYSIO11 (0x1u << 11) /**< \brief (CCFG_SYSIO) PB11 or DDP Assignment */ |
| 1669 | #define CCFG_SYSIO_SYSIO12 (0x1u << 12) /**< \brief (CCFG_SYSIO) PB12 or ERASE Assignment */ |
| 1670 | /* -------- CCFG_SMCNFCS : (MATRIX Offset: 0x011C) SMC Chip Select NAND Flash Assignment Register -------- */ |
| 1671 | #define CCFG_SMCNFCS_SMC_NFCS0 (0x1u << 0) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 0 Assignment */ |
| 1672 | #define CCFG_SMCNFCS_SMC_NFCS1 (0x1u << 1) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 1 Assignment */ |
| 1673 | #define CCFG_SMCNFCS_SMC_NFCS2 (0x1u << 2) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 2 Assignment */ |
| 1674 | #define CCFG_SMCNFCS_SMC_NFCS3 (0x1u << 3) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 3 Assignment */ |
| 1675 | /* -------- MATRIX_WPMR : (MATRIX Offset: 0x1E4) Write Protect Mode Register -------- */ |
| 1676 | #define MATRIX_WPMR_WPEN (0x1u << 0) /**< \brief (MATRIX_WPMR) Write Protect ENable */ |
| 1677 | #define MATRIX_WPMR_WPKEY_Pos 8 |
| 1678 | #define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos) /**< \brief (MATRIX_WPMR) Write Protect KEY (Write-only) */ |
| 1679 | #define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos))) |
| 1680 | /* -------- MATRIX_WPSR : (MATRIX Offset: 0x1E8) Write Protect Status Register -------- */ |
| 1681 | #define MATRIX_WPSR_WPVS (0x1u << 0) /**< \brief (MATRIX_WPSR) Write Protect Violation Status */ |
| 1682 | #define MATRIX_WPSR_WPVSRC_Pos 8 |
| 1683 | #define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos) /**< \brief (MATRIX_WPSR) Write Protect Violation Source */ |
| 1684 | |
| 1685 | /*@}*/ |
| 1686 | |
| 1687 | /* ============================================================================= */ |
| 1688 | /** SOFTWARE API DEFINITION FOR Peripheral DMA Controller */ |
| 1689 | /* ============================================================================= */ |
| 1690 | /** \addtogroup SAM3S_PDC Peripheral DMA Controller */ |
| 1691 | /*@{*/ |
| 1692 | |
| 1693 | #ifndef __ASSEMBLY__ |
| 1694 | /** \brief Pdc hardware registers */ |
| 1695 | typedef struct { |
| 1696 | RwReg Reserved1[64]; |
| 1697 | RwReg PERIPH_RPR; /**< \brief (Pdc Offset: 0x100) Receive Pointer Register */ |
| 1698 | RwReg PERIPH_RCR; /**< \brief (Pdc Offset: 0x104) Receive Counter Register */ |
| 1699 | RwReg PERIPH_TPR; /**< \brief (Pdc Offset: 0x108) Transmit Pointer Register */ |
| 1700 | RwReg PERIPH_TCR; /**< \brief (Pdc Offset: 0x10C) Transmit Counter Register */ |
| 1701 | RwReg PERIPH_RNPR; /**< \brief (Pdc Offset: 0x110) Receive Next Pointer Register */ |
| 1702 | RwReg PERIPH_RNCR; /**< \brief (Pdc Offset: 0x114) Receive Next Counter Register */ |
| 1703 | RwReg PERIPH_TNPR; /**< \brief (Pdc Offset: 0x118) Transmit Next Pointer Register */ |
| 1704 | RwReg PERIPH_TNCR; /**< \brief (Pdc Offset: 0x11C) Transmit Next Counter Register */ |
| 1705 | WoReg PERIPH_PTCR; /**< \brief (Pdc Offset: 0x120) Transfer Control Register */ |
| 1706 | RoReg PERIPH_PTSR; /**< \brief (Pdc Offset: 0x124) Transfer Status Register */ |
| 1707 | } Pdc; |
| 1708 | #endif /* __ASSEMBLY__ */ |
| 1709 | /* -------- PERIPH_RPR : (PDC Offset: 0x100) Receive Pointer Register -------- */ |
| 1710 | #define PERIPH_RPR_RXPTR_Pos 0 |
| 1711 | #define PERIPH_RPR_RXPTR_Msk (0xffffffffu << PERIPH_RPR_RXPTR_Pos) /**< \brief (PERIPH_RPR) Receive Pointer Register */ |
| 1712 | #define PERIPH_RPR_RXPTR(value) ((PERIPH_RPR_RXPTR_Msk & ((value) << PERIPH_RPR_RXPTR_Pos))) |
| 1713 | /* -------- PERIPH_RCR : (PDC Offset: 0x104) Receive Counter Register -------- */ |
| 1714 | #define PERIPH_RCR_RXCTR_Pos 0 |
| 1715 | #define PERIPH_RCR_RXCTR_Msk (0xffffu << PERIPH_RCR_RXCTR_Pos) /**< \brief (PERIPH_RCR) Receive Counter Register */ |
| 1716 | #define PERIPH_RCR_RXCTR(value) ((PERIPH_RCR_RXCTR_Msk & ((value) << PERIPH_RCR_RXCTR_Pos))) |
| 1717 | /* -------- PERIPH_TPR : (PDC Offset: 0x108) Transmit Pointer Register -------- */ |
| 1718 | #define PERIPH_TPR_TXPTR_Pos 0 |
| 1719 | #define PERIPH_TPR_TXPTR_Msk (0xffffffffu << PERIPH_TPR_TXPTR_Pos) /**< \brief (PERIPH_TPR) Transmit Counter Register */ |
| 1720 | #define PERIPH_TPR_TXPTR(value) ((PERIPH_TPR_TXPTR_Msk & ((value) << PERIPH_TPR_TXPTR_Pos))) |
| 1721 | /* -------- PERIPH_TCR : (PDC Offset: 0x10C) Transmit Counter Register -------- */ |
| 1722 | #define PERIPH_TCR_TXCTR_Pos 0 |
| 1723 | #define PERIPH_TCR_TXCTR_Msk (0xffffu << PERIPH_TCR_TXCTR_Pos) /**< \brief (PERIPH_TCR) Transmit Counter Register */ |
| 1724 | #define PERIPH_TCR_TXCTR(value) ((PERIPH_TCR_TXCTR_Msk & ((value) << PERIPH_TCR_TXCTR_Pos))) |
| 1725 | /* -------- PERIPH_RNPR : (PDC Offset: 0x110) Receive Next Pointer Register -------- */ |
| 1726 | #define PERIPH_RNPR_RXNPTR_Pos 0 |
| 1727 | #define PERIPH_RNPR_RXNPTR_Msk (0xffffffffu << PERIPH_RNPR_RXNPTR_Pos) /**< \brief (PERIPH_RNPR) Receive Next Pointer */ |
| 1728 | #define PERIPH_RNPR_RXNPTR(value) ((PERIPH_RNPR_RXNPTR_Msk & ((value) << PERIPH_RNPR_RXNPTR_Pos))) |
| 1729 | /* -------- PERIPH_RNCR : (PDC Offset: 0x114) Receive Next Counter Register -------- */ |
| 1730 | #define PERIPH_RNCR_RXNCTR_Pos 0 |
| 1731 | #define PERIPH_RNCR_RXNCTR_Msk (0xffffu << PERIPH_RNCR_RXNCTR_Pos) /**< \brief (PERIPH_RNCR) Receive Next Counter */ |
| 1732 | #define PERIPH_RNCR_RXNCTR(value) ((PERIPH_RNCR_RXNCTR_Msk & ((value) << PERIPH_RNCR_RXNCTR_Pos))) |
| 1733 | /* -------- PERIPH_TNPR : (PDC Offset: 0x118) Transmit Next Pointer Register -------- */ |
| 1734 | #define PERIPH_TNPR_TXNPTR_Pos 0 |
| 1735 | #define PERIPH_TNPR_TXNPTR_Msk (0xffffffffu << PERIPH_TNPR_TXNPTR_Pos) /**< \brief (PERIPH_TNPR) Transmit Next Pointer */ |
| 1736 | #define PERIPH_TNPR_TXNPTR(value) ((PERIPH_TNPR_TXNPTR_Msk & ((value) << PERIPH_TNPR_TXNPTR_Pos))) |
| 1737 | /* -------- PERIPH_TNCR : (PDC Offset: 0x11C) Transmit Next Counter Register -------- */ |
| 1738 | #define PERIPH_TNCR_TXNCTR_Pos 0 |
| 1739 | #define PERIPH_TNCR_TXNCTR_Msk (0xffffu << PERIPH_TNCR_TXNCTR_Pos) /**< \brief (PERIPH_TNCR) Transmit Counter Next */ |
| 1740 | #define PERIPH_TNCR_TXNCTR(value) ((PERIPH_TNCR_TXNCTR_Msk & ((value) << PERIPH_TNCR_TXNCTR_Pos))) |
| 1741 | /* -------- PERIPH_PTCR : (PDC Offset: 0x120) Transfer Control Register -------- */ |
| 1742 | #define PERIPH_PTCR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTCR) Receiver Transfer Enable */ |
| 1743 | #define PERIPH_PTCR_RXTDIS (0x1u << 1) /**< \brief (PERIPH_PTCR) Receiver Transfer Disable */ |
| 1744 | #define PERIPH_PTCR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTCR) Transmitter Transfer Enable */ |
| 1745 | #define PERIPH_PTCR_TXTDIS (0x1u << 9) /**< \brief (PERIPH_PTCR) Transmitter Transfer Disable */ |
| 1746 | /* -------- PERIPH_PTSR : (PDC Offset: 0x124) Transfer Status Register -------- */ |
| 1747 | #define PERIPH_PTSR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTSR) Receiver Transfer Enable */ |
| 1748 | #define PERIPH_PTSR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTSR) Transmitter Transfer Enable */ |
| 1749 | |
| 1750 | /*@}*/ |
| 1751 | |
| 1752 | /* ============================================================================= */ |
| 1753 | /** SOFTWARE API DEFINITION FOR Parallel Input/Output */ |
| 1754 | /* ============================================================================= */ |
| 1755 | /** \addtogroup SAM3S_PIO Parallel Input/Output */ |
| 1756 | /*@{*/ |
| 1757 | |
| 1758 | #ifndef __ASSEMBLY__ |
| 1759 | /** \brief Pio hardware registers */ |
| 1760 | typedef struct { |
| 1761 | WoReg PIO_PER; /**< \brief (Pio Offset: 0x0000) PIO Enable Register */ |
| 1762 | WoReg PIO_PDR; /**< \brief (Pio Offset: 0x0004) PIO Disable Register */ |
| 1763 | RoReg PIO_PSR; /**< \brief (Pio Offset: 0x0008) PIO Status Register */ |
| 1764 | RwReg Reserved1[1]; |
| 1765 | WoReg PIO_OER; /**< \brief (Pio Offset: 0x0010) Output Enable Register */ |
| 1766 | WoReg PIO_ODR; /**< \brief (Pio Offset: 0x0014) Output Disable Register */ |
| 1767 | RoReg PIO_OSR; /**< \brief (Pio Offset: 0x0018) Output Status Register */ |
| 1768 | RwReg Reserved2[1]; |
| 1769 | WoReg PIO_IFER; /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */ |
| 1770 | WoReg PIO_IFDR; /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */ |
| 1771 | RoReg PIO_IFSR; /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */ |
| 1772 | RwReg Reserved3[1]; |
| 1773 | WoReg PIO_SODR; /**< \brief (Pio Offset: 0x0030) Set Output Data Register */ |
| 1774 | WoReg PIO_CODR; /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */ |
| 1775 | RwReg PIO_ODSR; /**< \brief (Pio Offset: 0x0038) Output Data Status Register */ |
| 1776 | RoReg PIO_PDSR; /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */ |
| 1777 | WoReg PIO_IER; /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */ |
| 1778 | WoReg PIO_IDR; /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */ |
| 1779 | RoReg PIO_IMR; /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */ |
| 1780 | RoReg PIO_ISR; /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */ |
| 1781 | WoReg PIO_MDER; /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */ |
| 1782 | WoReg PIO_MDDR; /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */ |
| 1783 | RoReg PIO_MDSR; /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */ |
| 1784 | RwReg Reserved4[1]; |
| 1785 | WoReg PIO_PUDR; /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */ |
| 1786 | WoReg PIO_PUER; /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */ |
| 1787 | RoReg PIO_PUSR; /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */ |
| 1788 | RwReg Reserved5[1]; |
| 1789 | RwReg PIO_ABCDSR[2]; /**< \brief (Pio Offset: 0x0070) Peripheral Select Register */ |
| 1790 | RwReg Reserved6[2]; |
| 1791 | WoReg PIO_IFSCDR; /**< \brief (Pio Offset: 0x0080) Input Filter Slow Clock Disable Register */ |
| 1792 | WoReg PIO_IFSCER; /**< \brief (Pio Offset: 0x0084) Input Filter Slow Clock Enable Register */ |
| 1793 | RoReg PIO_IFSCSR; /**< \brief (Pio Offset: 0x0088) Input Filter Slow Clock Status Register */ |
| 1794 | RwReg PIO_SCDR; /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */ |
| 1795 | WoReg PIO_PPDDR; /**< \brief (Pio Offset: 0x0090) Pad Pull-down Disable Register */ |
| 1796 | WoReg PIO_PPDER; /**< \brief (Pio Offset: 0x0094) Pad Pull-down Enable Register */ |
| 1797 | RoReg PIO_PPDSR; /**< \brief (Pio Offset: 0x0098) Pad Pull-down Status Register */ |
| 1798 | RwReg Reserved7[1]; |
| 1799 | WoReg PIO_OWER; /**< \brief (Pio Offset: 0x00A0) Output Write Enable */ |
| 1800 | WoReg PIO_OWDR; /**< \brief (Pio Offset: 0x00A4) Output Write Disable */ |
| 1801 | RoReg PIO_OWSR; /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */ |
| 1802 | RwReg Reserved8[1]; |
| 1803 | WoReg PIO_AIMER; /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */ |
| 1804 | WoReg PIO_AIMDR; /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disables Register */ |
| 1805 | RoReg PIO_AIMMR; /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */ |
| 1806 | RwReg Reserved9[1]; |
| 1807 | WoReg PIO_ESR; /**< \brief (Pio Offset: 0x00C0) Edge Select Register */ |
| 1808 | WoReg PIO_LSR; /**< \brief (Pio Offset: 0x00C4) Level Select Register */ |
| 1809 | RoReg PIO_ELSR; /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */ |
| 1810 | RwReg Reserved10[1]; |
| 1811 | WoReg PIO_FELLSR; /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low Level Select Register */ |
| 1812 | WoReg PIO_REHLSR; /**< \brief (Pio Offset: 0x00D4) Rising Edge/ High Level Select Register */ |
| 1813 | RoReg PIO_FRLHSR; /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */ |
| 1814 | RwReg Reserved11[1]; |
| 1815 | RoReg PIO_LOCKSR; /**< \brief (Pio Offset: 0x00E0) Lock Status */ |
| 1816 | RwReg PIO_WPMR; /**< \brief (Pio Offset: 0x00E4) Write Protect Mode Register */ |
| 1817 | RoReg PIO_WPSR; /**< \brief (Pio Offset: 0x00E8) Write Protect Status Register */ |
| 1818 | RwReg Reserved12[5]; |
| 1819 | RwReg PIO_SCHMITT; /**< \brief (Pio Offset: 0x0100) Schmitt Trigger Register */ |
| 1820 | RwReg Reserved13[19]; |
| 1821 | RwReg PIO_PCMR; /**< \brief (Pio Offset: 0x150) Parallel Capture Mode Register */ |
| 1822 | WoReg PIO_PCIER; /**< \brief (Pio Offset: 0x154) Parallel Capture Interrupt Enable Register */ |
| 1823 | WoReg PIO_PCIDR; /**< \brief (Pio Offset: 0x158) Parallel Capture Interrupt Disable Register */ |
| 1824 | RoReg PIO_PCIMR; /**< \brief (Pio Offset: 0x15C) Parallel Capture Interrupt Mask Register */ |
| 1825 | RoReg PIO_PCISR; /**< \brief (Pio Offset: 0x160) Parallel Capture Interrupt Status Register */ |
| 1826 | RoReg PIO_PCRHR; /**< \brief (Pio Offset: 0x164) Parallel Capture Reception Holding Register */ |
| 1827 | RwReg PIO_RPR; /**< \brief (Pio Offset: 0x168) Receive Pointer Register */ |
| 1828 | RwReg PIO_RCR; /**< \brief (Pio Offset: 0x16C) Receive Counter Register */ |
| 1829 | RwReg PIO_TPR; /**< \brief (Pio Offset: 0x170) Transmit Pointer Register */ |
| 1830 | RwReg PIO_TCR; /**< \brief (Pio Offset: 0x174) Transmit Counter Register */ |
| 1831 | RwReg PIO_RNPR; /**< \brief (Pio Offset: 0x178) Receive Next Pointer Register */ |
| 1832 | RwReg PIO_RNCR; /**< \brief (Pio Offset: 0x17C) Receive Next Counter Register */ |
| 1833 | RwReg PIO_TNPR; /**< \brief (Pio Offset: 0x180) Transmit Next Pointer Register */ |
| 1834 | RwReg PIO_TNCR; /**< \brief (Pio Offset: 0x184) Transmit Next Counter Register */ |
| 1835 | WoReg PIO_PTCR; /**< \brief (Pio Offset: 0x188) Transfer Control Register */ |
| 1836 | RoReg PIO_PTSR; /**< \brief (Pio Offset: 0x18C) Transfer Status Register */ |
| 1837 | } Pio; |
| 1838 | #endif /* __ASSEMBLY__ */ |
| 1839 | /* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */ |
| 1840 | #define PIO_PER_P0 (0x1u << 0) /**< \brief (PIO_PER) PIO Enable */ |
| 1841 | #define PIO_PER_P1 (0x1u << 1) /**< \brief (PIO_PER) PIO Enable */ |
| 1842 | #define PIO_PER_P2 (0x1u << 2) /**< \brief (PIO_PER) PIO Enable */ |
| 1843 | #define PIO_PER_P3 (0x1u << 3) /**< \brief (PIO_PER) PIO Enable */ |
| 1844 | #define PIO_PER_P4 (0x1u << 4) /**< \brief (PIO_PER) PIO Enable */ |
| 1845 | #define PIO_PER_P5 (0x1u << 5) /**< \brief (PIO_PER) PIO Enable */ |
| 1846 | #define PIO_PER_P6 (0x1u << 6) /**< \brief (PIO_PER) PIO Enable */ |
| 1847 | #define PIO_PER_P7 (0x1u << 7) /**< \brief (PIO_PER) PIO Enable */ |
| 1848 | #define PIO_PER_P8 (0x1u << 8) /**< \brief (PIO_PER) PIO Enable */ |
| 1849 | #define PIO_PER_P9 (0x1u << 9) /**< \brief (PIO_PER) PIO Enable */ |
| 1850 | #define PIO_PER_P10 (0x1u << 10) /**< \brief (PIO_PER) PIO Enable */ |
| 1851 | #define PIO_PER_P11 (0x1u << 11) /**< \brief (PIO_PER) PIO Enable */ |
| 1852 | #define PIO_PER_P12 (0x1u << 12) /**< \brief (PIO_PER) PIO Enable */ |
| 1853 | #define PIO_PER_P13 (0x1u << 13) /**< \brief (PIO_PER) PIO Enable */ |
| 1854 | #define PIO_PER_P14 (0x1u << 14) /**< \brief (PIO_PER) PIO Enable */ |
| 1855 | #define PIO_PER_P15 (0x1u << 15) /**< \brief (PIO_PER) PIO Enable */ |
| 1856 | #define PIO_PER_P16 (0x1u << 16) /**< \brief (PIO_PER) PIO Enable */ |
| 1857 | #define PIO_PER_P17 (0x1u << 17) /**< \brief (PIO_PER) PIO Enable */ |
| 1858 | #define PIO_PER_P18 (0x1u << 18) /**< \brief (PIO_PER) PIO Enable */ |
| 1859 | #define PIO_PER_P19 (0x1u << 19) /**< \brief (PIO_PER) PIO Enable */ |
| 1860 | #define PIO_PER_P20 (0x1u << 20) /**< \brief (PIO_PER) PIO Enable */ |
| 1861 | #define PIO_PER_P21 (0x1u << 21) /**< \brief (PIO_PER) PIO Enable */ |
| 1862 | #define PIO_PER_P22 (0x1u << 22) /**< \brief (PIO_PER) PIO Enable */ |
| 1863 | #define PIO_PER_P23 (0x1u << 23) /**< \brief (PIO_PER) PIO Enable */ |
| 1864 | #define PIO_PER_P24 (0x1u << 24) /**< \brief (PIO_PER) PIO Enable */ |
| 1865 | #define PIO_PER_P25 (0x1u << 25) /**< \brief (PIO_PER) PIO Enable */ |
| 1866 | #define PIO_PER_P26 (0x1u << 26) /**< \brief (PIO_PER) PIO Enable */ |
| 1867 | #define PIO_PER_P27 (0x1u << 27) /**< \brief (PIO_PER) PIO Enable */ |
| 1868 | #define PIO_PER_P28 (0x1u << 28) /**< \brief (PIO_PER) PIO Enable */ |
| 1869 | #define PIO_PER_P29 (0x1u << 29) /**< \brief (PIO_PER) PIO Enable */ |
| 1870 | #define PIO_PER_P30 (0x1u << 30) /**< \brief (PIO_PER) PIO Enable */ |
| 1871 | #define PIO_PER_P31 (0x1u << 31) /**< \brief (PIO_PER) PIO Enable */ |
| 1872 | /* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */ |
| 1873 | #define PIO_PDR_P0 (0x1u << 0) /**< \brief (PIO_PDR) PIO Disable */ |
| 1874 | #define PIO_PDR_P1 (0x1u << 1) /**< \brief (PIO_PDR) PIO Disable */ |
| 1875 | #define PIO_PDR_P2 (0x1u << 2) /**< \brief (PIO_PDR) PIO Disable */ |
| 1876 | #define PIO_PDR_P3 (0x1u << 3) /**< \brief (PIO_PDR) PIO Disable */ |
| 1877 | #define PIO_PDR_P4 (0x1u << 4) /**< \brief (PIO_PDR) PIO Disable */ |
| 1878 | #define PIO_PDR_P5 (0x1u << 5) /**< \brief (PIO_PDR) PIO Disable */ |
| 1879 | #define PIO_PDR_P6 (0x1u << 6) /**< \brief (PIO_PDR) PIO Disable */ |
| 1880 | #define PIO_PDR_P7 (0x1u << 7) /**< \brief (PIO_PDR) PIO Disable */ |
| 1881 | #define PIO_PDR_P8 (0x1u << 8) /**< \brief (PIO_PDR) PIO Disable */ |
| 1882 | #define PIO_PDR_P9 (0x1u << 9) /**< \brief (PIO_PDR) PIO Disable */ |
| 1883 | #define PIO_PDR_P10 (0x1u << 10) /**< \brief (PIO_PDR) PIO Disable */ |
| 1884 | #define PIO_PDR_P11 (0x1u << 11) /**< \brief (PIO_PDR) PIO Disable */ |
| 1885 | #define PIO_PDR_P12 (0x1u << 12) /**< \brief (PIO_PDR) PIO Disable */ |
| 1886 | #define PIO_PDR_P13 (0x1u << 13) /**< \brief (PIO_PDR) PIO Disable */ |
| 1887 | #define PIO_PDR_P14 (0x1u << 14) /**< \brief (PIO_PDR) PIO Disable */ |
| 1888 | #define PIO_PDR_P15 (0x1u << 15) /**< \brief (PIO_PDR) PIO Disable */ |
| 1889 | #define PIO_PDR_P16 (0x1u << 16) /**< \brief (PIO_PDR) PIO Disable */ |
| 1890 | #define PIO_PDR_P17 (0x1u << 17) /**< \brief (PIO_PDR) PIO Disable */ |
| 1891 | #define PIO_PDR_P18 (0x1u << 18) /**< \brief (PIO_PDR) PIO Disable */ |
| 1892 | #define PIO_PDR_P19 (0x1u << 19) /**< \brief (PIO_PDR) PIO Disable */ |
| 1893 | #define PIO_PDR_P20 (0x1u << 20) /**< \brief (PIO_PDR) PIO Disable */ |
| 1894 | #define PIO_PDR_P21 (0x1u << 21) /**< \brief (PIO_PDR) PIO Disable */ |
| 1895 | #define PIO_PDR_P22 (0x1u << 22) /**< \brief (PIO_PDR) PIO Disable */ |
| 1896 | #define PIO_PDR_P23 (0x1u << 23) /**< \brief (PIO_PDR) PIO Disable */ |
| 1897 | #define PIO_PDR_P24 (0x1u << 24) /**< \brief (PIO_PDR) PIO Disable */ |
| 1898 | #define PIO_PDR_P25 (0x1u << 25) /**< \brief (PIO_PDR) PIO Disable */ |
| 1899 | #define PIO_PDR_P26 (0x1u << 26) /**< \brief (PIO_PDR) PIO Disable */ |
| 1900 | #define PIO_PDR_P27 (0x1u << 27) /**< \brief (PIO_PDR) PIO Disable */ |
| 1901 | #define PIO_PDR_P28 (0x1u << 28) /**< \brief (PIO_PDR) PIO Disable */ |
| 1902 | #define PIO_PDR_P29 (0x1u << 29) /**< \brief (PIO_PDR) PIO Disable */ |
| 1903 | #define PIO_PDR_P30 (0x1u << 30) /**< \brief (PIO_PDR) PIO Disable */ |
| 1904 | #define PIO_PDR_P31 (0x1u << 31) /**< \brief (PIO_PDR) PIO Disable */ |
| 1905 | /* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */ |
| 1906 | #define PIO_PSR_P0 (0x1u << 0) /**< \brief (PIO_PSR) PIO Status */ |
| 1907 | #define PIO_PSR_P1 (0x1u << 1) /**< \brief (PIO_PSR) PIO Status */ |
| 1908 | #define PIO_PSR_P2 (0x1u << 2) /**< \brief (PIO_PSR) PIO Status */ |
| 1909 | #define PIO_PSR_P3 (0x1u << 3) /**< \brief (PIO_PSR) PIO Status */ |
| 1910 | #define PIO_PSR_P4 (0x1u << 4) /**< \brief (PIO_PSR) PIO Status */ |
| 1911 | #define PIO_PSR_P5 (0x1u << 5) /**< \brief (PIO_PSR) PIO Status */ |
| 1912 | #define PIO_PSR_P6 (0x1u << 6) /**< \brief (PIO_PSR) PIO Status */ |
| 1913 | #define PIO_PSR_P7 (0x1u << 7) /**< \brief (PIO_PSR) PIO Status */ |
| 1914 | #define PIO_PSR_P8 (0x1u << 8) /**< \brief (PIO_PSR) PIO Status */ |
| 1915 | #define PIO_PSR_P9 (0x1u << 9) /**< \brief (PIO_PSR) PIO Status */ |
| 1916 | #define PIO_PSR_P10 (0x1u << 10) /**< \brief (PIO_PSR) PIO Status */ |
| 1917 | #define PIO_PSR_P11 (0x1u << 11) /**< \brief (PIO_PSR) PIO Status */ |
| 1918 | #define PIO_PSR_P12 (0x1u << 12) /**< \brief (PIO_PSR) PIO Status */ |
| 1919 | #define PIO_PSR_P13 (0x1u << 13) /**< \brief (PIO_PSR) PIO Status */ |
| 1920 | #define PIO_PSR_P14 (0x1u << 14) /**< \brief (PIO_PSR) PIO Status */ |
| 1921 | #define PIO_PSR_P15 (0x1u << 15) /**< \brief (PIO_PSR) PIO Status */ |
| 1922 | #define PIO_PSR_P16 (0x1u << 16) /**< \brief (PIO_PSR) PIO Status */ |
| 1923 | #define PIO_PSR_P17 (0x1u << 17) /**< \brief (PIO_PSR) PIO Status */ |
| 1924 | #define PIO_PSR_P18 (0x1u << 18) /**< \brief (PIO_PSR) PIO Status */ |
| 1925 | #define PIO_PSR_P19 (0x1u << 19) /**< \brief (PIO_PSR) PIO Status */ |
| 1926 | #define PIO_PSR_P20 (0x1u << 20) /**< \brief (PIO_PSR) PIO Status */ |
| 1927 | #define PIO_PSR_P21 (0x1u << 21) /**< \brief (PIO_PSR) PIO Status */ |
| 1928 | #define PIO_PSR_P22 (0x1u << 22) /**< \brief (PIO_PSR) PIO Status */ |
| 1929 | #define PIO_PSR_P23 (0x1u << 23) /**< \brief (PIO_PSR) PIO Status */ |
| 1930 | #define PIO_PSR_P24 (0x1u << 24) /**< \brief (PIO_PSR) PIO Status */ |
| 1931 | #define PIO_PSR_P25 (0x1u << 25) /**< \brief (PIO_PSR) PIO Status */ |
| 1932 | #define PIO_PSR_P26 (0x1u << 26) /**< \brief (PIO_PSR) PIO Status */ |
| 1933 | #define PIO_PSR_P27 (0x1u << 27) /**< \brief (PIO_PSR) PIO Status */ |
| 1934 | #define PIO_PSR_P28 (0x1u << 28) /**< \brief (PIO_PSR) PIO Status */ |
| 1935 | #define PIO_PSR_P29 (0x1u << 29) /**< \brief (PIO_PSR) PIO Status */ |
| 1936 | #define PIO_PSR_P30 (0x1u << 30) /**< \brief (PIO_PSR) PIO Status */ |
| 1937 | #define PIO_PSR_P31 (0x1u << 31) /**< \brief (PIO_PSR) PIO Status */ |
| 1938 | /* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */ |
| 1939 | #define PIO_OER_P0 (0x1u << 0) /**< \brief (PIO_OER) Output Enable */ |
| 1940 | #define PIO_OER_P1 (0x1u << 1) /**< \brief (PIO_OER) Output Enable */ |
| 1941 | #define PIO_OER_P2 (0x1u << 2) /**< \brief (PIO_OER) Output Enable */ |
| 1942 | #define PIO_OER_P3 (0x1u << 3) /**< \brief (PIO_OER) Output Enable */ |
| 1943 | #define PIO_OER_P4 (0x1u << 4) /**< \brief (PIO_OER) Output Enable */ |
| 1944 | #define PIO_OER_P5 (0x1u << 5) /**< \brief (PIO_OER) Output Enable */ |
| 1945 | #define PIO_OER_P6 (0x1u << 6) /**< \brief (PIO_OER) Output Enable */ |
| 1946 | #define PIO_OER_P7 (0x1u << 7) /**< \brief (PIO_OER) Output Enable */ |
| 1947 | #define PIO_OER_P8 (0x1u << 8) /**< \brief (PIO_OER) Output Enable */ |
| 1948 | #define PIO_OER_P9 (0x1u << 9) /**< \brief (PIO_OER) Output Enable */ |
| 1949 | #define PIO_OER_P10 (0x1u << 10) /**< \brief (PIO_OER) Output Enable */ |
| 1950 | #define PIO_OER_P11 (0x1u << 11) /**< \brief (PIO_OER) Output Enable */ |
| 1951 | #define PIO_OER_P12 (0x1u << 12) /**< \brief (PIO_OER) Output Enable */ |
| 1952 | #define PIO_OER_P13 (0x1u << 13) /**< \brief (PIO_OER) Output Enable */ |
| 1953 | #define PIO_OER_P14 (0x1u << 14) /**< \brief (PIO_OER) Output Enable */ |
| 1954 | #define PIO_OER_P15 (0x1u << 15) /**< \brief (PIO_OER) Output Enable */ |
| 1955 | #define PIO_OER_P16 (0x1u << 16) /**< \brief (PIO_OER) Output Enable */ |
| 1956 | #define PIO_OER_P17 (0x1u << 17) /**< \brief (PIO_OER) Output Enable */ |
| 1957 | #define PIO_OER_P18 (0x1u << 18) /**< \brief (PIO_OER) Output Enable */ |
| 1958 | #define PIO_OER_P19 (0x1u << 19) /**< \brief (PIO_OER) Output Enable */ |
| 1959 | #define PIO_OER_P20 (0x1u << 20) /**< \brief (PIO_OER) Output Enable */ |
| 1960 | #define PIO_OER_P21 (0x1u << 21) /**< \brief (PIO_OER) Output Enable */ |
| 1961 | #define PIO_OER_P22 (0x1u << 22) /**< \brief (PIO_OER) Output Enable */ |
| 1962 | #define PIO_OER_P23 (0x1u << 23) /**< \brief (PIO_OER) Output Enable */ |
| 1963 | #define PIO_OER_P24 (0x1u << 24) /**< \brief (PIO_OER) Output Enable */ |
| 1964 | #define PIO_OER_P25 (0x1u << 25) /**< \brief (PIO_OER) Output Enable */ |
| 1965 | #define PIO_OER_P26 (0x1u << 26) /**< \brief (PIO_OER) Output Enable */ |
| 1966 | #define PIO_OER_P27 (0x1u << 27) /**< \brief (PIO_OER) Output Enable */ |
| 1967 | #define PIO_OER_P28 (0x1u << 28) /**< \brief (PIO_OER) Output Enable */ |
| 1968 | #define PIO_OER_P29 (0x1u << 29) /**< \brief (PIO_OER) Output Enable */ |
| 1969 | #define PIO_OER_P30 (0x1u << 30) /**< \brief (PIO_OER) Output Enable */ |
| 1970 | #define PIO_OER_P31 (0x1u << 31) /**< \brief (PIO_OER) Output Enable */ |
| 1971 | /* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */ |
| 1972 | #define PIO_ODR_P0 (0x1u << 0) /**< \brief (PIO_ODR) Output Disable */ |
| 1973 | #define PIO_ODR_P1 (0x1u << 1) /**< \brief (PIO_ODR) Output Disable */ |
| 1974 | #define PIO_ODR_P2 (0x1u << 2) /**< \brief (PIO_ODR) Output Disable */ |
| 1975 | #define PIO_ODR_P3 (0x1u << 3) /**< \brief (PIO_ODR) Output Disable */ |
| 1976 | #define PIO_ODR_P4 (0x1u << 4) /**< \brief (PIO_ODR) Output Disable */ |
| 1977 | #define PIO_ODR_P5 (0x1u << 5) /**< \brief (PIO_ODR) Output Disable */ |
| 1978 | #define PIO_ODR_P6 (0x1u << 6) /**< \brief (PIO_ODR) Output Disable */ |
| 1979 | #define PIO_ODR_P7 (0x1u << 7) /**< \brief (PIO_ODR) Output Disable */ |
| 1980 | #define PIO_ODR_P8 (0x1u << 8) /**< \brief (PIO_ODR) Output Disable */ |
| 1981 | #define PIO_ODR_P9 (0x1u << 9) /**< \brief (PIO_ODR) Output Disable */ |
| 1982 | #define PIO_ODR_P10 (0x1u << 10) /**< \brief (PIO_ODR) Output Disable */ |
| 1983 | #define PIO_ODR_P11 (0x1u << 11) /**< \brief (PIO_ODR) Output Disable */ |
| 1984 | #define PIO_ODR_P12 (0x1u << 12) /**< \brief (PIO_ODR) Output Disable */ |
| 1985 | #define PIO_ODR_P13 (0x1u << 13) /**< \brief (PIO_ODR) Output Disable */ |
| 1986 | #define PIO_ODR_P14 (0x1u << 14) /**< \brief (PIO_ODR) Output Disable */ |
| 1987 | #define PIO_ODR_P15 (0x1u << 15) /**< \brief (PIO_ODR) Output Disable */ |
| 1988 | #define PIO_ODR_P16 (0x1u << 16) /**< \brief (PIO_ODR) Output Disable */ |
| 1989 | #define PIO_ODR_P17 (0x1u << 17) /**< \brief (PIO_ODR) Output Disable */ |
| 1990 | #define PIO_ODR_P18 (0x1u << 18) /**< \brief (PIO_ODR) Output Disable */ |
| 1991 | #define PIO_ODR_P19 (0x1u << 19) /**< \brief (PIO_ODR) Output Disable */ |
| 1992 | #define PIO_ODR_P20 (0x1u << 20) /**< \brief (PIO_ODR) Output Disable */ |
| 1993 | #define PIO_ODR_P21 (0x1u << 21) /**< \brief (PIO_ODR) Output Disable */ |
| 1994 | #define PIO_ODR_P22 (0x1u << 22) /**< \brief (PIO_ODR) Output Disable */ |
| 1995 | #define PIO_ODR_P23 (0x1u << 23) /**< \brief (PIO_ODR) Output Disable */ |
| 1996 | #define PIO_ODR_P24 (0x1u << 24) /**< \brief (PIO_ODR) Output Disable */ |
| 1997 | #define PIO_ODR_P25 (0x1u << 25) /**< \brief (PIO_ODR) Output Disable */ |
| 1998 | #define PIO_ODR_P26 (0x1u << 26) /**< \brief (PIO_ODR) Output Disable */ |
| 1999 | #define PIO_ODR_P27 (0x1u << 27) /**< \brief (PIO_ODR) Output Disable */ |
| 2000 | #define PIO_ODR_P28 (0x1u << 28) /**< \brief (PIO_ODR) Output Disable */ |
| 2001 | #define PIO_ODR_P29 (0x1u << 29) /**< \brief (PIO_ODR) Output Disable */ |
| 2002 | #define PIO_ODR_P30 (0x1u << 30) /**< \brief (PIO_ODR) Output Disable */ |
| 2003 | #define PIO_ODR_P31 (0x1u << 31) /**< \brief (PIO_ODR) Output Disable */ |
| 2004 | /* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */ |
| 2005 | #define PIO_OSR_P0 (0x1u << 0) /**< \brief (PIO_OSR) Output Status */ |
| 2006 | #define PIO_OSR_P1 (0x1u << 1) /**< \brief (PIO_OSR) Output Status */ |
| 2007 | #define PIO_OSR_P2 (0x1u << 2) /**< \brief (PIO_OSR) Output Status */ |
| 2008 | #define PIO_OSR_P3 (0x1u << 3) /**< \brief (PIO_OSR) Output Status */ |
| 2009 | #define PIO_OSR_P4 (0x1u << 4) /**< \brief (PIO_OSR) Output Status */ |
| 2010 | #define PIO_OSR_P5 (0x1u << 5) /**< \brief (PIO_OSR) Output Status */ |
| 2011 | #define PIO_OSR_P6 (0x1u << 6) /**< \brief (PIO_OSR) Output Status */ |
| 2012 | #define PIO_OSR_P7 (0x1u << 7) /**< \brief (PIO_OSR) Output Status */ |
| 2013 | #define PIO_OSR_P8 (0x1u << 8) /**< \brief (PIO_OSR) Output Status */ |
| 2014 | #define PIO_OSR_P9 (0x1u << 9) /**< \brief (PIO_OSR) Output Status */ |
| 2015 | #define PIO_OSR_P10 (0x1u << 10) /**< \brief (PIO_OSR) Output Status */ |
| 2016 | #define PIO_OSR_P11 (0x1u << 11) /**< \brief (PIO_OSR) Output Status */ |
| 2017 | #define PIO_OSR_P12 (0x1u << 12) /**< \brief (PIO_OSR) Output Status */ |
| 2018 | #define PIO_OSR_P13 (0x1u << 13) /**< \brief (PIO_OSR) Output Status */ |
| 2019 | #define PIO_OSR_P14 (0x1u << 14) /**< \brief (PIO_OSR) Output Status */ |
| 2020 | #define PIO_OSR_P15 (0x1u << 15) /**< \brief (PIO_OSR) Output Status */ |
| 2021 | #define PIO_OSR_P16 (0x1u << 16) /**< \brief (PIO_OSR) Output Status */ |
| 2022 | #define PIO_OSR_P17 (0x1u << 17) /**< \brief (PIO_OSR) Output Status */ |
| 2023 | #define PIO_OSR_P18 (0x1u << 18) /**< \brief (PIO_OSR) Output Status */ |
| 2024 | #define PIO_OSR_P19 (0x1u << 19) /**< \brief (PIO_OSR) Output Status */ |
| 2025 | #define PIO_OSR_P20 (0x1u << 20) /**< \brief (PIO_OSR) Output Status */ |
| 2026 | #define PIO_OSR_P21 (0x1u << 21) /**< \brief (PIO_OSR) Output Status */ |
| 2027 | #define PIO_OSR_P22 (0x1u << 22) /**< \brief (PIO_OSR) Output Status */ |
| 2028 | #define PIO_OSR_P23 (0x1u << 23) /**< \brief (PIO_OSR) Output Status */ |
| 2029 | #define PIO_OSR_P24 (0x1u << 24) /**< \brief (PIO_OSR) Output Status */ |
| 2030 | #define PIO_OSR_P25 (0x1u << 25) /**< \brief (PIO_OSR) Output Status */ |
| 2031 | #define PIO_OSR_P26 (0x1u << 26) /**< \brief (PIO_OSR) Output Status */ |
| 2032 | #define PIO_OSR_P27 (0x1u << 27) /**< \brief (PIO_OSR) Output Status */ |
| 2033 | #define PIO_OSR_P28 (0x1u << 28) /**< \brief (PIO_OSR) Output Status */ |
| 2034 | #define PIO_OSR_P29 (0x1u << 29) /**< \brief (PIO_OSR) Output Status */ |
| 2035 | #define PIO_OSR_P30 (0x1u << 30) /**< \brief (PIO_OSR) Output Status */ |
| 2036 | #define PIO_OSR_P31 (0x1u << 31) /**< \brief (PIO_OSR) Output Status */ |
| 2037 | /* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */ |
| 2038 | #define PIO_IFER_P0 (0x1u << 0) /**< \brief (PIO_IFER) Input Filter Enable */ |
| 2039 | #define PIO_IFER_P1 (0x1u << 1) /**< \brief (PIO_IFER) Input Filter Enable */ |
| 2040 | #define PIO_IFER_P2 (0x1u << 2) /**< \brief (PIO_IFER) Input Filter Enable */ |
| 2041 | #define PIO_IFER_P3 (0x1u << 3) /**< \brief (PIO_IFER) Input Filter Enable */ |
| 2042 | #define PIO_IFER_P4 (0x1u << 4) /**< \brief (PIO_IFER) Input Filter Enable */ |
| 2043 | #define PIO_IFER_P5 (0x1u << 5) /**< \brief (PIO_IFER) Input Filter Enable */ |
| 2044 | #define PIO_IFER_P6 (0x1u << 6) /**< \brief (PIO_IFER) Input Filter Enable */ |
| 2045 | #define PIO_IFER_P7 (0x1u << 7) /**< \brief (PIO_IFER) Input Filter Enable */ |
| 2046 | #define PIO_IFER_P8 (0x1u << 8) /**< \brief (PIO_IFER) Input Filter Enable */ |
| 2047 | #define PIO_IFER_P9 (0x1u << 9) /**< \brief (PIO_IFER) Input Filter Enable */ |
| 2048 | #define PIO_IFER_P10 (0x1u << 10) /**< \brief (PIO_IFER) Input Filter Enable */ |
| 2049 | #define PIO_IFER_P11 (0x1u << 11) /**< \brief (PIO_IFER) Input Filter Enable */ |
| 2050 | #define PIO_IFER_P12 (0x1u << 12) /**< \brief (PIO_IFER) Input Filter Enable */ |
| 2051 | #define PIO_IFER_P13 (0x1u << 13) /**< \brief (PIO_IFER) Input Filter Enable */ |
| 2052 | #define PIO_IFER_P14 (0x1u << 14) /**< \brief (PIO_IFER) Input Filter Enable */ |
| 2053 | #define PIO_IFER_P15 (0x1u << 15) /**< \brief (PIO_IFER) Input Filter Enable */ |
| 2054 | #define PIO_IFER_P16 (0x1u << 16) /**< \brief (PIO_IFER) Input Filter Enable */ |
| 2055 | #define PIO_IFER_P17 (0x1u << 17) /**< \brief (PIO_IFER) Input Filter Enable */ |
| 2056 | #define PIO_IFER_P18 (0x1u << 18) /**< \brief (PIO_IFER) Input Filter Enable */ |
| 2057 | #define PIO_IFER_P19 (0x1u << 19) /**< \brief (PIO_IFER) Input Filter Enable */ |
| 2058 | #define PIO_IFER_P20 (0x1u << 20) /**< \brief (PIO_IFER) Input Filter Enable */ |
| 2059 | #define PIO_IFER_P21 (0x1u << 21) /**< \brief (PIO_IFER) Input Filter Enable */ |
| 2060 | #define PIO_IFER_P22 (0x1u << 22) /**< \brief (PIO_IFER) Input Filter Enable */ |
| 2061 | #define PIO_IFER_P23 (0x1u << 23) /**< \brief (PIO_IFER) Input Filter Enable */ |
| 2062 | #define PIO_IFER_P24 (0x1u << 24) /**< \brief (PIO_IFER) Input Filter Enable */ |
| 2063 | #define PIO_IFER_P25 (0x1u << 25) /**< \brief (PIO_IFER) Input Filter Enable */ |
| 2064 | #define PIO_IFER_P26 (0x1u << 26) /**< \brief (PIO_IFER) Input Filter Enable */ |
| 2065 | #define PIO_IFER_P27 (0x1u << 27) /**< \brief (PIO_IFER) Input Filter Enable */ |
| 2066 | #define PIO_IFER_P28 (0x1u << 28) /**< \brief (PIO_IFER) Input Filter Enable */ |
| 2067 | #define PIO_IFER_P29 (0x1u << 29) /**< \brief (PIO_IFER) Input Filter Enable */ |
| 2068 | #define PIO_IFER_P30 (0x1u << 30) /**< \brief (PIO_IFER) Input Filter Enable */ |
| 2069 | #define PIO_IFER_P31 (0x1u << 31) /**< \brief (PIO_IFER) Input Filter Enable */ |
| 2070 | /* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */ |
| 2071 | #define PIO_IFDR_P0 (0x1u << 0) /**< \brief (PIO_IFDR) Input Filter Disable */ |
| 2072 | #define PIO_IFDR_P1 (0x1u << 1) /**< \brief (PIO_IFDR) Input Filter Disable */ |
| 2073 | #define PIO_IFDR_P2 (0x1u << 2) /**< \brief (PIO_IFDR) Input Filter Disable */ |
| 2074 | #define PIO_IFDR_P3 (0x1u << 3) /**< \brief (PIO_IFDR) Input Filter Disable */ |
| 2075 | #define PIO_IFDR_P4 (0x1u << 4) /**< \brief (PIO_IFDR) Input Filter Disable */ |
| 2076 | #define PIO_IFDR_P5 (0x1u << 5) /**< \brief (PIO_IFDR) Input Filter Disable */ |
| 2077 | #define PIO_IFDR_P6 (0x1u << 6) /**< \brief (PIO_IFDR) Input Filter Disable */ |
| 2078 | #define PIO_IFDR_P7 (0x1u << 7) /**< \brief (PIO_IFDR) Input Filter Disable */ |
| 2079 | #define PIO_IFDR_P8 (0x1u << 8) /**< \brief (PIO_IFDR) Input Filter Disable */ |
| 2080 | #define PIO_IFDR_P9 (0x1u << 9) /**< \brief (PIO_IFDR) Input Filter Disable */ |
| 2081 | #define PIO_IFDR_P10 (0x1u << 10) /**< \brief (PIO_IFDR) Input Filter Disable */ |
| 2082 | #define PIO_IFDR_P11 (0x1u << 11) /**< \brief (PIO_IFDR) Input Filter Disable */ |
| 2083 | #define PIO_IFDR_P12 (0x1u << 12) /**< \brief (PIO_IFDR) Input Filter Disable */ |
| 2084 | #define PIO_IFDR_P13 (0x1u << 13) /**< \brief (PIO_IFDR) Input Filter Disable */ |
| 2085 | #define PIO_IFDR_P14 (0x1u << 14) /**< \brief (PIO_IFDR) Input Filter Disable */ |
| 2086 | #define PIO_IFDR_P15 (0x1u << 15) /**< \brief (PIO_IFDR) Input Filter Disable */ |
| 2087 | #define PIO_IFDR_P16 (0x1u << 16) /**< \brief (PIO_IFDR) Input Filter Disable */ |
| 2088 | #define PIO_IFDR_P17 (0x1u << 17) /**< \brief (PIO_IFDR) Input Filter Disable */ |
| 2089 | #define PIO_IFDR_P18 (0x1u << 18) /**< \brief (PIO_IFDR) Input Filter Disable */ |
| 2090 | #define PIO_IFDR_P19 (0x1u << 19) /**< \brief (PIO_IFDR) Input Filter Disable */ |
| 2091 | #define PIO_IFDR_P20 (0x1u << 20) /**< \brief (PIO_IFDR) Input Filter Disable */ |
| 2092 | #define PIO_IFDR_P21 (0x1u << 21) /**< \brief (PIO_IFDR) Input Filter Disable */ |
| 2093 | #define PIO_IFDR_P22 (0x1u << 22) /**< \brief (PIO_IFDR) Input Filter Disable */ |
| 2094 | #define PIO_IFDR_P23 (0x1u << 23) /**< \brief (PIO_IFDR) Input Filter Disable */ |
| 2095 | #define PIO_IFDR_P24 (0x1u << 24) /**< \brief (PIO_IFDR) Input Filter Disable */ |
| 2096 | #define PIO_IFDR_P25 (0x1u << 25) /**< \brief (PIO_IFDR) Input Filter Disable */ |
| 2097 | #define PIO_IFDR_P26 (0x1u << 26) /**< \brief (PIO_IFDR) Input Filter Disable */ |
| 2098 | #define PIO_IFDR_P27 (0x1u << 27) /**< \brief (PIO_IFDR) Input Filter Disable */ |
| 2099 | #define PIO_IFDR_P28 (0x1u << 28) /**< \brief (PIO_IFDR) Input Filter Disable */ |
| 2100 | #define PIO_IFDR_P29 (0x1u << 29) /**< \brief (PIO_IFDR) Input Filter Disable */ |
| 2101 | #define PIO_IFDR_P30 (0x1u << 30) /**< \brief (PIO_IFDR) Input Filter Disable */ |
| 2102 | #define PIO_IFDR_P31 (0x1u << 31) /**< \brief (PIO_IFDR) Input Filter Disable */ |
| 2103 | /* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */ |
| 2104 | #define PIO_IFSR_P0 (0x1u << 0) /**< \brief (PIO_IFSR) Input Filer Status */ |
| 2105 | #define PIO_IFSR_P1 (0x1u << 1) /**< \brief (PIO_IFSR) Input Filer Status */ |
| 2106 | #define PIO_IFSR_P2 (0x1u << 2) /**< \brief (PIO_IFSR) Input Filer Status */ |
| 2107 | #define PIO_IFSR_P3 (0x1u << 3) /**< \brief (PIO_IFSR) Input Filer Status */ |
| 2108 | #define PIO_IFSR_P4 (0x1u << 4) /**< \brief (PIO_IFSR) Input Filer Status */ |
| 2109 | #define PIO_IFSR_P5 (0x1u << 5) /**< \brief (PIO_IFSR) Input Filer Status */ |
| 2110 | #define PIO_IFSR_P6 (0x1u << 6) /**< \brief (PIO_IFSR) Input Filer Status */ |
| 2111 | #define PIO_IFSR_P7 (0x1u << 7) /**< \brief (PIO_IFSR) Input Filer Status */ |
| 2112 | #define PIO_IFSR_P8 (0x1u << 8) /**< \brief (PIO_IFSR) Input Filer Status */ |
| 2113 | #define PIO_IFSR_P9 (0x1u << 9) /**< \brief (PIO_IFSR) Input Filer Status */ |
| 2114 | #define PIO_IFSR_P10 (0x1u << 10) /**< \brief (PIO_IFSR) Input Filer Status */ |
| 2115 | #define PIO_IFSR_P11 (0x1u << 11) /**< \brief (PIO_IFSR) Input Filer Status */ |
| 2116 | #define PIO_IFSR_P12 (0x1u << 12) /**< \brief (PIO_IFSR) Input Filer Status */ |
| 2117 | #define PIO_IFSR_P13 (0x1u << 13) /**< \brief (PIO_IFSR) Input Filer Status */ |
| 2118 | #define PIO_IFSR_P14 (0x1u << 14) /**< \brief (PIO_IFSR) Input Filer Status */ |
| 2119 | #define PIO_IFSR_P15 (0x1u << 15) /**< \brief (PIO_IFSR) Input Filer Status */ |
| 2120 | #define PIO_IFSR_P16 (0x1u << 16) /**< \brief (PIO_IFSR) Input Filer Status */ |
| 2121 | #define PIO_IFSR_P17 (0x1u << 17) /**< \brief (PIO_IFSR) Input Filer Status */ |
| 2122 | #define PIO_IFSR_P18 (0x1u << 18) /**< \brief (PIO_IFSR) Input Filer Status */ |
| 2123 | #define PIO_IFSR_P19 (0x1u << 19) /**< \brief (PIO_IFSR) Input Filer Status */ |
| 2124 | #define PIO_IFSR_P20 (0x1u << 20) /**< \brief (PIO_IFSR) Input Filer Status */ |
| 2125 | #define PIO_IFSR_P21 (0x1u << 21) /**< \brief (PIO_IFSR) Input Filer Status */ |
| 2126 | #define PIO_IFSR_P22 (0x1u << 22) /**< \brief (PIO_IFSR) Input Filer Status */ |
| 2127 | #define PIO_IFSR_P23 (0x1u << 23) /**< \brief (PIO_IFSR) Input Filer Status */ |
| 2128 | #define PIO_IFSR_P24 (0x1u << 24) /**< \brief (PIO_IFSR) Input Filer Status */ |
| 2129 | #define PIO_IFSR_P25 (0x1u << 25) /**< \brief (PIO_IFSR) Input Filer Status */ |
| 2130 | #define PIO_IFSR_P26 (0x1u << 26) /**< \brief (PIO_IFSR) Input Filer Status */ |
| 2131 | #define PIO_IFSR_P27 (0x1u << 27) /**< \brief (PIO_IFSR) Input Filer Status */ |
| 2132 | #define PIO_IFSR_P28 (0x1u << 28) /**< \brief (PIO_IFSR) Input Filer Status */ |
| 2133 | #define PIO_IFSR_P29 (0x1u << 29) /**< \brief (PIO_IFSR) Input Filer Status */ |
| 2134 | #define PIO_IFSR_P30 (0x1u << 30) /**< \brief (PIO_IFSR) Input Filer Status */ |
| 2135 | #define PIO_IFSR_P31 (0x1u << 31) /**< \brief (PIO_IFSR) Input Filer Status */ |
| 2136 | /* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */ |
| 2137 | #define PIO_SODR_P0 (0x1u << 0) /**< \brief (PIO_SODR) Set Output Data */ |
| 2138 | #define PIO_SODR_P1 (0x1u << 1) /**< \brief (PIO_SODR) Set Output Data */ |
| 2139 | #define PIO_SODR_P2 (0x1u << 2) /**< \brief (PIO_SODR) Set Output Data */ |
| 2140 | #define PIO_SODR_P3 (0x1u << 3) /**< \brief (PIO_SODR) Set Output Data */ |
| 2141 | #define PIO_SODR_P4 (0x1u << 4) /**< \brief (PIO_SODR) Set Output Data */ |
| 2142 | #define PIO_SODR_P5 (0x1u << 5) /**< \brief (PIO_SODR) Set Output Data */ |
| 2143 | #define PIO_SODR_P6 (0x1u << 6) /**< \brief (PIO_SODR) Set Output Data */ |
| 2144 | #define PIO_SODR_P7 (0x1u << 7) /**< \brief (PIO_SODR) Set Output Data */ |
| 2145 | #define PIO_SODR_P8 (0x1u << 8) /**< \brief (PIO_SODR) Set Output Data */ |
| 2146 | #define PIO_SODR_P9 (0x1u << 9) /**< \brief (PIO_SODR) Set Output Data */ |
| 2147 | #define PIO_SODR_P10 (0x1u << 10) /**< \brief (PIO_SODR) Set Output Data */ |
| 2148 | #define PIO_SODR_P11 (0x1u << 11) /**< \brief (PIO_SODR) Set Output Data */ |
| 2149 | #define PIO_SODR_P12 (0x1u << 12) /**< \brief (PIO_SODR) Set Output Data */ |
| 2150 | #define PIO_SODR_P13 (0x1u << 13) /**< \brief (PIO_SODR) Set Output Data */ |
| 2151 | #define PIO_SODR_P14 (0x1u << 14) /**< \brief (PIO_SODR) Set Output Data */ |
| 2152 | #define PIO_SODR_P15 (0x1u << 15) /**< \brief (PIO_SODR) Set Output Data */ |
| 2153 | #define PIO_SODR_P16 (0x1u << 16) /**< \brief (PIO_SODR) Set Output Data */ |
| 2154 | #define PIO_SODR_P17 (0x1u << 17) /**< \brief (PIO_SODR) Set Output Data */ |
| 2155 | #define PIO_SODR_P18 (0x1u << 18) /**< \brief (PIO_SODR) Set Output Data */ |
| 2156 | #define PIO_SODR_P19 (0x1u << 19) /**< \brief (PIO_SODR) Set Output Data */ |
| 2157 | #define PIO_SODR_P20 (0x1u << 20) /**< \brief (PIO_SODR) Set Output Data */ |
| 2158 | #define PIO_SODR_P21 (0x1u << 21) /**< \brief (PIO_SODR) Set Output Data */ |
| 2159 | #define PIO_SODR_P22 (0x1u << 22) /**< \brief (PIO_SODR) Set Output Data */ |
| 2160 | #define PIO_SODR_P23 (0x1u << 23) /**< \brief (PIO_SODR) Set Output Data */ |
| 2161 | #define PIO_SODR_P24 (0x1u << 24) /**< \brief (PIO_SODR) Set Output Data */ |
| 2162 | #define PIO_SODR_P25 (0x1u << 25) /**< \brief (PIO_SODR) Set Output Data */ |
| 2163 | #define PIO_SODR_P26 (0x1u << 26) /**< \brief (PIO_SODR) Set Output Data */ |
| 2164 | #define PIO_SODR_P27 (0x1u << 27) /**< \brief (PIO_SODR) Set Output Data */ |
| 2165 | #define PIO_SODR_P28 (0x1u << 28) /**< \brief (PIO_SODR) Set Output Data */ |
| 2166 | #define PIO_SODR_P29 (0x1u << 29) /**< \brief (PIO_SODR) Set Output Data */ |
| 2167 | #define PIO_SODR_P30 (0x1u << 30) /**< \brief (PIO_SODR) Set Output Data */ |
| 2168 | #define PIO_SODR_P31 (0x1u << 31) /**< \brief (PIO_SODR) Set Output Data */ |
| 2169 | /* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */ |
| 2170 | #define PIO_CODR_P0 (0x1u << 0) /**< \brief (PIO_CODR) Clear Output Data */ |
| 2171 | #define PIO_CODR_P1 (0x1u << 1) /**< \brief (PIO_CODR) Clear Output Data */ |
| 2172 | #define PIO_CODR_P2 (0x1u << 2) /**< \brief (PIO_CODR) Clear Output Data */ |
| 2173 | #define PIO_CODR_P3 (0x1u << 3) /**< \brief (PIO_CODR) Clear Output Data */ |
| 2174 | #define PIO_CODR_P4 (0x1u << 4) /**< \brief (PIO_CODR) Clear Output Data */ |
| 2175 | #define PIO_CODR_P5 (0x1u << 5) /**< \brief (PIO_CODR) Clear Output Data */ |
| 2176 | #define PIO_CODR_P6 (0x1u << 6) /**< \brief (PIO_CODR) Clear Output Data */ |
| 2177 | #define PIO_CODR_P7 (0x1u << 7) /**< \brief (PIO_CODR) Clear Output Data */ |
| 2178 | #define PIO_CODR_P8 (0x1u << 8) /**< \brief (PIO_CODR) Clear Output Data */ |
| 2179 | #define PIO_CODR_P9 (0x1u << 9) /**< \brief (PIO_CODR) Clear Output Data */ |
| 2180 | #define PIO_CODR_P10 (0x1u << 10) /**< \brief (PIO_CODR) Clear Output Data */ |
| 2181 | #define PIO_CODR_P11 (0x1u << 11) /**< \brief (PIO_CODR) Clear Output Data */ |
| 2182 | #define PIO_CODR_P12 (0x1u << 12) /**< \brief (PIO_CODR) Clear Output Data */ |
| 2183 | #define PIO_CODR_P13 (0x1u << 13) /**< \brief (PIO_CODR) Clear Output Data */ |
| 2184 | #define PIO_CODR_P14 (0x1u << 14) /**< \brief (PIO_CODR) Clear Output Data */ |
| 2185 | #define PIO_CODR_P15 (0x1u << 15) /**< \brief (PIO_CODR) Clear Output Data */ |
| 2186 | #define PIO_CODR_P16 (0x1u << 16) /**< \brief (PIO_CODR) Clear Output Data */ |
| 2187 | #define PIO_CODR_P17 (0x1u << 17) /**< \brief (PIO_CODR) Clear Output Data */ |
| 2188 | #define PIO_CODR_P18 (0x1u << 18) /**< \brief (PIO_CODR) Clear Output Data */ |
| 2189 | #define PIO_CODR_P19 (0x1u << 19) /**< \brief (PIO_CODR) Clear Output Data */ |
| 2190 | #define PIO_CODR_P20 (0x1u << 20) /**< \brief (PIO_CODR) Clear Output Data */ |
| 2191 | #define PIO_CODR_P21 (0x1u << 21) /**< \brief (PIO_CODR) Clear Output Data */ |
| 2192 | #define PIO_CODR_P22 (0x1u << 22) /**< \brief (PIO_CODR) Clear Output Data */ |
| 2193 | #define PIO_CODR_P23 (0x1u << 23) /**< \brief (PIO_CODR) Clear Output Data */ |
| 2194 | #define PIO_CODR_P24 (0x1u << 24) /**< \brief (PIO_CODR) Clear Output Data */ |
| 2195 | #define PIO_CODR_P25 (0x1u << 25) /**< \brief (PIO_CODR) Clear Output Data */ |
| 2196 | #define PIO_CODR_P26 (0x1u << 26) /**< \brief (PIO_CODR) Clear Output Data */ |
| 2197 | #define PIO_CODR_P27 (0x1u << 27) /**< \brief (PIO_CODR) Clear Output Data */ |
| 2198 | #define PIO_CODR_P28 (0x1u << 28) /**< \brief (PIO_CODR) Clear Output Data */ |
| 2199 | #define PIO_CODR_P29 (0x1u << 29) /**< \brief (PIO_CODR) Clear Output Data */ |
| 2200 | #define PIO_CODR_P30 (0x1u << 30) /**< \brief (PIO_CODR) Clear Output Data */ |
| 2201 | #define PIO_CODR_P31 (0x1u << 31) /**< \brief (PIO_CODR) Clear Output Data */ |
| 2202 | /* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */ |
| 2203 | #define PIO_ODSR_P0 (0x1u << 0) /**< \brief (PIO_ODSR) Output Data Status */ |
| 2204 | #define PIO_ODSR_P1 (0x1u << 1) /**< \brief (PIO_ODSR) Output Data Status */ |
| 2205 | #define PIO_ODSR_P2 (0x1u << 2) /**< \brief (PIO_ODSR) Output Data Status */ |
| 2206 | #define PIO_ODSR_P3 (0x1u << 3) /**< \brief (PIO_ODSR) Output Data Status */ |
| 2207 | #define PIO_ODSR_P4 (0x1u << 4) /**< \brief (PIO_ODSR) Output Data Status */ |
| 2208 | #define PIO_ODSR_P5 (0x1u << 5) /**< \brief (PIO_ODSR) Output Data Status */ |
| 2209 | #define PIO_ODSR_P6 (0x1u << 6) /**< \brief (PIO_ODSR) Output Data Status */ |
| 2210 | #define PIO_ODSR_P7 (0x1u << 7) /**< \brief (PIO_ODSR) Output Data Status */ |
| 2211 | #define PIO_ODSR_P8 (0x1u << 8) /**< \brief (PIO_ODSR) Output Data Status */ |
| 2212 | #define PIO_ODSR_P9 (0x1u << 9) /**< \brief (PIO_ODSR) Output Data Status */ |
| 2213 | #define PIO_ODSR_P10 (0x1u << 10) /**< \brief (PIO_ODSR) Output Data Status */ |
| 2214 | #define PIO_ODSR_P11 (0x1u << 11) /**< \brief (PIO_ODSR) Output Data Status */ |
| 2215 | #define PIO_ODSR_P12 (0x1u << 12) /**< \brief (PIO_ODSR) Output Data Status */ |
| 2216 | #define PIO_ODSR_P13 (0x1u << 13) /**< \brief (PIO_ODSR) Output Data Status */ |
| 2217 | #define PIO_ODSR_P14 (0x1u << 14) /**< \brief (PIO_ODSR) Output Data Status */ |
| 2218 | #define PIO_ODSR_P15 (0x1u << 15) /**< \brief (PIO_ODSR) Output Data Status */ |
| 2219 | #define PIO_ODSR_P16 (0x1u << 16) /**< \brief (PIO_ODSR) Output Data Status */ |
| 2220 | #define PIO_ODSR_P17 (0x1u << 17) /**< \brief (PIO_ODSR) Output Data Status */ |
| 2221 | #define PIO_ODSR_P18 (0x1u << 18) /**< \brief (PIO_ODSR) Output Data Status */ |
| 2222 | #define PIO_ODSR_P19 (0x1u << 19) /**< \brief (PIO_ODSR) Output Data Status */ |
| 2223 | #define PIO_ODSR_P20 (0x1u << 20) /**< \brief (PIO_ODSR) Output Data Status */ |
| 2224 | #define PIO_ODSR_P21 (0x1u << 21) /**< \brief (PIO_ODSR) Output Data Status */ |
| 2225 | #define PIO_ODSR_P22 (0x1u << 22) /**< \brief (PIO_ODSR) Output Data Status */ |
| 2226 | #define PIO_ODSR_P23 (0x1u << 23) /**< \brief (PIO_ODSR) Output Data Status */ |
| 2227 | #define PIO_ODSR_P24 (0x1u << 24) /**< \brief (PIO_ODSR) Output Data Status */ |
| 2228 | #define PIO_ODSR_P25 (0x1u << 25) /**< \brief (PIO_ODSR) Output Data Status */ |
| 2229 | #define PIO_ODSR_P26 (0x1u << 26) /**< \brief (PIO_ODSR) Output Data Status */ |
| 2230 | #define PIO_ODSR_P27 (0x1u << 27) /**< \brief (PIO_ODSR) Output Data Status */ |
| 2231 | #define PIO_ODSR_P28 (0x1u << 28) /**< \brief (PIO_ODSR) Output Data Status */ |
| 2232 | #define PIO_ODSR_P29 (0x1u << 29) /**< \brief (PIO_ODSR) Output Data Status */ |
| 2233 | #define PIO_ODSR_P30 (0x1u << 30) /**< \brief (PIO_ODSR) Output Data Status */ |
| 2234 | #define PIO_ODSR_P31 (0x1u << 31) /**< \brief (PIO_ODSR) Output Data Status */ |
| 2235 | /* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */ |
| 2236 | #define PIO_PDSR_P0 (0x1u << 0) /**< \brief (PIO_PDSR) Output Data Status */ |
| 2237 | #define PIO_PDSR_P1 (0x1u << 1) /**< \brief (PIO_PDSR) Output Data Status */ |
| 2238 | #define PIO_PDSR_P2 (0x1u << 2) /**< \brief (PIO_PDSR) Output Data Status */ |
| 2239 | #define PIO_PDSR_P3 (0x1u << 3) /**< \brief (PIO_PDSR) Output Data Status */ |
| 2240 | #define PIO_PDSR_P4 (0x1u << 4) /**< \brief (PIO_PDSR) Output Data Status */ |
| 2241 | #define PIO_PDSR_P5 (0x1u << 5) /**< \brief (PIO_PDSR) Output Data Status */ |
| 2242 | #define PIO_PDSR_P6 (0x1u << 6) /**< \brief (PIO_PDSR) Output Data Status */ |
| 2243 | #define PIO_PDSR_P7 (0x1u << 7) /**< \brief (PIO_PDSR) Output Data Status */ |
| 2244 | #define PIO_PDSR_P8 (0x1u << 8) /**< \brief (PIO_PDSR) Output Data Status */ |
| 2245 | #define PIO_PDSR_P9 (0x1u << 9) /**< \brief (PIO_PDSR) Output Data Status */ |
| 2246 | #define PIO_PDSR_P10 (0x1u << 10) /**< \brief (PIO_PDSR) Output Data Status */ |
| 2247 | #define PIO_PDSR_P11 (0x1u << 11) /**< \brief (PIO_PDSR) Output Data Status */ |
| 2248 | #define PIO_PDSR_P12 (0x1u << 12) /**< \brief (PIO_PDSR) Output Data Status */ |
| 2249 | #define PIO_PDSR_P13 (0x1u << 13) /**< \brief (PIO_PDSR) Output Data Status */ |
| 2250 | #define PIO_PDSR_P14 (0x1u << 14) /**< \brief (PIO_PDSR) Output Data Status */ |
| 2251 | #define PIO_PDSR_P15 (0x1u << 15) /**< \brief (PIO_PDSR) Output Data Status */ |
| 2252 | #define PIO_PDSR_P16 (0x1u << 16) /**< \brief (PIO_PDSR) Output Data Status */ |
| 2253 | #define PIO_PDSR_P17 (0x1u << 17) /**< \brief (PIO_PDSR) Output Data Status */ |
| 2254 | #define PIO_PDSR_P18 (0x1u << 18) /**< \brief (PIO_PDSR) Output Data Status */ |
| 2255 | #define PIO_PDSR_P19 (0x1u << 19) /**< \brief (PIO_PDSR) Output Data Status */ |
| 2256 | #define PIO_PDSR_P20 (0x1u << 20) /**< \brief (PIO_PDSR) Output Data Status */ |
| 2257 | #define PIO_PDSR_P21 (0x1u << 21) /**< \brief (PIO_PDSR) Output Data Status */ |
| 2258 | #define PIO_PDSR_P22 (0x1u << 22) /**< \brief (PIO_PDSR) Output Data Status */ |
| 2259 | #define PIO_PDSR_P23 (0x1u << 23) /**< \brief (PIO_PDSR) Output Data Status */ |
| 2260 | #define PIO_PDSR_P24 (0x1u << 24) /**< \brief (PIO_PDSR) Output Data Status */ |
| 2261 | #define PIO_PDSR_P25 (0x1u << 25) /**< \brief (PIO_PDSR) Output Data Status */ |
| 2262 | #define PIO_PDSR_P26 (0x1u << 26) /**< \brief (PIO_PDSR) Output Data Status */ |
| 2263 | #define PIO_PDSR_P27 (0x1u << 27) /**< \brief (PIO_PDSR) Output Data Status */ |
| 2264 | #define PIO_PDSR_P28 (0x1u << 28) /**< \brief (PIO_PDSR) Output Data Status */ |
| 2265 | #define PIO_PDSR_P29 (0x1u << 29) /**< \brief (PIO_PDSR) Output Data Status */ |
| 2266 | #define PIO_PDSR_P30 (0x1u << 30) /**< \brief (PIO_PDSR) Output Data Status */ |
| 2267 | #define PIO_PDSR_P31 (0x1u << 31) /**< \brief (PIO_PDSR) Output Data Status */ |
| 2268 | /* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */ |
| 2269 | #define PIO_IER_P0 (0x1u << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
| 2270 | #define PIO_IER_P1 (0x1u << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
| 2271 | #define PIO_IER_P2 (0x1u << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
| 2272 | #define PIO_IER_P3 (0x1u << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
| 2273 | #define PIO_IER_P4 (0x1u << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
| 2274 | #define PIO_IER_P5 (0x1u << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
| 2275 | #define PIO_IER_P6 (0x1u << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
| 2276 | #define PIO_IER_P7 (0x1u << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
| 2277 | #define PIO_IER_P8 (0x1u << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
| 2278 | #define PIO_IER_P9 (0x1u << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
| 2279 | #define PIO_IER_P10 (0x1u << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
| 2280 | #define PIO_IER_P11 (0x1u << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
| 2281 | #define PIO_IER_P12 (0x1u << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
| 2282 | #define PIO_IER_P13 (0x1u << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
| 2283 | #define PIO_IER_P14 (0x1u << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
| 2284 | #define PIO_IER_P15 (0x1u << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
| 2285 | #define PIO_IER_P16 (0x1u << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
| 2286 | #define PIO_IER_P17 (0x1u << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
| 2287 | #define PIO_IER_P18 (0x1u << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
| 2288 | #define PIO_IER_P19 (0x1u << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
| 2289 | #define PIO_IER_P20 (0x1u << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
| 2290 | #define PIO_IER_P21 (0x1u << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
| 2291 | #define PIO_IER_P22 (0x1u << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
| 2292 | #define PIO_IER_P23 (0x1u << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
| 2293 | #define PIO_IER_P24 (0x1u << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
| 2294 | #define PIO_IER_P25 (0x1u << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
| 2295 | #define PIO_IER_P26 (0x1u << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
| 2296 | #define PIO_IER_P27 (0x1u << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
| 2297 | #define PIO_IER_P28 (0x1u << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
| 2298 | #define PIO_IER_P29 (0x1u << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
| 2299 | #define PIO_IER_P30 (0x1u << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
| 2300 | #define PIO_IER_P31 (0x1u << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
| 2301 | /* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */ |
| 2302 | #define PIO_IDR_P0 (0x1u << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
| 2303 | #define PIO_IDR_P1 (0x1u << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
| 2304 | #define PIO_IDR_P2 (0x1u << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
| 2305 | #define PIO_IDR_P3 (0x1u << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
| 2306 | #define PIO_IDR_P4 (0x1u << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
| 2307 | #define PIO_IDR_P5 (0x1u << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
| 2308 | #define PIO_IDR_P6 (0x1u << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
| 2309 | #define PIO_IDR_P7 (0x1u << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
| 2310 | #define PIO_IDR_P8 (0x1u << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
| 2311 | #define PIO_IDR_P9 (0x1u << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
| 2312 | #define PIO_IDR_P10 (0x1u << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
| 2313 | #define PIO_IDR_P11 (0x1u << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
| 2314 | #define PIO_IDR_P12 (0x1u << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
| 2315 | #define PIO_IDR_P13 (0x1u << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
| 2316 | #define PIO_IDR_P14 (0x1u << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
| 2317 | #define PIO_IDR_P15 (0x1u << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
| 2318 | #define PIO_IDR_P16 (0x1u << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
| 2319 | #define PIO_IDR_P17 (0x1u << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
| 2320 | #define PIO_IDR_P18 (0x1u << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
| 2321 | #define PIO_IDR_P19 (0x1u << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
| 2322 | #define PIO_IDR_P20 (0x1u << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
| 2323 | #define PIO_IDR_P21 (0x1u << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
| 2324 | #define PIO_IDR_P22 (0x1u << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
| 2325 | #define PIO_IDR_P23 (0x1u << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
| 2326 | #define PIO_IDR_P24 (0x1u << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
| 2327 | #define PIO_IDR_P25 (0x1u << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
| 2328 | #define PIO_IDR_P26 (0x1u << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
| 2329 | #define PIO_IDR_P27 (0x1u << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
| 2330 | #define PIO_IDR_P28 (0x1u << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
| 2331 | #define PIO_IDR_P29 (0x1u << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
| 2332 | #define PIO_IDR_P30 (0x1u << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
| 2333 | #define PIO_IDR_P31 (0x1u << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
| 2334 | /* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */ |
| 2335 | #define PIO_IMR_P0 (0x1u << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
| 2336 | #define PIO_IMR_P1 (0x1u << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
| 2337 | #define PIO_IMR_P2 (0x1u << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
| 2338 | #define PIO_IMR_P3 (0x1u << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
| 2339 | #define PIO_IMR_P4 (0x1u << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
| 2340 | #define PIO_IMR_P5 (0x1u << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
| 2341 | #define PIO_IMR_P6 (0x1u << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
| 2342 | #define PIO_IMR_P7 (0x1u << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
| 2343 | #define PIO_IMR_P8 (0x1u << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
| 2344 | #define PIO_IMR_P9 (0x1u << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
| 2345 | #define PIO_IMR_P10 (0x1u << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
| 2346 | #define PIO_IMR_P11 (0x1u << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
| 2347 | #define PIO_IMR_P12 (0x1u << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
| 2348 | #define PIO_IMR_P13 (0x1u << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
| 2349 | #define PIO_IMR_P14 (0x1u << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
| 2350 | #define PIO_IMR_P15 (0x1u << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
| 2351 | #define PIO_IMR_P16 (0x1u << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
| 2352 | #define PIO_IMR_P17 (0x1u << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
| 2353 | #define PIO_IMR_P18 (0x1u << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
| 2354 | #define PIO_IMR_P19 (0x1u << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
| 2355 | #define PIO_IMR_P20 (0x1u << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
| 2356 | #define PIO_IMR_P21 (0x1u << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
| 2357 | #define PIO_IMR_P22 (0x1u << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
| 2358 | #define PIO_IMR_P23 (0x1u << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
| 2359 | #define PIO_IMR_P24 (0x1u << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
| 2360 | #define PIO_IMR_P25 (0x1u << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
| 2361 | #define PIO_IMR_P26 (0x1u << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
| 2362 | #define PIO_IMR_P27 (0x1u << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
| 2363 | #define PIO_IMR_P28 (0x1u << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
| 2364 | #define PIO_IMR_P29 (0x1u << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
| 2365 | #define PIO_IMR_P30 (0x1u << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
| 2366 | #define PIO_IMR_P31 (0x1u << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
| 2367 | /* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */ |
| 2368 | #define PIO_ISR_P0 (0x1u << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
| 2369 | #define PIO_ISR_P1 (0x1u << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
| 2370 | #define PIO_ISR_P2 (0x1u << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
| 2371 | #define PIO_ISR_P3 (0x1u << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
| 2372 | #define PIO_ISR_P4 (0x1u << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
| 2373 | #define PIO_ISR_P5 (0x1u << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
| 2374 | #define PIO_ISR_P6 (0x1u << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
| 2375 | #define PIO_ISR_P7 (0x1u << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
| 2376 | #define PIO_ISR_P8 (0x1u << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
| 2377 | #define PIO_ISR_P9 (0x1u << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
| 2378 | #define PIO_ISR_P10 (0x1u << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
| 2379 | #define PIO_ISR_P11 (0x1u << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
| 2380 | #define PIO_ISR_P12 (0x1u << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
| 2381 | #define PIO_ISR_P13 (0x1u << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
| 2382 | #define PIO_ISR_P14 (0x1u << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
| 2383 | #define PIO_ISR_P15 (0x1u << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
| 2384 | #define PIO_ISR_P16 (0x1u << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
| 2385 | #define PIO_ISR_P17 (0x1u << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
| 2386 | #define PIO_ISR_P18 (0x1u << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
| 2387 | #define PIO_ISR_P19 (0x1u << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
| 2388 | #define PIO_ISR_P20 (0x1u << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
| 2389 | #define PIO_ISR_P21 (0x1u << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
| 2390 | #define PIO_ISR_P22 (0x1u << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
| 2391 | #define PIO_ISR_P23 (0x1u << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
| 2392 | #define PIO_ISR_P24 (0x1u << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
| 2393 | #define PIO_ISR_P25 (0x1u << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
| 2394 | #define PIO_ISR_P26 (0x1u << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
| 2395 | #define PIO_ISR_P27 (0x1u << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
| 2396 | #define PIO_ISR_P28 (0x1u << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
| 2397 | #define PIO_ISR_P29 (0x1u << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
| 2398 | #define PIO_ISR_P30 (0x1u << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
| 2399 | #define PIO_ISR_P31 (0x1u << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
| 2400 | /* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */ |
| 2401 | #define PIO_MDER_P0 (0x1u << 0) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
| 2402 | #define PIO_MDER_P1 (0x1u << 1) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
| 2403 | #define PIO_MDER_P2 (0x1u << 2) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
| 2404 | #define PIO_MDER_P3 (0x1u << 3) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
| 2405 | #define PIO_MDER_P4 (0x1u << 4) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
| 2406 | #define PIO_MDER_P5 (0x1u << 5) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
| 2407 | #define PIO_MDER_P6 (0x1u << 6) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
| 2408 | #define PIO_MDER_P7 (0x1u << 7) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
| 2409 | #define PIO_MDER_P8 (0x1u << 8) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
| 2410 | #define PIO_MDER_P9 (0x1u << 9) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
| 2411 | #define PIO_MDER_P10 (0x1u << 10) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
| 2412 | #define PIO_MDER_P11 (0x1u << 11) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
| 2413 | #define PIO_MDER_P12 (0x1u << 12) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
| 2414 | #define PIO_MDER_P13 (0x1u << 13) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
| 2415 | #define PIO_MDER_P14 (0x1u << 14) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
| 2416 | #define PIO_MDER_P15 (0x1u << 15) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
| 2417 | #define PIO_MDER_P16 (0x1u << 16) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
| 2418 | #define PIO_MDER_P17 (0x1u << 17) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
| 2419 | #define PIO_MDER_P18 (0x1u << 18) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
| 2420 | #define PIO_MDER_P19 (0x1u << 19) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
| 2421 | #define PIO_MDER_P20 (0x1u << 20) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
| 2422 | #define PIO_MDER_P21 (0x1u << 21) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
| 2423 | #define PIO_MDER_P22 (0x1u << 22) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
| 2424 | #define PIO_MDER_P23 (0x1u << 23) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
| 2425 | #define PIO_MDER_P24 (0x1u << 24) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
| 2426 | #define PIO_MDER_P25 (0x1u << 25) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
| 2427 | #define PIO_MDER_P26 (0x1u << 26) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
| 2428 | #define PIO_MDER_P27 (0x1u << 27) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
| 2429 | #define PIO_MDER_P28 (0x1u << 28) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
| 2430 | #define PIO_MDER_P29 (0x1u << 29) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
| 2431 | #define PIO_MDER_P30 (0x1u << 30) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
| 2432 | #define PIO_MDER_P31 (0x1u << 31) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
| 2433 | /* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */ |
| 2434 | #define PIO_MDDR_P0 (0x1u << 0) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| 2435 | #define PIO_MDDR_P1 (0x1u << 1) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| 2436 | #define PIO_MDDR_P2 (0x1u << 2) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| 2437 | #define PIO_MDDR_P3 (0x1u << 3) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| 2438 | #define PIO_MDDR_P4 (0x1u << 4) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| 2439 | #define PIO_MDDR_P5 (0x1u << 5) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| 2440 | #define PIO_MDDR_P6 (0x1u << 6) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| 2441 | #define PIO_MDDR_P7 (0x1u << 7) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| 2442 | #define PIO_MDDR_P8 (0x1u << 8) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| 2443 | #define PIO_MDDR_P9 (0x1u << 9) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| 2444 | #define PIO_MDDR_P10 (0x1u << 10) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| 2445 | #define PIO_MDDR_P11 (0x1u << 11) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| 2446 | #define PIO_MDDR_P12 (0x1u << 12) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| 2447 | #define PIO_MDDR_P13 (0x1u << 13) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| 2448 | #define PIO_MDDR_P14 (0x1u << 14) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| 2449 | #define PIO_MDDR_P15 (0x1u << 15) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| 2450 | #define PIO_MDDR_P16 (0x1u << 16) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| 2451 | #define PIO_MDDR_P17 (0x1u << 17) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| 2452 | #define PIO_MDDR_P18 (0x1u << 18) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| 2453 | #define PIO_MDDR_P19 (0x1u << 19) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| 2454 | #define PIO_MDDR_P20 (0x1u << 20) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| 2455 | #define PIO_MDDR_P21 (0x1u << 21) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| 2456 | #define PIO_MDDR_P22 (0x1u << 22) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| 2457 | #define PIO_MDDR_P23 (0x1u << 23) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| 2458 | #define PIO_MDDR_P24 (0x1u << 24) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| 2459 | #define PIO_MDDR_P25 (0x1u << 25) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| 2460 | #define PIO_MDDR_P26 (0x1u << 26) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| 2461 | #define PIO_MDDR_P27 (0x1u << 27) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| 2462 | #define PIO_MDDR_P28 (0x1u << 28) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| 2463 | #define PIO_MDDR_P29 (0x1u << 29) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| 2464 | #define PIO_MDDR_P30 (0x1u << 30) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| 2465 | #define PIO_MDDR_P31 (0x1u << 31) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| 2466 | /* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */ |
| 2467 | #define PIO_MDSR_P0 (0x1u << 0) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| 2468 | #define PIO_MDSR_P1 (0x1u << 1) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| 2469 | #define PIO_MDSR_P2 (0x1u << 2) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| 2470 | #define PIO_MDSR_P3 (0x1u << 3) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| 2471 | #define PIO_MDSR_P4 (0x1u << 4) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| 2472 | #define PIO_MDSR_P5 (0x1u << 5) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| 2473 | #define PIO_MDSR_P6 (0x1u << 6) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| 2474 | #define PIO_MDSR_P7 (0x1u << 7) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| 2475 | #define PIO_MDSR_P8 (0x1u << 8) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| 2476 | #define PIO_MDSR_P9 (0x1u << 9) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| 2477 | #define PIO_MDSR_P10 (0x1u << 10) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| 2478 | #define PIO_MDSR_P11 (0x1u << 11) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| 2479 | #define PIO_MDSR_P12 (0x1u << 12) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| 2480 | #define PIO_MDSR_P13 (0x1u << 13) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| 2481 | #define PIO_MDSR_P14 (0x1u << 14) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| 2482 | #define PIO_MDSR_P15 (0x1u << 15) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| 2483 | #define PIO_MDSR_P16 (0x1u << 16) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| 2484 | #define PIO_MDSR_P17 (0x1u << 17) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| 2485 | #define PIO_MDSR_P18 (0x1u << 18) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| 2486 | #define PIO_MDSR_P19 (0x1u << 19) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| 2487 | #define PIO_MDSR_P20 (0x1u << 20) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| 2488 | #define PIO_MDSR_P21 (0x1u << 21) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| 2489 | #define PIO_MDSR_P22 (0x1u << 22) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| 2490 | #define PIO_MDSR_P23 (0x1u << 23) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| 2491 | #define PIO_MDSR_P24 (0x1u << 24) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| 2492 | #define PIO_MDSR_P25 (0x1u << 25) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| 2493 | #define PIO_MDSR_P26 (0x1u << 26) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| 2494 | #define PIO_MDSR_P27 (0x1u << 27) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| 2495 | #define PIO_MDSR_P28 (0x1u << 28) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| 2496 | #define PIO_MDSR_P29 (0x1u << 29) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| 2497 | #define PIO_MDSR_P30 (0x1u << 30) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| 2498 | #define PIO_MDSR_P31 (0x1u << 31) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| 2499 | /* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */ |
| 2500 | #define PIO_PUDR_P0 (0x1u << 0) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| 2501 | #define PIO_PUDR_P1 (0x1u << 1) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| 2502 | #define PIO_PUDR_P2 (0x1u << 2) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| 2503 | #define PIO_PUDR_P3 (0x1u << 3) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| 2504 | #define PIO_PUDR_P4 (0x1u << 4) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| 2505 | #define PIO_PUDR_P5 (0x1u << 5) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| 2506 | #define PIO_PUDR_P6 (0x1u << 6) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| 2507 | #define PIO_PUDR_P7 (0x1u << 7) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| 2508 | #define PIO_PUDR_P8 (0x1u << 8) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| 2509 | #define PIO_PUDR_P9 (0x1u << 9) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| 2510 | #define PIO_PUDR_P10 (0x1u << 10) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| 2511 | #define PIO_PUDR_P11 (0x1u << 11) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| 2512 | #define PIO_PUDR_P12 (0x1u << 12) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| 2513 | #define PIO_PUDR_P13 (0x1u << 13) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| 2514 | #define PIO_PUDR_P14 (0x1u << 14) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| 2515 | #define PIO_PUDR_P15 (0x1u << 15) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| 2516 | #define PIO_PUDR_P16 (0x1u << 16) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| 2517 | #define PIO_PUDR_P17 (0x1u << 17) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| 2518 | #define PIO_PUDR_P18 (0x1u << 18) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| 2519 | #define PIO_PUDR_P19 (0x1u << 19) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| 2520 | #define PIO_PUDR_P20 (0x1u << 20) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| 2521 | #define PIO_PUDR_P21 (0x1u << 21) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| 2522 | #define PIO_PUDR_P22 (0x1u << 22) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| 2523 | #define PIO_PUDR_P23 (0x1u << 23) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| 2524 | #define PIO_PUDR_P24 (0x1u << 24) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| 2525 | #define PIO_PUDR_P25 (0x1u << 25) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| 2526 | #define PIO_PUDR_P26 (0x1u << 26) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| 2527 | #define PIO_PUDR_P27 (0x1u << 27) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| 2528 | #define PIO_PUDR_P28 (0x1u << 28) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| 2529 | #define PIO_PUDR_P29 (0x1u << 29) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| 2530 | #define PIO_PUDR_P30 (0x1u << 30) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| 2531 | #define PIO_PUDR_P31 (0x1u << 31) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| 2532 | /* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */ |
| 2533 | #define PIO_PUER_P0 (0x1u << 0) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| 2534 | #define PIO_PUER_P1 (0x1u << 1) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| 2535 | #define PIO_PUER_P2 (0x1u << 2) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| 2536 | #define PIO_PUER_P3 (0x1u << 3) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| 2537 | #define PIO_PUER_P4 (0x1u << 4) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| 2538 | #define PIO_PUER_P5 (0x1u << 5) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| 2539 | #define PIO_PUER_P6 (0x1u << 6) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| 2540 | #define PIO_PUER_P7 (0x1u << 7) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| 2541 | #define PIO_PUER_P8 (0x1u << 8) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| 2542 | #define PIO_PUER_P9 (0x1u << 9) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| 2543 | #define PIO_PUER_P10 (0x1u << 10) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| 2544 | #define PIO_PUER_P11 (0x1u << 11) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| 2545 | #define PIO_PUER_P12 (0x1u << 12) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| 2546 | #define PIO_PUER_P13 (0x1u << 13) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| 2547 | #define PIO_PUER_P14 (0x1u << 14) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| 2548 | #define PIO_PUER_P15 (0x1u << 15) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| 2549 | #define PIO_PUER_P16 (0x1u << 16) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| 2550 | #define PIO_PUER_P17 (0x1u << 17) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| 2551 | #define PIO_PUER_P18 (0x1u << 18) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| 2552 | #define PIO_PUER_P19 (0x1u << 19) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| 2553 | #define PIO_PUER_P20 (0x1u << 20) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| 2554 | #define PIO_PUER_P21 (0x1u << 21) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| 2555 | #define PIO_PUER_P22 (0x1u << 22) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| 2556 | #define PIO_PUER_P23 (0x1u << 23) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| 2557 | #define PIO_PUER_P24 (0x1u << 24) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| 2558 | #define PIO_PUER_P25 (0x1u << 25) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| 2559 | #define PIO_PUER_P26 (0x1u << 26) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| 2560 | #define PIO_PUER_P27 (0x1u << 27) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| 2561 | #define PIO_PUER_P28 (0x1u << 28) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| 2562 | #define PIO_PUER_P29 (0x1u << 29) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| 2563 | #define PIO_PUER_P30 (0x1u << 30) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| 2564 | #define PIO_PUER_P31 (0x1u << 31) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| 2565 | /* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */ |
| 2566 | #define PIO_PUSR_P0 (0x1u << 0) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| 2567 | #define PIO_PUSR_P1 (0x1u << 1) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| 2568 | #define PIO_PUSR_P2 (0x1u << 2) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| 2569 | #define PIO_PUSR_P3 (0x1u << 3) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| 2570 | #define PIO_PUSR_P4 (0x1u << 4) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| 2571 | #define PIO_PUSR_P5 (0x1u << 5) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| 2572 | #define PIO_PUSR_P6 (0x1u << 6) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| 2573 | #define PIO_PUSR_P7 (0x1u << 7) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| 2574 | #define PIO_PUSR_P8 (0x1u << 8) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| 2575 | #define PIO_PUSR_P9 (0x1u << 9) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| 2576 | #define PIO_PUSR_P10 (0x1u << 10) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| 2577 | #define PIO_PUSR_P11 (0x1u << 11) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| 2578 | #define PIO_PUSR_P12 (0x1u << 12) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| 2579 | #define PIO_PUSR_P13 (0x1u << 13) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| 2580 | #define PIO_PUSR_P14 (0x1u << 14) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| 2581 | #define PIO_PUSR_P15 (0x1u << 15) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| 2582 | #define PIO_PUSR_P16 (0x1u << 16) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| 2583 | #define PIO_PUSR_P17 (0x1u << 17) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| 2584 | #define PIO_PUSR_P18 (0x1u << 18) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| 2585 | #define PIO_PUSR_P19 (0x1u << 19) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| 2586 | #define PIO_PUSR_P20 (0x1u << 20) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| 2587 | #define PIO_PUSR_P21 (0x1u << 21) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| 2588 | #define PIO_PUSR_P22 (0x1u << 22) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| 2589 | #define PIO_PUSR_P23 (0x1u << 23) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| 2590 | #define PIO_PUSR_P24 (0x1u << 24) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| 2591 | #define PIO_PUSR_P25 (0x1u << 25) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| 2592 | #define PIO_PUSR_P26 (0x1u << 26) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| 2593 | #define PIO_PUSR_P27 (0x1u << 27) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| 2594 | #define PIO_PUSR_P28 (0x1u << 28) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| 2595 | #define PIO_PUSR_P29 (0x1u << 29) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| 2596 | #define PIO_PUSR_P30 (0x1u << 30) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| 2597 | #define PIO_PUSR_P31 (0x1u << 31) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| 2598 | /* -------- PIO_ABCDSR[2] : (PIO Offset: 0x0070) Peripheral Select Register -------- */ |
| 2599 | #define PIO_ABCDSR_P0 (0x1u << 0) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ |
| 2600 | #define PIO_ABCDSR_P1 (0x1u << 1) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ |
| 2601 | #define PIO_ABCDSR_P2 (0x1u << 2) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ |
| 2602 | #define PIO_ABCDSR_P3 (0x1u << 3) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ |
| 2603 | #define PIO_ABCDSR_P4 (0x1u << 4) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ |
| 2604 | #define PIO_ABCDSR_P5 (0x1u << 5) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ |
| 2605 | #define PIO_ABCDSR_P6 (0x1u << 6) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ |
| 2606 | #define PIO_ABCDSR_P7 (0x1u << 7) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ |
| 2607 | #define PIO_ABCDSR_P8 (0x1u << 8) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ |
| 2608 | #define PIO_ABCDSR_P9 (0x1u << 9) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ |
| 2609 | #define PIO_ABCDSR_P10 (0x1u << 10) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ |
| 2610 | #define PIO_ABCDSR_P11 (0x1u << 11) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ |
| 2611 | #define PIO_ABCDSR_P12 (0x1u << 12) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ |
| 2612 | #define PIO_ABCDSR_P13 (0x1u << 13) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ |
| 2613 | #define PIO_ABCDSR_P14 (0x1u << 14) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ |
| 2614 | #define PIO_ABCDSR_P15 (0x1u << 15) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ |
| 2615 | #define PIO_ABCDSR_P16 (0x1u << 16) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ |
| 2616 | #define PIO_ABCDSR_P17 (0x1u << 17) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ |
| 2617 | #define PIO_ABCDSR_P18 (0x1u << 18) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ |
| 2618 | #define PIO_ABCDSR_P19 (0x1u << 19) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ |
| 2619 | #define PIO_ABCDSR_P20 (0x1u << 20) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ |
| 2620 | #define PIO_ABCDSR_P21 (0x1u << 21) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ |
| 2621 | #define PIO_ABCDSR_P22 (0x1u << 22) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ |
| 2622 | #define PIO_ABCDSR_P23 (0x1u << 23) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ |
| 2623 | #define PIO_ABCDSR_P24 (0x1u << 24) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ |
| 2624 | #define PIO_ABCDSR_P25 (0x1u << 25) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ |
| 2625 | #define PIO_ABCDSR_P26 (0x1u << 26) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ |
| 2626 | #define PIO_ABCDSR_P27 (0x1u << 27) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ |
| 2627 | #define PIO_ABCDSR_P28 (0x1u << 28) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ |
| 2628 | #define PIO_ABCDSR_P29 (0x1u << 29) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ |
| 2629 | #define PIO_ABCDSR_P30 (0x1u << 30) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ |
| 2630 | #define PIO_ABCDSR_P31 (0x1u << 31) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ |
| 2631 | /* -------- PIO_IFSCDR : (PIO Offset: 0x0080) Input Filter Slow Clock Disable Register -------- */ |
| 2632 | #define PIO_IFSCDR_P0 (0x1u << 0) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ |
| 2633 | #define PIO_IFSCDR_P1 (0x1u << 1) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ |
| 2634 | #define PIO_IFSCDR_P2 (0x1u << 2) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ |
| 2635 | #define PIO_IFSCDR_P3 (0x1u << 3) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ |
| 2636 | #define PIO_IFSCDR_P4 (0x1u << 4) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ |
| 2637 | #define PIO_IFSCDR_P5 (0x1u << 5) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ |
| 2638 | #define PIO_IFSCDR_P6 (0x1u << 6) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ |
| 2639 | #define PIO_IFSCDR_P7 (0x1u << 7) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ |
| 2640 | #define PIO_IFSCDR_P8 (0x1u << 8) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ |
| 2641 | #define PIO_IFSCDR_P9 (0x1u << 9) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ |
| 2642 | #define PIO_IFSCDR_P10 (0x1u << 10) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ |
| 2643 | #define PIO_IFSCDR_P11 (0x1u << 11) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ |
| 2644 | #define PIO_IFSCDR_P12 (0x1u << 12) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ |
| 2645 | #define PIO_IFSCDR_P13 (0x1u << 13) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ |
| 2646 | #define PIO_IFSCDR_P14 (0x1u << 14) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ |
| 2647 | #define PIO_IFSCDR_P15 (0x1u << 15) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ |
| 2648 | #define PIO_IFSCDR_P16 (0x1u << 16) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ |
| 2649 | #define PIO_IFSCDR_P17 (0x1u << 17) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ |
| 2650 | #define PIO_IFSCDR_P18 (0x1u << 18) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ |
| 2651 | #define PIO_IFSCDR_P19 (0x1u << 19) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ |
| 2652 | #define PIO_IFSCDR_P20 (0x1u << 20) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ |
| 2653 | #define PIO_IFSCDR_P21 (0x1u << 21) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ |
| 2654 | #define PIO_IFSCDR_P22 (0x1u << 22) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ |
| 2655 | #define PIO_IFSCDR_P23 (0x1u << 23) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ |
| 2656 | #define PIO_IFSCDR_P24 (0x1u << 24) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ |
| 2657 | #define PIO_IFSCDR_P25 (0x1u << 25) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ |
| 2658 | #define PIO_IFSCDR_P26 (0x1u << 26) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ |
| 2659 | #define PIO_IFSCDR_P27 (0x1u << 27) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ |
| 2660 | #define PIO_IFSCDR_P28 (0x1u << 28) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ |
| 2661 | #define PIO_IFSCDR_P29 (0x1u << 29) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ |
| 2662 | #define PIO_IFSCDR_P30 (0x1u << 30) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ |
| 2663 | #define PIO_IFSCDR_P31 (0x1u << 31) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ |
| 2664 | /* -------- PIO_IFSCER : (PIO Offset: 0x0084) Input Filter Slow Clock Enable Register -------- */ |
| 2665 | #define PIO_IFSCER_P0 (0x1u << 0) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ |
| 2666 | #define PIO_IFSCER_P1 (0x1u << 1) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ |
| 2667 | #define PIO_IFSCER_P2 (0x1u << 2) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ |
| 2668 | #define PIO_IFSCER_P3 (0x1u << 3) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ |
| 2669 | #define PIO_IFSCER_P4 (0x1u << 4) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ |
| 2670 | #define PIO_IFSCER_P5 (0x1u << 5) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ |
| 2671 | #define PIO_IFSCER_P6 (0x1u << 6) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ |
| 2672 | #define PIO_IFSCER_P7 (0x1u << 7) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ |
| 2673 | #define PIO_IFSCER_P8 (0x1u << 8) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ |
| 2674 | #define PIO_IFSCER_P9 (0x1u << 9) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ |
| 2675 | #define PIO_IFSCER_P10 (0x1u << 10) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ |
| 2676 | #define PIO_IFSCER_P11 (0x1u << 11) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ |
| 2677 | #define PIO_IFSCER_P12 (0x1u << 12) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ |
| 2678 | #define PIO_IFSCER_P13 (0x1u << 13) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ |
| 2679 | #define PIO_IFSCER_P14 (0x1u << 14) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ |
| 2680 | #define PIO_IFSCER_P15 (0x1u << 15) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ |
| 2681 | #define PIO_IFSCER_P16 (0x1u << 16) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ |
| 2682 | #define PIO_IFSCER_P17 (0x1u << 17) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ |
| 2683 | #define PIO_IFSCER_P18 (0x1u << 18) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ |
| 2684 | #define PIO_IFSCER_P19 (0x1u << 19) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ |
| 2685 | #define PIO_IFSCER_P20 (0x1u << 20) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ |
| 2686 | #define PIO_IFSCER_P21 (0x1u << 21) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ |
| 2687 | #define PIO_IFSCER_P22 (0x1u << 22) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ |
| 2688 | #define PIO_IFSCER_P23 (0x1u << 23) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ |
| 2689 | #define PIO_IFSCER_P24 (0x1u << 24) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ |
| 2690 | #define PIO_IFSCER_P25 (0x1u << 25) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ |
| 2691 | #define PIO_IFSCER_P26 (0x1u << 26) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ |
| 2692 | #define PIO_IFSCER_P27 (0x1u << 27) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ |
| 2693 | #define PIO_IFSCER_P28 (0x1u << 28) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ |
| 2694 | #define PIO_IFSCER_P29 (0x1u << 29) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ |
| 2695 | #define PIO_IFSCER_P30 (0x1u << 30) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ |
| 2696 | #define PIO_IFSCER_P31 (0x1u << 31) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ |
| 2697 | /* -------- PIO_IFSCSR : (PIO Offset: 0x0088) Input Filter Slow Clock Status Register -------- */ |
| 2698 | #define PIO_IFSCSR_P0 (0x1u << 0) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ |
| 2699 | #define PIO_IFSCSR_P1 (0x1u << 1) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ |
| 2700 | #define PIO_IFSCSR_P2 (0x1u << 2) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ |
| 2701 | #define PIO_IFSCSR_P3 (0x1u << 3) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ |
| 2702 | #define PIO_IFSCSR_P4 (0x1u << 4) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ |
| 2703 | #define PIO_IFSCSR_P5 (0x1u << 5) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ |
| 2704 | #define PIO_IFSCSR_P6 (0x1u << 6) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ |
| 2705 | #define PIO_IFSCSR_P7 (0x1u << 7) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ |
| 2706 | #define PIO_IFSCSR_P8 (0x1u << 8) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ |
| 2707 | #define PIO_IFSCSR_P9 (0x1u << 9) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ |
| 2708 | #define PIO_IFSCSR_P10 (0x1u << 10) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ |
| 2709 | #define PIO_IFSCSR_P11 (0x1u << 11) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ |
| 2710 | #define PIO_IFSCSR_P12 (0x1u << 12) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ |
| 2711 | #define PIO_IFSCSR_P13 (0x1u << 13) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ |
| 2712 | #define PIO_IFSCSR_P14 (0x1u << 14) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ |
| 2713 | #define PIO_IFSCSR_P15 (0x1u << 15) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ |
| 2714 | #define PIO_IFSCSR_P16 (0x1u << 16) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ |
| 2715 | #define PIO_IFSCSR_P17 (0x1u << 17) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ |
| 2716 | #define PIO_IFSCSR_P18 (0x1u << 18) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ |
| 2717 | #define PIO_IFSCSR_P19 (0x1u << 19) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ |
| 2718 | #define PIO_IFSCSR_P20 (0x1u << 20) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ |
| 2719 | #define PIO_IFSCSR_P21 (0x1u << 21) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ |
| 2720 | #define PIO_IFSCSR_P22 (0x1u << 22) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ |
| 2721 | #define PIO_IFSCSR_P23 (0x1u << 23) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ |
| 2722 | #define PIO_IFSCSR_P24 (0x1u << 24) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ |
| 2723 | #define PIO_IFSCSR_P25 (0x1u << 25) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ |
| 2724 | #define PIO_IFSCSR_P26 (0x1u << 26) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ |
| 2725 | #define PIO_IFSCSR_P27 (0x1u << 27) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ |
| 2726 | #define PIO_IFSCSR_P28 (0x1u << 28) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ |
| 2727 | #define PIO_IFSCSR_P29 (0x1u << 29) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ |
| 2728 | #define PIO_IFSCSR_P30 (0x1u << 30) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ |
| 2729 | #define PIO_IFSCSR_P31 (0x1u << 31) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ |
| 2730 | /* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */ |
| 2731 | #define PIO_SCDR_DIV0 (0x1u << 0) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ |
| 2732 | #define PIO_SCDR_DIV1 (0x1u << 1) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ |
| 2733 | #define PIO_SCDR_DIV2 (0x1u << 2) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ |
| 2734 | #define PIO_SCDR_DIV3 (0x1u << 3) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ |
| 2735 | #define PIO_SCDR_DIV4 (0x1u << 4) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ |
| 2736 | #define PIO_SCDR_DIV5 (0x1u << 5) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ |
| 2737 | #define PIO_SCDR_DIV6 (0x1u << 6) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ |
| 2738 | #define PIO_SCDR_DIV7 (0x1u << 7) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ |
| 2739 | #define PIO_SCDR_DIV8 (0x1u << 8) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ |
| 2740 | #define PIO_SCDR_DIV9 (0x1u << 9) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ |
| 2741 | #define PIO_SCDR_DIV10 (0x1u << 10) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ |
| 2742 | #define PIO_SCDR_DIV11 (0x1u << 11) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ |
| 2743 | #define PIO_SCDR_DIV12 (0x1u << 12) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ |
| 2744 | #define PIO_SCDR_DIV13 (0x1u << 13) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ |
| 2745 | /* -------- PIO_PPDDR : (PIO Offset: 0x0090) Pad Pull-down Disable Register -------- */ |
| 2746 | #define PIO_PPDDR_P0 (0x1u << 0) /**< \brief (PIO_PPDDR) Pull Down Disable. */ |
| 2747 | #define PIO_PPDDR_P1 (0x1u << 1) /**< \brief (PIO_PPDDR) Pull Down Disable. */ |
| 2748 | #define PIO_PPDDR_P2 (0x1u << 2) /**< \brief (PIO_PPDDR) Pull Down Disable. */ |
| 2749 | #define PIO_PPDDR_P3 (0x1u << 3) /**< \brief (PIO_PPDDR) Pull Down Disable. */ |
| 2750 | #define PIO_PPDDR_P4 (0x1u << 4) /**< \brief (PIO_PPDDR) Pull Down Disable. */ |
| 2751 | #define PIO_PPDDR_P5 (0x1u << 5) /**< \brief (PIO_PPDDR) Pull Down Disable. */ |
| 2752 | #define PIO_PPDDR_P6 (0x1u << 6) /**< \brief (PIO_PPDDR) Pull Down Disable. */ |
| 2753 | #define PIO_PPDDR_P7 (0x1u << 7) /**< \brief (PIO_PPDDR) Pull Down Disable. */ |
| 2754 | #define PIO_PPDDR_P8 (0x1u << 8) /**< \brief (PIO_PPDDR) Pull Down Disable. */ |
| 2755 | #define PIO_PPDDR_P9 (0x1u << 9) /**< \brief (PIO_PPDDR) Pull Down Disable. */ |
| 2756 | #define PIO_PPDDR_P10 (0x1u << 10) /**< \brief (PIO_PPDDR) Pull Down Disable. */ |
| 2757 | #define PIO_PPDDR_P11 (0x1u << 11) /**< \brief (PIO_PPDDR) Pull Down Disable. */ |
| 2758 | #define PIO_PPDDR_P12 (0x1u << 12) /**< \brief (PIO_PPDDR) Pull Down Disable. */ |
| 2759 | #define PIO_PPDDR_P13 (0x1u << 13) /**< \brief (PIO_PPDDR) Pull Down Disable. */ |
| 2760 | #define PIO_PPDDR_P14 (0x1u << 14) /**< \brief (PIO_PPDDR) Pull Down Disable. */ |
| 2761 | #define PIO_PPDDR_P15 (0x1u << 15) /**< \brief (PIO_PPDDR) Pull Down Disable. */ |
| 2762 | #define PIO_PPDDR_P16 (0x1u << 16) /**< \brief (PIO_PPDDR) Pull Down Disable. */ |
| 2763 | #define PIO_PPDDR_P17 (0x1u << 17) /**< \brief (PIO_PPDDR) Pull Down Disable. */ |
| 2764 | #define PIO_PPDDR_P18 (0x1u << 18) /**< \brief (PIO_PPDDR) Pull Down Disable. */ |
| 2765 | #define PIO_PPDDR_P19 (0x1u << 19) /**< \brief (PIO_PPDDR) Pull Down Disable. */ |
| 2766 | #define PIO_PPDDR_P20 (0x1u << 20) /**< \brief (PIO_PPDDR) Pull Down Disable. */ |
| 2767 | #define PIO_PPDDR_P21 (0x1u << 21) /**< \brief (PIO_PPDDR) Pull Down Disable. */ |
| 2768 | #define PIO_PPDDR_P22 (0x1u << 22) /**< \brief (PIO_PPDDR) Pull Down Disable. */ |
| 2769 | #define PIO_PPDDR_P23 (0x1u << 23) /**< \brief (PIO_PPDDR) Pull Down Disable. */ |
| 2770 | #define PIO_PPDDR_P24 (0x1u << 24) /**< \brief (PIO_PPDDR) Pull Down Disable. */ |
| 2771 | #define PIO_PPDDR_P25 (0x1u << 25) /**< \brief (PIO_PPDDR) Pull Down Disable. */ |
| 2772 | #define PIO_PPDDR_P26 (0x1u << 26) /**< \brief (PIO_PPDDR) Pull Down Disable. */ |
| 2773 | #define PIO_PPDDR_P27 (0x1u << 27) /**< \brief (PIO_PPDDR) Pull Down Disable. */ |
| 2774 | #define PIO_PPDDR_P28 (0x1u << 28) /**< \brief (PIO_PPDDR) Pull Down Disable. */ |
| 2775 | #define PIO_PPDDR_P29 (0x1u << 29) /**< \brief (PIO_PPDDR) Pull Down Disable. */ |
| 2776 | #define PIO_PPDDR_P30 (0x1u << 30) /**< \brief (PIO_PPDDR) Pull Down Disable. */ |
| 2777 | #define PIO_PPDDR_P31 (0x1u << 31) /**< \brief (PIO_PPDDR) Pull Down Disable. */ |
| 2778 | /* -------- PIO_PPDER : (PIO Offset: 0x0094) Pad Pull-down Enable Register -------- */ |
| 2779 | #define PIO_PPDER_P0 (0x1u << 0) /**< \brief (PIO_PPDER) Pull Down Enable. */ |
| 2780 | #define PIO_PPDER_P1 (0x1u << 1) /**< \brief (PIO_PPDER) Pull Down Enable. */ |
| 2781 | #define PIO_PPDER_P2 (0x1u << 2) /**< \brief (PIO_PPDER) Pull Down Enable. */ |
| 2782 | #define PIO_PPDER_P3 (0x1u << 3) /**< \brief (PIO_PPDER) Pull Down Enable. */ |
| 2783 | #define PIO_PPDER_P4 (0x1u << 4) /**< \brief (PIO_PPDER) Pull Down Enable. */ |
| 2784 | #define PIO_PPDER_P5 (0x1u << 5) /**< \brief (PIO_PPDER) Pull Down Enable. */ |
| 2785 | #define PIO_PPDER_P6 (0x1u << 6) /**< \brief (PIO_PPDER) Pull Down Enable. */ |
| 2786 | #define PIO_PPDER_P7 (0x1u << 7) /**< \brief (PIO_PPDER) Pull Down Enable. */ |
| 2787 | #define PIO_PPDER_P8 (0x1u << 8) /**< \brief (PIO_PPDER) Pull Down Enable. */ |
| 2788 | #define PIO_PPDER_P9 (0x1u << 9) /**< \brief (PIO_PPDER) Pull Down Enable. */ |
| 2789 | #define PIO_PPDER_P10 (0x1u << 10) /**< \brief (PIO_PPDER) Pull Down Enable. */ |
| 2790 | #define PIO_PPDER_P11 (0x1u << 11) /**< \brief (PIO_PPDER) Pull Down Enable. */ |
| 2791 | #define PIO_PPDER_P12 (0x1u << 12) /**< \brief (PIO_PPDER) Pull Down Enable. */ |
| 2792 | #define PIO_PPDER_P13 (0x1u << 13) /**< \brief (PIO_PPDER) Pull Down Enable. */ |
| 2793 | #define PIO_PPDER_P14 (0x1u << 14) /**< \brief (PIO_PPDER) Pull Down Enable. */ |
| 2794 | #define PIO_PPDER_P15 (0x1u << 15) /**< \brief (PIO_PPDER) Pull Down Enable. */ |
| 2795 | #define PIO_PPDER_P16 (0x1u << 16) /**< \brief (PIO_PPDER) Pull Down Enable. */ |
| 2796 | #define PIO_PPDER_P17 (0x1u << 17) /**< \brief (PIO_PPDER) Pull Down Enable. */ |
| 2797 | #define PIO_PPDER_P18 (0x1u << 18) /**< \brief (PIO_PPDER) Pull Down Enable. */ |
| 2798 | #define PIO_PPDER_P19 (0x1u << 19) /**< \brief (PIO_PPDER) Pull Down Enable. */ |
| 2799 | #define PIO_PPDER_P20 (0x1u << 20) /**< \brief (PIO_PPDER) Pull Down Enable. */ |
| 2800 | #define PIO_PPDER_P21 (0x1u << 21) /**< \brief (PIO_PPDER) Pull Down Enable. */ |
| 2801 | #define PIO_PPDER_P22 (0x1u << 22) /**< \brief (PIO_PPDER) Pull Down Enable. */ |
| 2802 | #define PIO_PPDER_P23 (0x1u << 23) /**< \brief (PIO_PPDER) Pull Down Enable. */ |
| 2803 | #define PIO_PPDER_P24 (0x1u << 24) /**< \brief (PIO_PPDER) Pull Down Enable. */ |
| 2804 | #define PIO_PPDER_P25 (0x1u << 25) /**< \brief (PIO_PPDER) Pull Down Enable. */ |
| 2805 | #define PIO_PPDER_P26 (0x1u << 26) /**< \brief (PIO_PPDER) Pull Down Enable. */ |
| 2806 | #define PIO_PPDER_P27 (0x1u << 27) /**< \brief (PIO_PPDER) Pull Down Enable. */ |
| 2807 | #define PIO_PPDER_P28 (0x1u << 28) /**< \brief (PIO_PPDER) Pull Down Enable. */ |
| 2808 | #define PIO_PPDER_P29 (0x1u << 29) /**< \brief (PIO_PPDER) Pull Down Enable. */ |
| 2809 | #define PIO_PPDER_P30 (0x1u << 30) /**< \brief (PIO_PPDER) Pull Down Enable. */ |
| 2810 | #define PIO_PPDER_P31 (0x1u << 31) /**< \brief (PIO_PPDER) Pull Down Enable. */ |
| 2811 | /* -------- PIO_PPDSR : (PIO Offset: 0x0098) Pad Pull-down Status Register -------- */ |
| 2812 | #define PIO_PPDSR_P0 (0x1u << 0) /**< \brief (PIO_PPDSR) Pull Down Status. */ |
| 2813 | #define PIO_PPDSR_P1 (0x1u << 1) /**< \brief (PIO_PPDSR) Pull Down Status. */ |
| 2814 | #define PIO_PPDSR_P2 (0x1u << 2) /**< \brief (PIO_PPDSR) Pull Down Status. */ |
| 2815 | #define PIO_PPDSR_P3 (0x1u << 3) /**< \brief (PIO_PPDSR) Pull Down Status. */ |
| 2816 | #define PIO_PPDSR_P4 (0x1u << 4) /**< \brief (PIO_PPDSR) Pull Down Status. */ |
| 2817 | #define PIO_PPDSR_P5 (0x1u << 5) /**< \brief (PIO_PPDSR) Pull Down Status. */ |
| 2818 | #define PIO_PPDSR_P6 (0x1u << 6) /**< \brief (PIO_PPDSR) Pull Down Status. */ |
| 2819 | #define PIO_PPDSR_P7 (0x1u << 7) /**< \brief (PIO_PPDSR) Pull Down Status. */ |
| 2820 | #define PIO_PPDSR_P8 (0x1u << 8) /**< \brief (PIO_PPDSR) Pull Down Status. */ |
| 2821 | #define PIO_PPDSR_P9 (0x1u << 9) /**< \brief (PIO_PPDSR) Pull Down Status. */ |
| 2822 | #define PIO_PPDSR_P10 (0x1u << 10) /**< \brief (PIO_PPDSR) Pull Down Status. */ |
| 2823 | #define PIO_PPDSR_P11 (0x1u << 11) /**< \brief (PIO_PPDSR) Pull Down Status. */ |
| 2824 | #define PIO_PPDSR_P12 (0x1u << 12) /**< \brief (PIO_PPDSR) Pull Down Status. */ |
| 2825 | #define PIO_PPDSR_P13 (0x1u << 13) /**< \brief (PIO_PPDSR) Pull Down Status. */ |
| 2826 | #define PIO_PPDSR_P14 (0x1u << 14) /**< \brief (PIO_PPDSR) Pull Down Status. */ |
| 2827 | #define PIO_PPDSR_P15 (0x1u << 15) /**< \brief (PIO_PPDSR) Pull Down Status. */ |
| 2828 | #define PIO_PPDSR_P16 (0x1u << 16) /**< \brief (PIO_PPDSR) Pull Down Status. */ |
| 2829 | #define PIO_PPDSR_P17 (0x1u << 17) /**< \brief (PIO_PPDSR) Pull Down Status. */ |
| 2830 | #define PIO_PPDSR_P18 (0x1u << 18) /**< \brief (PIO_PPDSR) Pull Down Status. */ |
| 2831 | #define PIO_PPDSR_P19 (0x1u << 19) /**< \brief (PIO_PPDSR) Pull Down Status. */ |
| 2832 | #define PIO_PPDSR_P20 (0x1u << 20) /**< \brief (PIO_PPDSR) Pull Down Status. */ |
| 2833 | #define PIO_PPDSR_P21 (0x1u << 21) /**< \brief (PIO_PPDSR) Pull Down Status. */ |
| 2834 | #define PIO_PPDSR_P22 (0x1u << 22) /**< \brief (PIO_PPDSR) Pull Down Status. */ |
| 2835 | #define PIO_PPDSR_P23 (0x1u << 23) /**< \brief (PIO_PPDSR) Pull Down Status. */ |
| 2836 | #define PIO_PPDSR_P24 (0x1u << 24) /**< \brief (PIO_PPDSR) Pull Down Status. */ |
| 2837 | #define PIO_PPDSR_P25 (0x1u << 25) /**< \brief (PIO_PPDSR) Pull Down Status. */ |
| 2838 | #define PIO_PPDSR_P26 (0x1u << 26) /**< \brief (PIO_PPDSR) Pull Down Status. */ |
| 2839 | #define PIO_PPDSR_P27 (0x1u << 27) /**< \brief (PIO_PPDSR) Pull Down Status. */ |
| 2840 | #define PIO_PPDSR_P28 (0x1u << 28) /**< \brief (PIO_PPDSR) Pull Down Status. */ |
| 2841 | #define PIO_PPDSR_P29 (0x1u << 29) /**< \brief (PIO_PPDSR) Pull Down Status. */ |
| 2842 | #define PIO_PPDSR_P30 (0x1u << 30) /**< \brief (PIO_PPDSR) Pull Down Status. */ |
| 2843 | #define PIO_PPDSR_P31 (0x1u << 31) /**< \brief (PIO_PPDSR) Pull Down Status. */ |
| 2844 | /* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */ |
| 2845 | #define PIO_OWER_P0 (0x1u << 0) /**< \brief (PIO_OWER) Output Write Enable. */ |
| 2846 | #define PIO_OWER_P1 (0x1u << 1) /**< \brief (PIO_OWER) Output Write Enable. */ |
| 2847 | #define PIO_OWER_P2 (0x1u << 2) /**< \brief (PIO_OWER) Output Write Enable. */ |
| 2848 | #define PIO_OWER_P3 (0x1u << 3) /**< \brief (PIO_OWER) Output Write Enable. */ |
| 2849 | #define PIO_OWER_P4 (0x1u << 4) /**< \brief (PIO_OWER) Output Write Enable. */ |
| 2850 | #define PIO_OWER_P5 (0x1u << 5) /**< \brief (PIO_OWER) Output Write Enable. */ |
| 2851 | #define PIO_OWER_P6 (0x1u << 6) /**< \brief (PIO_OWER) Output Write Enable. */ |
| 2852 | #define PIO_OWER_P7 (0x1u << 7) /**< \brief (PIO_OWER) Output Write Enable. */ |
| 2853 | #define PIO_OWER_P8 (0x1u << 8) /**< \brief (PIO_OWER) Output Write Enable. */ |
| 2854 | #define PIO_OWER_P9 (0x1u << 9) /**< \brief (PIO_OWER) Output Write Enable. */ |
| 2855 | #define PIO_OWER_P10 (0x1u << 10) /**< \brief (PIO_OWER) Output Write Enable. */ |
| 2856 | #define PIO_OWER_P11 (0x1u << 11) /**< \brief (PIO_OWER) Output Write Enable. */ |
| 2857 | #define PIO_OWER_P12 (0x1u << 12) /**< \brief (PIO_OWER) Output Write Enable. */ |
| 2858 | #define PIO_OWER_P13 (0x1u << 13) /**< \brief (PIO_OWER) Output Write Enable. */ |
| 2859 | #define PIO_OWER_P14 (0x1u << 14) /**< \brief (PIO_OWER) Output Write Enable. */ |
| 2860 | #define PIO_OWER_P15 (0x1u << 15) /**< \brief (PIO_OWER) Output Write Enable. */ |
| 2861 | #define PIO_OWER_P16 (0x1u << 16) /**< \brief (PIO_OWER) Output Write Enable. */ |
| 2862 | #define PIO_OWER_P17 (0x1u << 17) /**< \brief (PIO_OWER) Output Write Enable. */ |
| 2863 | #define PIO_OWER_P18 (0x1u << 18) /**< \brief (PIO_OWER) Output Write Enable. */ |
| 2864 | #define PIO_OWER_P19 (0x1u << 19) /**< \brief (PIO_OWER) Output Write Enable. */ |
| 2865 | #define PIO_OWER_P20 (0x1u << 20) /**< \brief (PIO_OWER) Output Write Enable. */ |
| 2866 | #define PIO_OWER_P21 (0x1u << 21) /**< \brief (PIO_OWER) Output Write Enable. */ |
| 2867 | #define PIO_OWER_P22 (0x1u << 22) /**< \brief (PIO_OWER) Output Write Enable. */ |
| 2868 | #define PIO_OWER_P23 (0x1u << 23) /**< \brief (PIO_OWER) Output Write Enable. */ |
| 2869 | #define PIO_OWER_P24 (0x1u << 24) /**< \brief (PIO_OWER) Output Write Enable. */ |
| 2870 | #define PIO_OWER_P25 (0x1u << 25) /**< \brief (PIO_OWER) Output Write Enable. */ |
| 2871 | #define PIO_OWER_P26 (0x1u << 26) /**< \brief (PIO_OWER) Output Write Enable. */ |
| 2872 | #define PIO_OWER_P27 (0x1u << 27) /**< \brief (PIO_OWER) Output Write Enable. */ |
| 2873 | #define PIO_OWER_P28 (0x1u << 28) /**< \brief (PIO_OWER) Output Write Enable. */ |
| 2874 | #define PIO_OWER_P29 (0x1u << 29) /**< \brief (PIO_OWER) Output Write Enable. */ |
| 2875 | #define PIO_OWER_P30 (0x1u << 30) /**< \brief (PIO_OWER) Output Write Enable. */ |
| 2876 | #define PIO_OWER_P31 (0x1u << 31) /**< \brief (PIO_OWER) Output Write Enable. */ |
| 2877 | /* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */ |
| 2878 | #define PIO_OWDR_P0 (0x1u << 0) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| 2879 | #define PIO_OWDR_P1 (0x1u << 1) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| 2880 | #define PIO_OWDR_P2 (0x1u << 2) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| 2881 | #define PIO_OWDR_P3 (0x1u << 3) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| 2882 | #define PIO_OWDR_P4 (0x1u << 4) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| 2883 | #define PIO_OWDR_P5 (0x1u << 5) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| 2884 | #define PIO_OWDR_P6 (0x1u << 6) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| 2885 | #define PIO_OWDR_P7 (0x1u << 7) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| 2886 | #define PIO_OWDR_P8 (0x1u << 8) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| 2887 | #define PIO_OWDR_P9 (0x1u << 9) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| 2888 | #define PIO_OWDR_P10 (0x1u << 10) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| 2889 | #define PIO_OWDR_P11 (0x1u << 11) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| 2890 | #define PIO_OWDR_P12 (0x1u << 12) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| 2891 | #define PIO_OWDR_P13 (0x1u << 13) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| 2892 | #define PIO_OWDR_P14 (0x1u << 14) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| 2893 | #define PIO_OWDR_P15 (0x1u << 15) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| 2894 | #define PIO_OWDR_P16 (0x1u << 16) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| 2895 | #define PIO_OWDR_P17 (0x1u << 17) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| 2896 | #define PIO_OWDR_P18 (0x1u << 18) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| 2897 | #define PIO_OWDR_P19 (0x1u << 19) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| 2898 | #define PIO_OWDR_P20 (0x1u << 20) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| 2899 | #define PIO_OWDR_P21 (0x1u << 21) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| 2900 | #define PIO_OWDR_P22 (0x1u << 22) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| 2901 | #define PIO_OWDR_P23 (0x1u << 23) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| 2902 | #define PIO_OWDR_P24 (0x1u << 24) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| 2903 | #define PIO_OWDR_P25 (0x1u << 25) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| 2904 | #define PIO_OWDR_P26 (0x1u << 26) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| 2905 | #define PIO_OWDR_P27 (0x1u << 27) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| 2906 | #define PIO_OWDR_P28 (0x1u << 28) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| 2907 | #define PIO_OWDR_P29 (0x1u << 29) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| 2908 | #define PIO_OWDR_P30 (0x1u << 30) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| 2909 | #define PIO_OWDR_P31 (0x1u << 31) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| 2910 | /* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */ |
| 2911 | #define PIO_OWSR_P0 (0x1u << 0) /**< \brief (PIO_OWSR) Output Write Status. */ |
| 2912 | #define PIO_OWSR_P1 (0x1u << 1) /**< \brief (PIO_OWSR) Output Write Status. */ |
| 2913 | #define PIO_OWSR_P2 (0x1u << 2) /**< \brief (PIO_OWSR) Output Write Status. */ |
| 2914 | #define PIO_OWSR_P3 (0x1u << 3) /**< \brief (PIO_OWSR) Output Write Status. */ |
| 2915 | #define PIO_OWSR_P4 (0x1u << 4) /**< \brief (PIO_OWSR) Output Write Status. */ |
| 2916 | #define PIO_OWSR_P5 (0x1u << 5) /**< \brief (PIO_OWSR) Output Write Status. */ |
| 2917 | #define PIO_OWSR_P6 (0x1u << 6) /**< \brief (PIO_OWSR) Output Write Status. */ |
| 2918 | #define PIO_OWSR_P7 (0x1u << 7) /**< \brief (PIO_OWSR) Output Write Status. */ |
| 2919 | #define PIO_OWSR_P8 (0x1u << 8) /**< \brief (PIO_OWSR) Output Write Status. */ |
| 2920 | #define PIO_OWSR_P9 (0x1u << 9) /**< \brief (PIO_OWSR) Output Write Status. */ |
| 2921 | #define PIO_OWSR_P10 (0x1u << 10) /**< \brief (PIO_OWSR) Output Write Status. */ |
| 2922 | #define PIO_OWSR_P11 (0x1u << 11) /**< \brief (PIO_OWSR) Output Write Status. */ |
| 2923 | #define PIO_OWSR_P12 (0x1u << 12) /**< \brief (PIO_OWSR) Output Write Status. */ |
| 2924 | #define PIO_OWSR_P13 (0x1u << 13) /**< \brief (PIO_OWSR) Output Write Status. */ |
| 2925 | #define PIO_OWSR_P14 (0x1u << 14) /**< \brief (PIO_OWSR) Output Write Status. */ |
| 2926 | #define PIO_OWSR_P15 (0x1u << 15) /**< \brief (PIO_OWSR) Output Write Status. */ |
| 2927 | #define PIO_OWSR_P16 (0x1u << 16) /**< \brief (PIO_OWSR) Output Write Status. */ |
| 2928 | #define PIO_OWSR_P17 (0x1u << 17) /**< \brief (PIO_OWSR) Output Write Status. */ |
| 2929 | #define PIO_OWSR_P18 (0x1u << 18) /**< \brief (PIO_OWSR) Output Write Status. */ |
| 2930 | #define PIO_OWSR_P19 (0x1u << 19) /**< \brief (PIO_OWSR) Output Write Status. */ |
| 2931 | #define PIO_OWSR_P20 (0x1u << 20) /**< \brief (PIO_OWSR) Output Write Status. */ |
| 2932 | #define PIO_OWSR_P21 (0x1u << 21) /**< \brief (PIO_OWSR) Output Write Status. */ |
| 2933 | #define PIO_OWSR_P22 (0x1u << 22) /**< \brief (PIO_OWSR) Output Write Status. */ |
| 2934 | #define PIO_OWSR_P23 (0x1u << 23) /**< \brief (PIO_OWSR) Output Write Status. */ |
| 2935 | #define PIO_OWSR_P24 (0x1u << 24) /**< \brief (PIO_OWSR) Output Write Status. */ |
| 2936 | #define PIO_OWSR_P25 (0x1u << 25) /**< \brief (PIO_OWSR) Output Write Status. */ |
| 2937 | #define PIO_OWSR_P26 (0x1u << 26) /**< \brief (PIO_OWSR) Output Write Status. */ |
| 2938 | #define PIO_OWSR_P27 (0x1u << 27) /**< \brief (PIO_OWSR) Output Write Status. */ |
| 2939 | #define PIO_OWSR_P28 (0x1u << 28) /**< \brief (PIO_OWSR) Output Write Status. */ |
| 2940 | #define PIO_OWSR_P29 (0x1u << 29) /**< \brief (PIO_OWSR) Output Write Status. */ |
| 2941 | #define PIO_OWSR_P30 (0x1u << 30) /**< \brief (PIO_OWSR) Output Write Status. */ |
| 2942 | #define PIO_OWSR_P31 (0x1u << 31) /**< \brief (PIO_OWSR) Output Write Status. */ |
| 2943 | /* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */ |
| 2944 | #define PIO_AIMER_P0 (0x1u << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| 2945 | #define PIO_AIMER_P1 (0x1u << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| 2946 | #define PIO_AIMER_P2 (0x1u << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| 2947 | #define PIO_AIMER_P3 (0x1u << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| 2948 | #define PIO_AIMER_P4 (0x1u << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| 2949 | #define PIO_AIMER_P5 (0x1u << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| 2950 | #define PIO_AIMER_P6 (0x1u << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| 2951 | #define PIO_AIMER_P7 (0x1u << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| 2952 | #define PIO_AIMER_P8 (0x1u << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| 2953 | #define PIO_AIMER_P9 (0x1u << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| 2954 | #define PIO_AIMER_P10 (0x1u << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| 2955 | #define PIO_AIMER_P11 (0x1u << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| 2956 | #define PIO_AIMER_P12 (0x1u << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| 2957 | #define PIO_AIMER_P13 (0x1u << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| 2958 | #define PIO_AIMER_P14 (0x1u << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| 2959 | #define PIO_AIMER_P15 (0x1u << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| 2960 | #define PIO_AIMER_P16 (0x1u << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| 2961 | #define PIO_AIMER_P17 (0x1u << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| 2962 | #define PIO_AIMER_P18 (0x1u << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| 2963 | #define PIO_AIMER_P19 (0x1u << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| 2964 | #define PIO_AIMER_P20 (0x1u << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| 2965 | #define PIO_AIMER_P21 (0x1u << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| 2966 | #define PIO_AIMER_P22 (0x1u << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| 2967 | #define PIO_AIMER_P23 (0x1u << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| 2968 | #define PIO_AIMER_P24 (0x1u << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| 2969 | #define PIO_AIMER_P25 (0x1u << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| 2970 | #define PIO_AIMER_P26 (0x1u << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| 2971 | #define PIO_AIMER_P27 (0x1u << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| 2972 | #define PIO_AIMER_P28 (0x1u << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| 2973 | #define PIO_AIMER_P29 (0x1u << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| 2974 | #define PIO_AIMER_P30 (0x1u << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| 2975 | #define PIO_AIMER_P31 (0x1u << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| 2976 | /* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disables Register -------- */ |
| 2977 | #define PIO_AIMDR_P0 (0x1u << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| 2978 | #define PIO_AIMDR_P1 (0x1u << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| 2979 | #define PIO_AIMDR_P2 (0x1u << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| 2980 | #define PIO_AIMDR_P3 (0x1u << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| 2981 | #define PIO_AIMDR_P4 (0x1u << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| 2982 | #define PIO_AIMDR_P5 (0x1u << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| 2983 | #define PIO_AIMDR_P6 (0x1u << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| 2984 | #define PIO_AIMDR_P7 (0x1u << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| 2985 | #define PIO_AIMDR_P8 (0x1u << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| 2986 | #define PIO_AIMDR_P9 (0x1u << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| 2987 | #define PIO_AIMDR_P10 (0x1u << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| 2988 | #define PIO_AIMDR_P11 (0x1u << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| 2989 | #define PIO_AIMDR_P12 (0x1u << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| 2990 | #define PIO_AIMDR_P13 (0x1u << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| 2991 | #define PIO_AIMDR_P14 (0x1u << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| 2992 | #define PIO_AIMDR_P15 (0x1u << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| 2993 | #define PIO_AIMDR_P16 (0x1u << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| 2994 | #define PIO_AIMDR_P17 (0x1u << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| 2995 | #define PIO_AIMDR_P18 (0x1u << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| 2996 | #define PIO_AIMDR_P19 (0x1u << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| 2997 | #define PIO_AIMDR_P20 (0x1u << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| 2998 | #define PIO_AIMDR_P21 (0x1u << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| 2999 | #define PIO_AIMDR_P22 (0x1u << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| 3000 | #define PIO_AIMDR_P23 (0x1u << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| 3001 | #define PIO_AIMDR_P24 (0x1u << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| 3002 | #define PIO_AIMDR_P25 (0x1u << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| 3003 | #define PIO_AIMDR_P26 (0x1u << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| 3004 | #define PIO_AIMDR_P27 (0x1u << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| 3005 | #define PIO_AIMDR_P28 (0x1u << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| 3006 | #define PIO_AIMDR_P29 (0x1u << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| 3007 | #define PIO_AIMDR_P30 (0x1u << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| 3008 | #define PIO_AIMDR_P31 (0x1u << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| 3009 | /* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */ |
| 3010 | #define PIO_AIMMR_P0 (0x1u << 0) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| 3011 | #define PIO_AIMMR_P1 (0x1u << 1) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| 3012 | #define PIO_AIMMR_P2 (0x1u << 2) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| 3013 | #define PIO_AIMMR_P3 (0x1u << 3) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| 3014 | #define PIO_AIMMR_P4 (0x1u << 4) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| 3015 | #define PIO_AIMMR_P5 (0x1u << 5) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| 3016 | #define PIO_AIMMR_P6 (0x1u << 6) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| 3017 | #define PIO_AIMMR_P7 (0x1u << 7) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| 3018 | #define PIO_AIMMR_P8 (0x1u << 8) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| 3019 | #define PIO_AIMMR_P9 (0x1u << 9) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| 3020 | #define PIO_AIMMR_P10 (0x1u << 10) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| 3021 | #define PIO_AIMMR_P11 (0x1u << 11) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| 3022 | #define PIO_AIMMR_P12 (0x1u << 12) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| 3023 | #define PIO_AIMMR_P13 (0x1u << 13) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| 3024 | #define PIO_AIMMR_P14 (0x1u << 14) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| 3025 | #define PIO_AIMMR_P15 (0x1u << 15) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| 3026 | #define PIO_AIMMR_P16 (0x1u << 16) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| 3027 | #define PIO_AIMMR_P17 (0x1u << 17) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| 3028 | #define PIO_AIMMR_P18 (0x1u << 18) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| 3029 | #define PIO_AIMMR_P19 (0x1u << 19) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| 3030 | #define PIO_AIMMR_P20 (0x1u << 20) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| 3031 | #define PIO_AIMMR_P21 (0x1u << 21) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| 3032 | #define PIO_AIMMR_P22 (0x1u << 22) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| 3033 | #define PIO_AIMMR_P23 (0x1u << 23) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| 3034 | #define PIO_AIMMR_P24 (0x1u << 24) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| 3035 | #define PIO_AIMMR_P25 (0x1u << 25) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| 3036 | #define PIO_AIMMR_P26 (0x1u << 26) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| 3037 | #define PIO_AIMMR_P27 (0x1u << 27) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| 3038 | #define PIO_AIMMR_P28 (0x1u << 28) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| 3039 | #define PIO_AIMMR_P29 (0x1u << 29) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| 3040 | #define PIO_AIMMR_P30 (0x1u << 30) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| 3041 | #define PIO_AIMMR_P31 (0x1u << 31) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| 3042 | /* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */ |
| 3043 | #define PIO_ESR_P0 (0x1u << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| 3044 | #define PIO_ESR_P1 (0x1u << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| 3045 | #define PIO_ESR_P2 (0x1u << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| 3046 | #define PIO_ESR_P3 (0x1u << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| 3047 | #define PIO_ESR_P4 (0x1u << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| 3048 | #define PIO_ESR_P5 (0x1u << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| 3049 | #define PIO_ESR_P6 (0x1u << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| 3050 | #define PIO_ESR_P7 (0x1u << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| 3051 | #define PIO_ESR_P8 (0x1u << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| 3052 | #define PIO_ESR_P9 (0x1u << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| 3053 | #define PIO_ESR_P10 (0x1u << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| 3054 | #define PIO_ESR_P11 (0x1u << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| 3055 | #define PIO_ESR_P12 (0x1u << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| 3056 | #define PIO_ESR_P13 (0x1u << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| 3057 | #define PIO_ESR_P14 (0x1u << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| 3058 | #define PIO_ESR_P15 (0x1u << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| 3059 | #define PIO_ESR_P16 (0x1u << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| 3060 | #define PIO_ESR_P17 (0x1u << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| 3061 | #define PIO_ESR_P18 (0x1u << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| 3062 | #define PIO_ESR_P19 (0x1u << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| 3063 | #define PIO_ESR_P20 (0x1u << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| 3064 | #define PIO_ESR_P21 (0x1u << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| 3065 | #define PIO_ESR_P22 (0x1u << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| 3066 | #define PIO_ESR_P23 (0x1u << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| 3067 | #define PIO_ESR_P24 (0x1u << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| 3068 | #define PIO_ESR_P25 (0x1u << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| 3069 | #define PIO_ESR_P26 (0x1u << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| 3070 | #define PIO_ESR_P27 (0x1u << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| 3071 | #define PIO_ESR_P28 (0x1u << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| 3072 | #define PIO_ESR_P29 (0x1u << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| 3073 | #define PIO_ESR_P30 (0x1u << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| 3074 | #define PIO_ESR_P31 (0x1u << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| 3075 | /* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */ |
| 3076 | #define PIO_LSR_P0 (0x1u << 0) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| 3077 | #define PIO_LSR_P1 (0x1u << 1) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| 3078 | #define PIO_LSR_P2 (0x1u << 2) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| 3079 | #define PIO_LSR_P3 (0x1u << 3) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| 3080 | #define PIO_LSR_P4 (0x1u << 4) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| 3081 | #define PIO_LSR_P5 (0x1u << 5) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| 3082 | #define PIO_LSR_P6 (0x1u << 6) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| 3083 | #define PIO_LSR_P7 (0x1u << 7) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| 3084 | #define PIO_LSR_P8 (0x1u << 8) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| 3085 | #define PIO_LSR_P9 (0x1u << 9) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| 3086 | #define PIO_LSR_P10 (0x1u << 10) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| 3087 | #define PIO_LSR_P11 (0x1u << 11) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| 3088 | #define PIO_LSR_P12 (0x1u << 12) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| 3089 | #define PIO_LSR_P13 (0x1u << 13) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| 3090 | #define PIO_LSR_P14 (0x1u << 14) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| 3091 | #define PIO_LSR_P15 (0x1u << 15) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| 3092 | #define PIO_LSR_P16 (0x1u << 16) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| 3093 | #define PIO_LSR_P17 (0x1u << 17) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| 3094 | #define PIO_LSR_P18 (0x1u << 18) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| 3095 | #define PIO_LSR_P19 (0x1u << 19) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| 3096 | #define PIO_LSR_P20 (0x1u << 20) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| 3097 | #define PIO_LSR_P21 (0x1u << 21) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| 3098 | #define PIO_LSR_P22 (0x1u << 22) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| 3099 | #define PIO_LSR_P23 (0x1u << 23) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| 3100 | #define PIO_LSR_P24 (0x1u << 24) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| 3101 | #define PIO_LSR_P25 (0x1u << 25) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| 3102 | #define PIO_LSR_P26 (0x1u << 26) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| 3103 | #define PIO_LSR_P27 (0x1u << 27) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| 3104 | #define PIO_LSR_P28 (0x1u << 28) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| 3105 | #define PIO_LSR_P29 (0x1u << 29) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| 3106 | #define PIO_LSR_P30 (0x1u << 30) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| 3107 | #define PIO_LSR_P31 (0x1u << 31) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| 3108 | /* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */ |
| 3109 | #define PIO_ELSR_P0 (0x1u << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| 3110 | #define PIO_ELSR_P1 (0x1u << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| 3111 | #define PIO_ELSR_P2 (0x1u << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| 3112 | #define PIO_ELSR_P3 (0x1u << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| 3113 | #define PIO_ELSR_P4 (0x1u << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| 3114 | #define PIO_ELSR_P5 (0x1u << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| 3115 | #define PIO_ELSR_P6 (0x1u << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| 3116 | #define PIO_ELSR_P7 (0x1u << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| 3117 | #define PIO_ELSR_P8 (0x1u << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| 3118 | #define PIO_ELSR_P9 (0x1u << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| 3119 | #define PIO_ELSR_P10 (0x1u << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| 3120 | #define PIO_ELSR_P11 (0x1u << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| 3121 | #define PIO_ELSR_P12 (0x1u << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| 3122 | #define PIO_ELSR_P13 (0x1u << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| 3123 | #define PIO_ELSR_P14 (0x1u << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| 3124 | #define PIO_ELSR_P15 (0x1u << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| 3125 | #define PIO_ELSR_P16 (0x1u << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| 3126 | #define PIO_ELSR_P17 (0x1u << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| 3127 | #define PIO_ELSR_P18 (0x1u << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| 3128 | #define PIO_ELSR_P19 (0x1u << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| 3129 | #define PIO_ELSR_P20 (0x1u << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| 3130 | #define PIO_ELSR_P21 (0x1u << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| 3131 | #define PIO_ELSR_P22 (0x1u << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| 3132 | #define PIO_ELSR_P23 (0x1u << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| 3133 | #define PIO_ELSR_P24 (0x1u << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| 3134 | #define PIO_ELSR_P25 (0x1u << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| 3135 | #define PIO_ELSR_P26 (0x1u << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| 3136 | #define PIO_ELSR_P27 (0x1u << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| 3137 | #define PIO_ELSR_P28 (0x1u << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| 3138 | #define PIO_ELSR_P29 (0x1u << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| 3139 | #define PIO_ELSR_P30 (0x1u << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| 3140 | #define PIO_ELSR_P31 (0x1u << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| 3141 | /* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low Level Select Register -------- */ |
| 3142 | #define PIO_FELLSR_P0 (0x1u << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| 3143 | #define PIO_FELLSR_P1 (0x1u << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| 3144 | #define PIO_FELLSR_P2 (0x1u << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| 3145 | #define PIO_FELLSR_P3 (0x1u << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| 3146 | #define PIO_FELLSR_P4 (0x1u << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| 3147 | #define PIO_FELLSR_P5 (0x1u << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| 3148 | #define PIO_FELLSR_P6 (0x1u << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| 3149 | #define PIO_FELLSR_P7 (0x1u << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| 3150 | #define PIO_FELLSR_P8 (0x1u << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| 3151 | #define PIO_FELLSR_P9 (0x1u << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| 3152 | #define PIO_FELLSR_P10 (0x1u << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| 3153 | #define PIO_FELLSR_P11 (0x1u << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| 3154 | #define PIO_FELLSR_P12 (0x1u << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| 3155 | #define PIO_FELLSR_P13 (0x1u << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| 3156 | #define PIO_FELLSR_P14 (0x1u << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| 3157 | #define PIO_FELLSR_P15 (0x1u << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| 3158 | #define PIO_FELLSR_P16 (0x1u << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| 3159 | #define PIO_FELLSR_P17 (0x1u << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| 3160 | #define PIO_FELLSR_P18 (0x1u << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| 3161 | #define PIO_FELLSR_P19 (0x1u << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| 3162 | #define PIO_FELLSR_P20 (0x1u << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| 3163 | #define PIO_FELLSR_P21 (0x1u << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| 3164 | #define PIO_FELLSR_P22 (0x1u << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| 3165 | #define PIO_FELLSR_P23 (0x1u << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| 3166 | #define PIO_FELLSR_P24 (0x1u << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| 3167 | #define PIO_FELLSR_P25 (0x1u << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| 3168 | #define PIO_FELLSR_P26 (0x1u << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| 3169 | #define PIO_FELLSR_P27 (0x1u << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| 3170 | #define PIO_FELLSR_P28 (0x1u << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| 3171 | #define PIO_FELLSR_P29 (0x1u << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| 3172 | #define PIO_FELLSR_P30 (0x1u << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| 3173 | #define PIO_FELLSR_P31 (0x1u << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| 3174 | /* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/ High Level Select Register -------- */ |
| 3175 | #define PIO_REHLSR_P0 (0x1u << 0) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| 3176 | #define PIO_REHLSR_P1 (0x1u << 1) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| 3177 | #define PIO_REHLSR_P2 (0x1u << 2) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| 3178 | #define PIO_REHLSR_P3 (0x1u << 3) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| 3179 | #define PIO_REHLSR_P4 (0x1u << 4) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| 3180 | #define PIO_REHLSR_P5 (0x1u << 5) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| 3181 | #define PIO_REHLSR_P6 (0x1u << 6) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| 3182 | #define PIO_REHLSR_P7 (0x1u << 7) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| 3183 | #define PIO_REHLSR_P8 (0x1u << 8) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| 3184 | #define PIO_REHLSR_P9 (0x1u << 9) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| 3185 | #define PIO_REHLSR_P10 (0x1u << 10) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| 3186 | #define PIO_REHLSR_P11 (0x1u << 11) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| 3187 | #define PIO_REHLSR_P12 (0x1u << 12) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| 3188 | #define PIO_REHLSR_P13 (0x1u << 13) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| 3189 | #define PIO_REHLSR_P14 (0x1u << 14) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| 3190 | #define PIO_REHLSR_P15 (0x1u << 15) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| 3191 | #define PIO_REHLSR_P16 (0x1u << 16) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| 3192 | #define PIO_REHLSR_P17 (0x1u << 17) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| 3193 | #define PIO_REHLSR_P18 (0x1u << 18) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| 3194 | #define PIO_REHLSR_P19 (0x1u << 19) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| 3195 | #define PIO_REHLSR_P20 (0x1u << 20) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| 3196 | #define PIO_REHLSR_P21 (0x1u << 21) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| 3197 | #define PIO_REHLSR_P22 (0x1u << 22) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| 3198 | #define PIO_REHLSR_P23 (0x1u << 23) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| 3199 | #define PIO_REHLSR_P24 (0x1u << 24) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| 3200 | #define PIO_REHLSR_P25 (0x1u << 25) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| 3201 | #define PIO_REHLSR_P26 (0x1u << 26) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| 3202 | #define PIO_REHLSR_P27 (0x1u << 27) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| 3203 | #define PIO_REHLSR_P28 (0x1u << 28) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| 3204 | #define PIO_REHLSR_P29 (0x1u << 29) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| 3205 | #define PIO_REHLSR_P30 (0x1u << 30) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| 3206 | #define PIO_REHLSR_P31 (0x1u << 31) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| 3207 | /* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */ |
| 3208 | #define PIO_FRLHSR_P0 (0x1u << 0) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| 3209 | #define PIO_FRLHSR_P1 (0x1u << 1) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| 3210 | #define PIO_FRLHSR_P2 (0x1u << 2) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| 3211 | #define PIO_FRLHSR_P3 (0x1u << 3) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| 3212 | #define PIO_FRLHSR_P4 (0x1u << 4) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| 3213 | #define PIO_FRLHSR_P5 (0x1u << 5) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| 3214 | #define PIO_FRLHSR_P6 (0x1u << 6) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| 3215 | #define PIO_FRLHSR_P7 (0x1u << 7) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| 3216 | #define PIO_FRLHSR_P8 (0x1u << 8) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| 3217 | #define PIO_FRLHSR_P9 (0x1u << 9) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| 3218 | #define PIO_FRLHSR_P10 (0x1u << 10) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| 3219 | #define PIO_FRLHSR_P11 (0x1u << 11) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| 3220 | #define PIO_FRLHSR_P12 (0x1u << 12) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| 3221 | #define PIO_FRLHSR_P13 (0x1u << 13) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| 3222 | #define PIO_FRLHSR_P14 (0x1u << 14) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| 3223 | #define PIO_FRLHSR_P15 (0x1u << 15) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| 3224 | #define PIO_FRLHSR_P16 (0x1u << 16) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| 3225 | #define PIO_FRLHSR_P17 (0x1u << 17) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| 3226 | #define PIO_FRLHSR_P18 (0x1u << 18) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| 3227 | #define PIO_FRLHSR_P19 (0x1u << 19) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| 3228 | #define PIO_FRLHSR_P20 (0x1u << 20) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| 3229 | #define PIO_FRLHSR_P21 (0x1u << 21) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| 3230 | #define PIO_FRLHSR_P22 (0x1u << 22) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| 3231 | #define PIO_FRLHSR_P23 (0x1u << 23) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| 3232 | #define PIO_FRLHSR_P24 (0x1u << 24) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| 3233 | #define PIO_FRLHSR_P25 (0x1u << 25) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| 3234 | #define PIO_FRLHSR_P26 (0x1u << 26) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| 3235 | #define PIO_FRLHSR_P27 (0x1u << 27) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| 3236 | #define PIO_FRLHSR_P28 (0x1u << 28) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| 3237 | #define PIO_FRLHSR_P29 (0x1u << 29) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| 3238 | #define PIO_FRLHSR_P30 (0x1u << 30) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| 3239 | #define PIO_FRLHSR_P31 (0x1u << 31) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| 3240 | /* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */ |
| 3241 | #define PIO_LOCKSR_P0 (0x1u << 0) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| 3242 | #define PIO_LOCKSR_P1 (0x1u << 1) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| 3243 | #define PIO_LOCKSR_P2 (0x1u << 2) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| 3244 | #define PIO_LOCKSR_P3 (0x1u << 3) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| 3245 | #define PIO_LOCKSR_P4 (0x1u << 4) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| 3246 | #define PIO_LOCKSR_P5 (0x1u << 5) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| 3247 | #define PIO_LOCKSR_P6 (0x1u << 6) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| 3248 | #define PIO_LOCKSR_P7 (0x1u << 7) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| 3249 | #define PIO_LOCKSR_P8 (0x1u << 8) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| 3250 | #define PIO_LOCKSR_P9 (0x1u << 9) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| 3251 | #define PIO_LOCKSR_P10 (0x1u << 10) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| 3252 | #define PIO_LOCKSR_P11 (0x1u << 11) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| 3253 | #define PIO_LOCKSR_P12 (0x1u << 12) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| 3254 | #define PIO_LOCKSR_P13 (0x1u << 13) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| 3255 | #define PIO_LOCKSR_P14 (0x1u << 14) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| 3256 | #define PIO_LOCKSR_P15 (0x1u << 15) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| 3257 | #define PIO_LOCKSR_P16 (0x1u << 16) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| 3258 | #define PIO_LOCKSR_P17 (0x1u << 17) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| 3259 | #define PIO_LOCKSR_P18 (0x1u << 18) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| 3260 | #define PIO_LOCKSR_P19 (0x1u << 19) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| 3261 | #define PIO_LOCKSR_P20 (0x1u << 20) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| 3262 | #define PIO_LOCKSR_P21 (0x1u << 21) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| 3263 | #define PIO_LOCKSR_P22 (0x1u << 22) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| 3264 | #define PIO_LOCKSR_P23 (0x1u << 23) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| 3265 | #define PIO_LOCKSR_P24 (0x1u << 24) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| 3266 | #define PIO_LOCKSR_P25 (0x1u << 25) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| 3267 | #define PIO_LOCKSR_P26 (0x1u << 26) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| 3268 | #define PIO_LOCKSR_P27 (0x1u << 27) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| 3269 | #define PIO_LOCKSR_P28 (0x1u << 28) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| 3270 | #define PIO_LOCKSR_P29 (0x1u << 29) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| 3271 | #define PIO_LOCKSR_P30 (0x1u << 30) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| 3272 | #define PIO_LOCKSR_P31 (0x1u << 31) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| 3273 | /* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protect Mode Register -------- */ |
| 3274 | #define PIO_WPMR_WPEN (0x1u << 0) /**< \brief (PIO_WPMR) Write Protect Enable */ |
| 3275 | #define PIO_WPMR_WPKEY_Pos 8 |
| 3276 | #define PIO_WPMR_WPKEY_Msk (0xffffffu << PIO_WPMR_WPKEY_Pos) /**< \brief (PIO_WPMR) Write Protect KEY */ |
| 3277 | #define PIO_WPMR_WPKEY(value) ((PIO_WPMR_WPKEY_Msk & ((value) << PIO_WPMR_WPKEY_Pos))) |
| 3278 | /* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protect Status Register -------- */ |
| 3279 | #define PIO_WPSR_WPVS (0x1u << 0) /**< \brief (PIO_WPSR) Write Protect Violation Status */ |
| 3280 | #define PIO_WPSR_WPVSRC_Pos 8 |
| 3281 | #define PIO_WPSR_WPVSRC_Msk (0xffffu << PIO_WPSR_WPVSRC_Pos) /**< \brief (PIO_WPSR) Write Protect Violation Source */ |
| 3282 | /* -------- PIO_SCHMITT : (PIO Offset: 0x0100) Schmitt Trigger Register -------- */ |
| 3283 | #define PIO_SCHMITT_SCHMITT0 (0x1u << 0) /**< \brief (PIO_SCHMITT) */ |
| 3284 | #define PIO_SCHMITT_SCHMITT1 (0x1u << 1) /**< \brief (PIO_SCHMITT) */ |
| 3285 | #define PIO_SCHMITT_SCHMITT2 (0x1u << 2) /**< \brief (PIO_SCHMITT) */ |
| 3286 | #define PIO_SCHMITT_SCHMITT3 (0x1u << 3) /**< \brief (PIO_SCHMITT) */ |
| 3287 | #define PIO_SCHMITT_SCHMITT4 (0x1u << 4) /**< \brief (PIO_SCHMITT) */ |
| 3288 | #define PIO_SCHMITT_SCHMITT5 (0x1u << 5) /**< \brief (PIO_SCHMITT) */ |
| 3289 | #define PIO_SCHMITT_SCHMITT6 (0x1u << 6) /**< \brief (PIO_SCHMITT) */ |
| 3290 | #define PIO_SCHMITT_SCHMITT7 (0x1u << 7) /**< \brief (PIO_SCHMITT) */ |
| 3291 | #define PIO_SCHMITT_SCHMITT8 (0x1u << 8) /**< \brief (PIO_SCHMITT) */ |
| 3292 | #define PIO_SCHMITT_SCHMITT9 (0x1u << 9) /**< \brief (PIO_SCHMITT) */ |
| 3293 | #define PIO_SCHMITT_SCHMITT10 (0x1u << 10) /**< \brief (PIO_SCHMITT) */ |
| 3294 | #define PIO_SCHMITT_SCHMITT11 (0x1u << 11) /**< \brief (PIO_SCHMITT) */ |
| 3295 | #define PIO_SCHMITT_SCHMITT12 (0x1u << 12) /**< \brief (PIO_SCHMITT) */ |
| 3296 | #define PIO_SCHMITT_SCHMITT13 (0x1u << 13) /**< \brief (PIO_SCHMITT) */ |
| 3297 | #define PIO_SCHMITT_SCHMITT14 (0x1u << 14) /**< \brief (PIO_SCHMITT) */ |
| 3298 | #define PIO_SCHMITT_SCHMITT15 (0x1u << 15) /**< \brief (PIO_SCHMITT) */ |
| 3299 | #define PIO_SCHMITT_SCHMITT16 (0x1u << 16) /**< \brief (PIO_SCHMITT) */ |
| 3300 | #define PIO_SCHMITT_SCHMITT17 (0x1u << 17) /**< \brief (PIO_SCHMITT) */ |
| 3301 | #define PIO_SCHMITT_SCHMITT18 (0x1u << 18) /**< \brief (PIO_SCHMITT) */ |
| 3302 | #define PIO_SCHMITT_SCHMITT19 (0x1u << 19) /**< \brief (PIO_SCHMITT) */ |
| 3303 | #define PIO_SCHMITT_SCHMITT20 (0x1u << 20) /**< \brief (PIO_SCHMITT) */ |
| 3304 | #define PIO_SCHMITT_SCHMITT21 (0x1u << 21) /**< \brief (PIO_SCHMITT) */ |
| 3305 | #define PIO_SCHMITT_SCHMITT22 (0x1u << 22) /**< \brief (PIO_SCHMITT) */ |
| 3306 | #define PIO_SCHMITT_SCHMITT23 (0x1u << 23) /**< \brief (PIO_SCHMITT) */ |
| 3307 | #define PIO_SCHMITT_SCHMITT24 (0x1u << 24) /**< \brief (PIO_SCHMITT) */ |
| 3308 | #define PIO_SCHMITT_SCHMITT25 (0x1u << 25) /**< \brief (PIO_SCHMITT) */ |
| 3309 | #define PIO_SCHMITT_SCHMITT26 (0x1u << 26) /**< \brief (PIO_SCHMITT) */ |
| 3310 | #define PIO_SCHMITT_SCHMITT27 (0x1u << 27) /**< \brief (PIO_SCHMITT) */ |
| 3311 | #define PIO_SCHMITT_SCHMITT28 (0x1u << 28) /**< \brief (PIO_SCHMITT) */ |
| 3312 | #define PIO_SCHMITT_SCHMITT29 (0x1u << 29) /**< \brief (PIO_SCHMITT) */ |
| 3313 | #define PIO_SCHMITT_SCHMITT30 (0x1u << 30) /**< \brief (PIO_SCHMITT) */ |
| 3314 | #define PIO_SCHMITT_SCHMITT31 (0x1u << 31) /**< \brief (PIO_SCHMITT) */ |
| 3315 | /* -------- PIO_PCMR : (PIO Offset: 0x150) Parallel Capture Mode Register -------- */ |
| 3316 | #define PIO_PCMR_PCEN (0x1u << 0) /**< \brief (PIO_PCMR) Parallel Capture Mode Enable */ |
| 3317 | #define PIO_PCMR_DSIZE_Pos 4 |
| 3318 | #define PIO_PCMR_DSIZE_Msk (0x3u << PIO_PCMR_DSIZE_Pos) /**< \brief (PIO_PCMR) Parallel Capture Mode Data Size */ |
| 3319 | #define PIO_PCMR_DSIZE(value) ((PIO_PCMR_DSIZE_Msk & ((value) << PIO_PCMR_DSIZE_Pos))) |
| 3320 | #define PIO_PCMR_ALWYS (0x1u << 9) /**< \brief (PIO_PCMR) Parallel Capture Mode Always Sampling */ |
| 3321 | #define PIO_PCMR_HALFS (0x1u << 10) /**< \brief (PIO_PCMR) Parallel Capture Mode Half Sampling */ |
| 3322 | #define PIO_PCMR_FRSTS (0x1u << 11) /**< \brief (PIO_PCMR) Parallel Capture Mode First Sample */ |
| 3323 | /* -------- PIO_PCIER : (PIO Offset: 0x154) Parallel Capture Interrupt Enable Register -------- */ |
| 3324 | #define PIO_PCIER_DRDY (0x1u << 0) /**< \brief (PIO_PCIER) Parallel Capture Mode Data Ready Interrupt Enable */ |
| 3325 | #define PIO_PCIER_OVRE (0x1u << 1) /**< \brief (PIO_PCIER) Parallel Capture Mode Overrun Error Interrupt Enable */ |
| 3326 | #define PIO_PCIER_ENDRX (0x1u << 2) /**< \brief (PIO_PCIER) End of Reception Transfer Interrupt Enable */ |
| 3327 | #define PIO_PCIER_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIER) Reception Buffer Full Interrupt Enable */ |
| 3328 | /* -------- PIO_PCIDR : (PIO Offset: 0x158) Parallel Capture Interrupt Disable Register -------- */ |
| 3329 | #define PIO_PCIDR_DRDY (0x1u << 0) /**< \brief (PIO_PCIDR) Parallel Capture Mode Data Ready Interrupt Disable */ |
| 3330 | #define PIO_PCIDR_OVRE (0x1u << 1) /**< \brief (PIO_PCIDR) Parallel Capture Mode Overrun Error Interrupt Disable */ |
| 3331 | #define PIO_PCIDR_ENDRX (0x1u << 2) /**< \brief (PIO_PCIDR) End of Reception Transfer Interrupt Disable */ |
| 3332 | #define PIO_PCIDR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIDR) Reception Buffer Full Interrupt Disable */ |
| 3333 | /* -------- PIO_PCIMR : (PIO Offset: 0x15C) Parallel Capture Interrupt Mask Register -------- */ |
| 3334 | #define PIO_PCIMR_DRDY (0x1u << 0) /**< \brief (PIO_PCIMR) Parallel Capture Mode Data Ready Interrupt Mask */ |
| 3335 | #define PIO_PCIMR_OVRE (0x1u << 1) /**< \brief (PIO_PCIMR) Parallel Capture Mode Overrun Error Interrupt Mask */ |
| 3336 | #define PIO_PCIMR_ENDRX (0x1u << 2) /**< \brief (PIO_PCIMR) End of Reception Transfer Interrupt Mask */ |
| 3337 | #define PIO_PCIMR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIMR) Reception Buffer Full Interrupt Mask */ |
| 3338 | /* -------- PIO_PCISR : (PIO Offset: 0x160) Parallel Capture Interrupt Status Register -------- */ |
| 3339 | #define PIO_PCISR_DRDY (0x1u << 0) /**< \brief (PIO_PCISR) Parallel Capture Mode Data Ready */ |
| 3340 | #define PIO_PCISR_OVRE (0x1u << 1) /**< \brief (PIO_PCISR) Parallel Capture Mode Overrun Error. */ |
| 3341 | #define PIO_PCISR_ENDRX (0x1u << 2) /**< \brief (PIO_PCISR) End of Reception Transfer. */ |
| 3342 | #define PIO_PCISR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCISR) Reception Buffer Full */ |
| 3343 | /* -------- PIO_PCRHR : (PIO Offset: 0x164) Parallel Capture Reception Holding Register -------- */ |
| 3344 | #define PIO_PCRHR_RDATA_Pos 0 |
| 3345 | #define PIO_PCRHR_RDATA_Msk (0xffffffffu << PIO_PCRHR_RDATA_Pos) /**< \brief (PIO_PCRHR) Parallel Capture Mode Reception Data. */ |
| 3346 | /* -------- PIO_RPR : (PIO Offset: 0x168) Receive Pointer Register -------- */ |
| 3347 | #define PIO_RPR_RXPTR_Pos 0 |
| 3348 | #define PIO_RPR_RXPTR_Msk (0xffffffffu << PIO_RPR_RXPTR_Pos) /**< \brief (PIO_RPR) Receive Pointer Register */ |
| 3349 | #define PIO_RPR_RXPTR(value) ((PIO_RPR_RXPTR_Msk & ((value) << PIO_RPR_RXPTR_Pos))) |
| 3350 | /* -------- PIO_RCR : (PIO Offset: 0x16C) Receive Counter Register -------- */ |
| 3351 | #define PIO_RCR_RXCTR_Pos 0 |
| 3352 | #define PIO_RCR_RXCTR_Msk (0xffffu << PIO_RCR_RXCTR_Pos) /**< \brief (PIO_RCR) Receive Counter Register */ |
| 3353 | #define PIO_RCR_RXCTR(value) ((PIO_RCR_RXCTR_Msk & ((value) << PIO_RCR_RXCTR_Pos))) |
| 3354 | /* -------- PIO_TPR : (PIO Offset: 0x170) Transmit Pointer Register -------- */ |
| 3355 | #define PIO_TPR_TXPTR_Pos 0 |
| 3356 | #define PIO_TPR_TXPTR_Msk (0xffffffffu << PIO_TPR_TXPTR_Pos) /**< \brief (PIO_TPR) Transmit Counter Register */ |
| 3357 | #define PIO_TPR_TXPTR(value) ((PIO_TPR_TXPTR_Msk & ((value) << PIO_TPR_TXPTR_Pos))) |
| 3358 | /* -------- PIO_TCR : (PIO Offset: 0x174) Transmit Counter Register -------- */ |
| 3359 | #define PIO_TCR_TXCTR_Pos 0 |
| 3360 | #define PIO_TCR_TXCTR_Msk (0xffffu << PIO_TCR_TXCTR_Pos) /**< \brief (PIO_TCR) Transmit Counter Register */ |
| 3361 | #define PIO_TCR_TXCTR(value) ((PIO_TCR_TXCTR_Msk & ((value) << PIO_TCR_TXCTR_Pos))) |
| 3362 | /* -------- PIO_RNPR : (PIO Offset: 0x178) Receive Next Pointer Register -------- */ |
| 3363 | #define PIO_RNPR_RXNPTR_Pos 0 |
| 3364 | #define PIO_RNPR_RXNPTR_Msk (0xffffffffu << PIO_RNPR_RXNPTR_Pos) /**< \brief (PIO_RNPR) Receive Next Pointer */ |
| 3365 | #define PIO_RNPR_RXNPTR(value) ((PIO_RNPR_RXNPTR_Msk & ((value) << PIO_RNPR_RXNPTR_Pos))) |
| 3366 | /* -------- PIO_RNCR : (PIO Offset: 0x17C) Receive Next Counter Register -------- */ |
| 3367 | #define PIO_RNCR_RXNCTR_Pos 0 |
| 3368 | #define PIO_RNCR_RXNCTR_Msk (0xffffu << PIO_RNCR_RXNCTR_Pos) /**< \brief (PIO_RNCR) Receive Next Counter */ |
| 3369 | #define PIO_RNCR_RXNCTR(value) ((PIO_RNCR_RXNCTR_Msk & ((value) << PIO_RNCR_RXNCTR_Pos))) |
| 3370 | /* -------- PIO_TNPR : (PIO Offset: 0x180) Transmit Next Pointer Register -------- */ |
| 3371 | #define PIO_TNPR_TXNPTR_Pos 0 |
| 3372 | #define PIO_TNPR_TXNPTR_Msk (0xffffffffu << PIO_TNPR_TXNPTR_Pos) /**< \brief (PIO_TNPR) Transmit Next Pointer */ |
| 3373 | #define PIO_TNPR_TXNPTR(value) ((PIO_TNPR_TXNPTR_Msk & ((value) << PIO_TNPR_TXNPTR_Pos))) |
| 3374 | /* -------- PIO_TNCR : (PIO Offset: 0x184) Transmit Next Counter Register -------- */ |
| 3375 | #define PIO_TNCR_TXNCTR_Pos 0 |
| 3376 | #define PIO_TNCR_TXNCTR_Msk (0xffffu << PIO_TNCR_TXNCTR_Pos) /**< \brief (PIO_TNCR) Transmit Counter Next */ |
| 3377 | #define PIO_TNCR_TXNCTR(value) ((PIO_TNCR_TXNCTR_Msk & ((value) << PIO_TNCR_TXNCTR_Pos))) |
| 3378 | /* -------- PIO_PTCR : (PIO Offset: 0x188) Transfer Control Register -------- */ |
| 3379 | #define PIO_PTCR_RXTEN (0x1u << 0) /**< \brief (PIO_PTCR) Receiver Transfer Enable */ |
| 3380 | #define PIO_PTCR_RXTDIS (0x1u << 1) /**< \brief (PIO_PTCR) Receiver Transfer Disable */ |
| 3381 | #define PIO_PTCR_TXTEN (0x1u << 8) /**< \brief (PIO_PTCR) Transmitter Transfer Enable */ |
| 3382 | #define PIO_PTCR_TXTDIS (0x1u << 9) /**< \brief (PIO_PTCR) Transmitter Transfer Disable */ |
| 3383 | /* -------- PIO_PTSR : (PIO Offset: 0x18C) Transfer Status Register -------- */ |
| 3384 | #define PIO_PTSR_RXTEN (0x1u << 0) /**< \brief (PIO_PTSR) Receiver Transfer Enable */ |
| 3385 | #define PIO_PTSR_TXTEN (0x1u << 8) /**< \brief (PIO_PTSR) Transmitter Transfer Enable */ |
| 3386 | |
| 3387 | /*@}*/ |
| 3388 | |
| 3389 | /* ============================================================================= */ |
| 3390 | /** SOFTWARE API DEFINITION FOR Power Management Controller */ |
| 3391 | /* ============================================================================= */ |
| 3392 | /** \addtogroup SAM3S_PMC Power Management Controller */ |
| 3393 | /*@{*/ |
| 3394 | |
| 3395 | #ifndef __ASSEMBLY__ |
| 3396 | /** \brief Pmc hardware registers */ |
| 3397 | typedef struct { |
| 3398 | WoReg PMC_SCER; /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */ |
| 3399 | WoReg PMC_SCDR; /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */ |
| 3400 | RoReg PMC_SCSR; /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */ |
| 3401 | RwReg Reserved1[1]; |
| 3402 | WoReg PMC_PCER0; /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */ |
| 3403 | WoReg PMC_PCDR0; /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */ |
| 3404 | RoReg PMC_PCSR0; /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */ |
| 3405 | RwReg Reserved2[1]; |
| 3406 | RwReg CKGR_MOR; /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */ |
| 3407 | RoReg CKGR_MCFR; /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */ |
| 3408 | RwReg CKGR_PLLAR; /**< \brief (Pmc Offset: 0x0028) PLLA Register */ |
| 3409 | RwReg CKGR_PLLBR; /**< \brief (Pmc Offset: 0x002C) PLLB Register */ |
| 3410 | RwReg PMC_MCKR; /**< \brief (Pmc Offset: 0x0030) Master Clock Register */ |
| 3411 | RwReg Reserved3[1]; |
| 3412 | RwReg PMC_USB; /**< \brief (Pmc Offset: 0x0038) USB Clock Register */ |
| 3413 | RwReg Reserved4[1]; |
| 3414 | RwReg PMC_PCK[3]; /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */ |
| 3415 | RwReg Reserved5[5]; |
| 3416 | WoReg PMC_IER; /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */ |
| 3417 | WoReg PMC_IDR; /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */ |
| 3418 | RoReg PMC_SR; /**< \brief (Pmc Offset: 0x0068) Status Register */ |
| 3419 | RoReg PMC_IMR; /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */ |
| 3420 | RwReg PMC_FSMR; /**< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register */ |
| 3421 | RwReg PMC_FSPR; /**< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register */ |
| 3422 | WoReg PMC_FOCR; /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */ |
| 3423 | RwReg Reserved6[26]; |
| 3424 | RwReg PMC_WPMR; /**< \brief (Pmc Offset: 0x00E4) Write Protect Mode Register */ |
| 3425 | RoReg PMC_WPSR; /**< \brief (Pmc Offset: 0x00E8) Write Protect Status Register */ |
| 3426 | RwReg Reserved7[5]; |
| 3427 | WoReg PMC_PCER1; /**< \brief (Pmc Offset: 0x0100) Peripheral Clock Enable Register 1 */ |
| 3428 | WoReg PMC_PCDR1; /**< \brief (Pmc Offset: 0x0104) Peripheral Clock Disable Register 1 */ |
| 3429 | RoReg PMC_PCSR1; /**< \brief (Pmc Offset: 0x0108) Peripheral Clock Status Register 1 */ |
| 3430 | RwReg Reserved8[1]; |
| 3431 | RwReg PMC_OCR; /**< \brief (Pmc Offset: 0x0110) Oscillator Calibration Register */ |
| 3432 | } Pmc; |
| 3433 | #endif /* __ASSEMBLY__ */ |
| 3434 | /* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */ |
| 3435 | #define PMC_SCER_UDP (0x1u << 7) /**< \brief (PMC_SCER) USB Device Port Clock Enable */ |
| 3436 | #define PMC_SCER_PCK0 (0x1u << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */ |
| 3437 | #define PMC_SCER_PCK1 (0x1u << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */ |
| 3438 | #define PMC_SCER_PCK2 (0x1u << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */ |
| 3439 | /* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */ |
| 3440 | #define PMC_SCDR_UDP (0x1u << 7) /**< \brief (PMC_SCDR) USB Device Port Clock Disable */ |
| 3441 | #define PMC_SCDR_PCK0 (0x1u << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */ |
| 3442 | #define PMC_SCDR_PCK1 (0x1u << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */ |
| 3443 | #define PMC_SCDR_PCK2 (0x1u << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */ |
| 3444 | /* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */ |
| 3445 | #define PMC_SCSR_UDP (0x1u << 7) /**< \brief (PMC_SCSR) USB Device Port Clock Status */ |
| 3446 | #define PMC_SCSR_PCK0 (0x1u << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */ |
| 3447 | #define PMC_SCSR_PCK1 (0x1u << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */ |
| 3448 | #define PMC_SCSR_PCK2 (0x1u << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */ |
| 3449 | /* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */ |
| 3450 | #define PMC_PCER0_PID2 (0x1u << 2) /**< \brief (PMC_PCER0) Peripheral Clock 2 Enable */ |
| 3451 | #define PMC_PCER0_PID3 (0x1u << 3) /**< \brief (PMC_PCER0) Peripheral Clock 3 Enable */ |
| 3452 | #define PMC_PCER0_PID4 (0x1u << 4) /**< \brief (PMC_PCER0) Peripheral Clock 4 Enable */ |
| 3453 | #define PMC_PCER0_PID5 (0x1u << 5) /**< \brief (PMC_PCER0) Peripheral Clock 5 Enable */ |
| 3454 | #define PMC_PCER0_PID6 (0x1u << 6) /**< \brief (PMC_PCER0) Peripheral Clock 6 Enable */ |
| 3455 | #define PMC_PCER0_PID7 (0x1u << 7) /**< \brief (PMC_PCER0) Peripheral Clock 7 Enable */ |
| 3456 | #define PMC_PCER0_PID8 (0x1u << 8) /**< \brief (PMC_PCER0) Peripheral Clock 8 Enable */ |
| 3457 | #define PMC_PCER0_PID9 (0x1u << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */ |
| 3458 | #define PMC_PCER0_PID10 (0x1u << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */ |
| 3459 | #define PMC_PCER0_PID11 (0x1u << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */ |
| 3460 | #define PMC_PCER0_PID12 (0x1u << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */ |
| 3461 | #define PMC_PCER0_PID13 (0x1u << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */ |
| 3462 | #define PMC_PCER0_PID14 (0x1u << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */ |
| 3463 | #define PMC_PCER0_PID15 (0x1u << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */ |
| 3464 | #define PMC_PCER0_PID16 (0x1u << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */ |
| 3465 | #define PMC_PCER0_PID17 (0x1u << 17) /**< \brief (PMC_PCER0) Peripheral Clock 17 Enable */ |
| 3466 | #define PMC_PCER0_PID18 (0x1u << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */ |
| 3467 | #define PMC_PCER0_PID19 (0x1u << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */ |
| 3468 | #define PMC_PCER0_PID20 (0x1u << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */ |
| 3469 | #define PMC_PCER0_PID21 (0x1u << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */ |
| 3470 | #define PMC_PCER0_PID22 (0x1u << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */ |
| 3471 | #define PMC_PCER0_PID23 (0x1u << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */ |
| 3472 | #define PMC_PCER0_PID24 (0x1u << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */ |
| 3473 | #define PMC_PCER0_PID25 (0x1u << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */ |
| 3474 | #define PMC_PCER0_PID26 (0x1u << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */ |
| 3475 | #define PMC_PCER0_PID27 (0x1u << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */ |
| 3476 | #define PMC_PCER0_PID28 (0x1u << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */ |
| 3477 | #define PMC_PCER0_PID29 (0x1u << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */ |
| 3478 | #define PMC_PCER0_PID30 (0x1u << 30) /**< \brief (PMC_PCER0) Peripheral Clock 30 Enable */ |
| 3479 | #define PMC_PCER0_PID31 (0x1u << 31) /**< \brief (PMC_PCER0) Peripheral Clock 31 Enable */ |
| 3480 | /* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */ |
| 3481 | #define PMC_PCDR0_PID2 (0x1u << 2) /**< \brief (PMC_PCDR0) Peripheral Clock 2 Disable */ |
| 3482 | #define PMC_PCDR0_PID3 (0x1u << 3) /**< \brief (PMC_PCDR0) Peripheral Clock 3 Disable */ |
| 3483 | #define PMC_PCDR0_PID4 (0x1u << 4) /**< \brief (PMC_PCDR0) Peripheral Clock 4 Disable */ |
| 3484 | #define PMC_PCDR0_PID5 (0x1u << 5) /**< \brief (PMC_PCDR0) Peripheral Clock 5 Disable */ |
| 3485 | #define PMC_PCDR0_PID6 (0x1u << 6) /**< \brief (PMC_PCDR0) Peripheral Clock 6 Disable */ |
| 3486 | #define PMC_PCDR0_PID7 (0x1u << 7) /**< \brief (PMC_PCDR0) Peripheral Clock 7 Disable */ |
| 3487 | #define PMC_PCDR0_PID8 (0x1u << 8) /**< \brief (PMC_PCDR0) Peripheral Clock 8 Disable */ |
| 3488 | #define PMC_PCDR0_PID9 (0x1u << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */ |
| 3489 | #define PMC_PCDR0_PID10 (0x1u << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */ |
| 3490 | #define PMC_PCDR0_PID11 (0x1u << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */ |
| 3491 | #define PMC_PCDR0_PID12 (0x1u << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */ |
| 3492 | #define PMC_PCDR0_PID13 (0x1u << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */ |
| 3493 | #define PMC_PCDR0_PID14 (0x1u << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */ |
| 3494 | #define PMC_PCDR0_PID15 (0x1u << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */ |
| 3495 | #define PMC_PCDR0_PID16 (0x1u << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */ |
| 3496 | #define PMC_PCDR0_PID17 (0x1u << 17) /**< \brief (PMC_PCDR0) Peripheral Clock 17 Disable */ |
| 3497 | #define PMC_PCDR0_PID18 (0x1u << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */ |
| 3498 | #define PMC_PCDR0_PID19 (0x1u << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */ |
| 3499 | #define PMC_PCDR0_PID20 (0x1u << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */ |
| 3500 | #define PMC_PCDR0_PID21 (0x1u << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */ |
| 3501 | #define PMC_PCDR0_PID22 (0x1u << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */ |
| 3502 | #define PMC_PCDR0_PID23 (0x1u << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */ |
| 3503 | #define PMC_PCDR0_PID24 (0x1u << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */ |
| 3504 | #define PMC_PCDR0_PID25 (0x1u << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */ |
| 3505 | #define PMC_PCDR0_PID26 (0x1u << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */ |
| 3506 | #define PMC_PCDR0_PID27 (0x1u << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */ |
| 3507 | #define PMC_PCDR0_PID28 (0x1u << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */ |
| 3508 | #define PMC_PCDR0_PID29 (0x1u << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */ |
| 3509 | #define PMC_PCDR0_PID30 (0x1u << 30) /**< \brief (PMC_PCDR0) Peripheral Clock 30 Disable */ |
| 3510 | #define PMC_PCDR0_PID31 (0x1u << 31) /**< \brief (PMC_PCDR0) Peripheral Clock 31 Disable */ |
| 3511 | /* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */ |
| 3512 | #define PMC_PCSR0_PID2 (0x1u << 2) /**< \brief (PMC_PCSR0) Peripheral Clock 2 Status */ |
| 3513 | #define PMC_PCSR0_PID3 (0x1u << 3) /**< \brief (PMC_PCSR0) Peripheral Clock 3 Status */ |
| 3514 | #define PMC_PCSR0_PID4 (0x1u << 4) /**< \brief (PMC_PCSR0) Peripheral Clock 4 Status */ |
| 3515 | #define PMC_PCSR0_PID5 (0x1u << 5) /**< \brief (PMC_PCSR0) Peripheral Clock 5 Status */ |
| 3516 | #define PMC_PCSR0_PID6 (0x1u << 6) /**< \brief (PMC_PCSR0) Peripheral Clock 6 Status */ |
| 3517 | #define PMC_PCSR0_PID7 (0x1u << 7) /**< \brief (PMC_PCSR0) Peripheral Clock 7 Status */ |
| 3518 | #define PMC_PCSR0_PID8 (0x1u << 8) /**< \brief (PMC_PCSR0) Peripheral Clock 8 Status */ |
| 3519 | #define PMC_PCSR0_PID9 (0x1u << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */ |
| 3520 | #define PMC_PCSR0_PID10 (0x1u << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */ |
| 3521 | #define PMC_PCSR0_PID11 (0x1u << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */ |
| 3522 | #define PMC_PCSR0_PID12 (0x1u << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */ |
| 3523 | #define PMC_PCSR0_PID13 (0x1u << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */ |
| 3524 | #define PMC_PCSR0_PID14 (0x1u << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */ |
| 3525 | #define PMC_PCSR0_PID15 (0x1u << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */ |
| 3526 | #define PMC_PCSR0_PID16 (0x1u << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */ |
| 3527 | #define PMC_PCSR0_PID17 (0x1u << 17) /**< \brief (PMC_PCSR0) Peripheral Clock 17 Status */ |
| 3528 | #define PMC_PCSR0_PID18 (0x1u << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */ |
| 3529 | #define PMC_PCSR0_PID19 (0x1u << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */ |
| 3530 | #define PMC_PCSR0_PID20 (0x1u << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */ |
| 3531 | #define PMC_PCSR0_PID21 (0x1u << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */ |
| 3532 | #define PMC_PCSR0_PID22 (0x1u << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */ |
| 3533 | #define PMC_PCSR0_PID23 (0x1u << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */ |
| 3534 | #define PMC_PCSR0_PID24 (0x1u << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */ |
| 3535 | #define PMC_PCSR0_PID25 (0x1u << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */ |
| 3536 | #define PMC_PCSR0_PID26 (0x1u << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */ |
| 3537 | #define PMC_PCSR0_PID27 (0x1u << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */ |
| 3538 | #define PMC_PCSR0_PID28 (0x1u << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */ |
| 3539 | #define PMC_PCSR0_PID29 (0x1u << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */ |
| 3540 | #define PMC_PCSR0_PID30 (0x1u << 30) /**< \brief (PMC_PCSR0) Peripheral Clock 30 Status */ |
| 3541 | #define PMC_PCSR0_PID31 (0x1u << 31) /**< \brief (PMC_PCSR0) Peripheral Clock 31 Status */ |
| 3542 | /* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */ |
| 3543 | #define CKGR_MOR_MOSCXTEN (0x1u << 0) /**< \brief (CKGR_MOR) Main Crystal Oscillator Enable */ |
| 3544 | #define CKGR_MOR_MOSCXTBY (0x1u << 1) /**< \brief (CKGR_MOR) Main Crystal Oscillator Bypass */ |
| 3545 | #define CKGR_MOR_WAITMODE (0x1u << 2) /**< \brief (CKGR_MOR) Wait Mode Command */ |
| 3546 | #define CKGR_MOR_MOSCRCEN (0x1u << 3) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Enable */ |
| 3547 | #define CKGR_MOR_MOSCRCF_Pos 4 |
| 3548 | #define CKGR_MOR_MOSCRCF_Msk (0x7u << CKGR_MOR_MOSCRCF_Pos) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection */ |
| 3549 | #define CKGR_MOR_MOSCRCF_4MHZ (0x0u << 4) /**< \brief (CKGR_MOR) Fast RC Oscillator Frequency is at 4 MHz */ |
| 3550 | #define CKGR_MOR_MOSCRCF_8MHZ (0x1u << 4) /**< \brief (CKGR_MOR) Fast RC Oscillator Frequency is at 8 MHz */ |
| 3551 | #define CKGR_MOR_MOSCRCF_12MHZ (0x2u << 4) /**< \brief (CKGR_MOR) Fast RC Oscillator Frequency is at 12 MHz */ |
| 3552 | #define CKGR_MOR_MOSCXTST_Pos 8 |
| 3553 | #define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) /**< \brief (CKGR_MOR) Main Crystal Oscillator Start-up Time */ |
| 3554 | #define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos))) |
| 3555 | #define CKGR_MOR_KEY_Pos 16 |
| 3556 | #define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos) /**< \brief (CKGR_MOR) Password */ |
| 3557 | #define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos))) |
| 3558 | #define CKGR_MOR_MOSCSEL (0x1u << 24) /**< \brief (CKGR_MOR) Main Oscillator Selection */ |
| 3559 | #define CKGR_MOR_CFDEN (0x1u << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */ |
| 3560 | /* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */ |
| 3561 | #define CKGR_MCFR_MAINF_Pos 0 |
| 3562 | #define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos) /**< \brief (CKGR_MCFR) Main Clock Frequency */ |
| 3563 | #define CKGR_MCFR_MAINFRDY (0x1u << 16) /**< \brief (CKGR_MCFR) Main Clock Ready */ |
| 3564 | /* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */ |
| 3565 | #define CKGR_PLLAR_DIVA_Pos 0 |
| 3566 | #define CKGR_PLLAR_DIVA_Msk (0xffu << CKGR_PLLAR_DIVA_Pos) /**< \brief (CKGR_PLLAR) Divider */ |
| 3567 | #define CKGR_PLLAR_DIVA(value) ((CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos))) |
| 3568 | #define CKGR_PLLAR_PLLACOUNT_Pos 8 |
| 3569 | #define CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos) /**< \brief (CKGR_PLLAR) PLLA Counter */ |
| 3570 | #define CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos))) |
| 3571 | #define CKGR_PLLAR_MULA_Pos 16 |
| 3572 | #define CKGR_PLLAR_MULA_Msk (0x7ffu << CKGR_PLLAR_MULA_Pos) /**< \brief (CKGR_PLLAR) PLLA Multiplier */ |
| 3573 | #define CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos))) |
| 3574 | #define CKGR_PLLAR_STUCKTO1 (0x1u << 29) /**< \brief (CKGR_PLLAR) */ |
| 3575 | /* -------- CKGR_PLLBR : (PMC Offset: 0x002C) PLLB Register -------- */ |
| 3576 | #define CKGR_PLLBR_DIVB_Pos 0 |
| 3577 | #define CKGR_PLLBR_DIVB_Msk (0xffu << CKGR_PLLBR_DIVB_Pos) /**< \brief (CKGR_PLLBR) Divider */ |
| 3578 | #define CKGR_PLLBR_DIVB(value) ((CKGR_PLLBR_DIVB_Msk & ((value) << CKGR_PLLBR_DIVB_Pos))) |
| 3579 | #define CKGR_PLLBR_PLLBCOUNT_Pos 8 |
| 3580 | #define CKGR_PLLBR_PLLBCOUNT_Msk (0x3fu << CKGR_PLLBR_PLLBCOUNT_Pos) /**< \brief (CKGR_PLLBR) PLLB Counter */ |
| 3581 | #define CKGR_PLLBR_PLLBCOUNT(value) ((CKGR_PLLBR_PLLBCOUNT_Msk & ((value) << CKGR_PLLBR_PLLBCOUNT_Pos))) |
| 3582 | #define CKGR_PLLBR_MULB_Pos 16 |
| 3583 | #define CKGR_PLLBR_MULB_Msk (0x7ffu << CKGR_PLLBR_MULB_Pos) /**< \brief (CKGR_PLLBR) PLLB Multiplier */ |
| 3584 | #define CKGR_PLLBR_MULB(value) ((CKGR_PLLBR_MULB_Msk & ((value) << CKGR_PLLBR_MULB_Pos))) |
| 3585 | /* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */ |
| 3586 | #define PMC_MCKR_CSS_Pos 0 |
| 3587 | #define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos) /**< \brief (PMC_MCKR) Master Clock Source Selection */ |
| 3588 | #define PMC_MCKR_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */ |
| 3589 | #define PMC_MCKR_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_MCKR) Main Clock is selected */ |
| 3590 | #define PMC_MCKR_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */ |
| 3591 | #define PMC_MCKR_CSS_PLLB_CLK (0x3u << 0) /**< \brief (PMC_MCKR) PLLB Clock is selected */ |
| 3592 | #define PMC_MCKR_PRES_Pos 4 |
| 3593 | #define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) /**< \brief (PMC_MCKR) Processor Clock Prescaler */ |
| 3594 | #define PMC_MCKR_PRES_CLK (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */ |
| 3595 | #define PMC_MCKR_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */ |
| 3596 | #define PMC_MCKR_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */ |
| 3597 | #define PMC_MCKR_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */ |
| 3598 | #define PMC_MCKR_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */ |
| 3599 | #define PMC_MCKR_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */ |
| 3600 | #define PMC_MCKR_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */ |
| 3601 | #define PMC_MCKR_PRES_CLK_3 (0x7u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 3 */ |
| 3602 | #define PMC_MCKR_PLLADIV2 (0x1u << 12) /**< \brief (PMC_MCKR) PLLA Divisor by 2 */ |
| 3603 | #define PMC_MCKR_PLLBDIV2 (0x1u << 13) /**< \brief (PMC_MCKR) PLLB Divisor by 2 */ |
| 3604 | /* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */ |
| 3605 | #define PMC_USB_USBS (0x1u << 0) /**< \brief (PMC_USB) USB Input Clock Selection */ |
| 3606 | #define PMC_USB_USBDIV_Pos 8 |
| 3607 | #define PMC_USB_USBDIV_Msk (0xfu << PMC_USB_USBDIV_Pos) /**< \brief (PMC_USB) Divider for USB Clock. */ |
| 3608 | #define PMC_USB_USBDIV(value) ((PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos))) |
| 3609 | /* -------- PMC_PCK[3] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */ |
| 3610 | #define PMC_PCK_CSS_Pos 0 |
| 3611 | #define PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos) /**< \brief (PMC_PCK[3]) Master Clock Source Selection */ |
| 3612 | #define PMC_PCK_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK[3]) Slow Clock is selected */ |
| 3613 | #define PMC_PCK_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK[3]) Main Clock is selected */ |
| 3614 | #define PMC_PCK_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK[3]) PLLA Clock is selected */ |
| 3615 | #define PMC_PCK_CSS_PLLB_CLK (0x3u << 0) /**< \brief (PMC_PCK[3]) PLLB Clock is selected */ |
| 3616 | #define PMC_PCK_CSS_MCK (0x4u << 0) /**< \brief (PMC_PCK[3]) Master Clock is selected */ |
| 3617 | #define PMC_PCK_PRES_Pos 4 |
| 3618 | #define PMC_PCK_PRES_Msk (0x7u << PMC_PCK_PRES_Pos) /**< \brief (PMC_PCK[3]) Programmable Clock Prescaler */ |
| 3619 | #define PMC_PCK_PRES_CLK (0x0u << 4) /**< \brief (PMC_PCK[3]) Selected clock */ |
| 3620 | #define PMC_PCK_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 2 */ |
| 3621 | #define PMC_PCK_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 4 */ |
| 3622 | #define PMC_PCK_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 8 */ |
| 3623 | #define PMC_PCK_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 16 */ |
| 3624 | #define PMC_PCK_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 32 */ |
| 3625 | #define PMC_PCK_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 64 */ |
| 3626 | /* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */ |
| 3627 | #define PMC_IER_MOSCXTS (0x1u << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */ |
| 3628 | #define PMC_IER_LOCKA (0x1u << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */ |
| 3629 | #define PMC_IER_LOCKB (0x1u << 2) /**< \brief (PMC_IER) PLLB Lock Interrupt Enable */ |
| 3630 | #define PMC_IER_MCKRDY (0x1u << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */ |
| 3631 | #define PMC_IER_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */ |
| 3632 | #define PMC_IER_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */ |
| 3633 | #define PMC_IER_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */ |
| 3634 | #define PMC_IER_MOSCSELS (0x1u << 16) /**< \brief (PMC_IER) Main Oscillator Selection Status Interrupt Enable */ |
| 3635 | #define PMC_IER_MOSCRCS (0x1u << 17) /**< \brief (PMC_IER) Main On-Chip RC Status Interrupt Enable */ |
| 3636 | #define PMC_IER_CFDEV (0x1u << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */ |
| 3637 | /* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */ |
| 3638 | #define PMC_IDR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */ |
| 3639 | #define PMC_IDR_LOCKA (0x1u << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */ |
| 3640 | #define PMC_IDR_LOCKB (0x1u << 2) /**< \brief (PMC_IDR) PLLB Lock Interrupt Disable */ |
| 3641 | #define PMC_IDR_MCKRDY (0x1u << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */ |
| 3642 | #define PMC_IDR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */ |
| 3643 | #define PMC_IDR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */ |
| 3644 | #define PMC_IDR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */ |
| 3645 | #define PMC_IDR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IDR) Main Oscillator Selection Status Interrupt Disable */ |
| 3646 | #define PMC_IDR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IDR) Main On-Chip RC Status Interrupt Disable */ |
| 3647 | #define PMC_IDR_CFDEV (0x1u << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */ |
| 3648 | /* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */ |
| 3649 | #define PMC_SR_MOSCXTS (0x1u << 0) /**< \brief (PMC_SR) Main XTAL Oscillator Status */ |
| 3650 | #define PMC_SR_LOCKA (0x1u << 1) /**< \brief (PMC_SR) PLLA Lock Status */ |
| 3651 | #define PMC_SR_LOCKB (0x1u << 2) /**< \brief (PMC_SR) PLLB Lock Status */ |
| 3652 | #define PMC_SR_MCKRDY (0x1u << 3) /**< \brief (PMC_SR) Master Clock Status */ |
| 3653 | #define PMC_SR_OSCSELS (0x1u << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */ |
| 3654 | #define PMC_SR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */ |
| 3655 | #define PMC_SR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */ |
| 3656 | #define PMC_SR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */ |
| 3657 | #define PMC_SR_MOSCSELS (0x1u << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */ |
| 3658 | #define PMC_SR_MOSCRCS (0x1u << 17) /**< \brief (PMC_SR) Main On-Chip RC Oscillator Status */ |
| 3659 | #define PMC_SR_CFDEV (0x1u << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */ |
| 3660 | #define PMC_SR_CFDS (0x1u << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */ |
| 3661 | #define PMC_SR_FOS (0x1u << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */ |
| 3662 | /* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */ |
| 3663 | #define PMC_IMR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */ |
| 3664 | #define PMC_IMR_LOCKA (0x1u << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */ |
| 3665 | #define PMC_IMR_LOCKB (0x1u << 2) /**< \brief (PMC_IMR) PLLB Lock Interrupt Mask */ |
| 3666 | #define PMC_IMR_MCKRDY (0x1u << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */ |
| 3667 | #define PMC_IMR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */ |
| 3668 | #define PMC_IMR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */ |
| 3669 | #define PMC_IMR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */ |
| 3670 | #define PMC_IMR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IMR) Main Oscillator Selection Status Interrupt Mask */ |
| 3671 | #define PMC_IMR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IMR) Main On-Chip RC Status Interrupt Mask */ |
| 3672 | #define PMC_IMR_CFDEV (0x1u << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */ |
| 3673 | /* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */ |
| 3674 | #define PMC_FSMR_FSTT0 (0x1u << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */ |
| 3675 | #define PMC_FSMR_FSTT1 (0x1u << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */ |
| 3676 | #define PMC_FSMR_FSTT2 (0x1u << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */ |
| 3677 | #define PMC_FSMR_FSTT3 (0x1u << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */ |
| 3678 | #define PMC_FSMR_FSTT4 (0x1u << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */ |
| 3679 | #define PMC_FSMR_FSTT5 (0x1u << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */ |
| 3680 | #define PMC_FSMR_FSTT6 (0x1u << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */ |
| 3681 | #define PMC_FSMR_FSTT7 (0x1u << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */ |
| 3682 | #define PMC_FSMR_FSTT8 (0x1u << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */ |
| 3683 | #define PMC_FSMR_FSTT9 (0x1u << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */ |
| 3684 | #define PMC_FSMR_FSTT10 (0x1u << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */ |
| 3685 | #define PMC_FSMR_FSTT11 (0x1u << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */ |
| 3686 | #define PMC_FSMR_FSTT12 (0x1u << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */ |
| 3687 | #define PMC_FSMR_FSTT13 (0x1u << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */ |
| 3688 | #define PMC_FSMR_FSTT14 (0x1u << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */ |
| 3689 | #define PMC_FSMR_FSTT15 (0x1u << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */ |
| 3690 | #define PMC_FSMR_RTTAL (0x1u << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */ |
| 3691 | #define PMC_FSMR_RTCAL (0x1u << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */ |
| 3692 | #define PMC_FSMR_USBAL (0x1u << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */ |
| 3693 | #define PMC_FSMR_LPM (0x1u << 20) /**< \brief (PMC_FSMR) Low Power Mode */ |
| 3694 | /* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */ |
| 3695 | #define PMC_FSPR_FSTP0 (0x1u << 0) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ |
| 3696 | #define PMC_FSPR_FSTP1 (0x1u << 1) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ |
| 3697 | #define PMC_FSPR_FSTP2 (0x1u << 2) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ |
| 3698 | #define PMC_FSPR_FSTP3 (0x1u << 3) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ |
| 3699 | #define PMC_FSPR_FSTP4 (0x1u << 4) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ |
| 3700 | #define PMC_FSPR_FSTP5 (0x1u << 5) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ |
| 3701 | #define PMC_FSPR_FSTP6 (0x1u << 6) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ |
| 3702 | #define PMC_FSPR_FSTP7 (0x1u << 7) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ |
| 3703 | #define PMC_FSPR_FSTP8 (0x1u << 8) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ |
| 3704 | #define PMC_FSPR_FSTP9 (0x1u << 9) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ |
| 3705 | #define PMC_FSPR_FSTP10 (0x1u << 10) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ |
| 3706 | #define PMC_FSPR_FSTP11 (0x1u << 11) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ |
| 3707 | #define PMC_FSPR_FSTP12 (0x1u << 12) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ |
| 3708 | #define PMC_FSPR_FSTP13 (0x1u << 13) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ |
| 3709 | #define PMC_FSPR_FSTP14 (0x1u << 14) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ |
| 3710 | #define PMC_FSPR_FSTP15 (0x1u << 15) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ |
| 3711 | /* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */ |
| 3712 | #define PMC_FOCR_FOCLR (0x1u << 0) /**< \brief (PMC_FOCR) Fault Output Clear */ |
| 3713 | /* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protect Mode Register -------- */ |
| 3714 | #define PMC_WPMR_WPEN (0x1u << 0) /**< \brief (PMC_WPMR) Write Protect Enable */ |
| 3715 | #define PMC_WPMR_WPKEY_Pos 8 |
| 3716 | #define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos) /**< \brief (PMC_WPMR) Write Protect KEY */ |
| 3717 | #define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos))) |
| 3718 | /* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protect Status Register -------- */ |
| 3719 | #define PMC_WPSR_WPVS (0x1u << 0) /**< \brief (PMC_WPSR) Write Protect Violation Status */ |
| 3720 | #define PMC_WPSR_WPVSRC_Pos 8 |
| 3721 | #define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos) /**< \brief (PMC_WPSR) Write Protect Violation Source */ |
| 3722 | /* -------- PMC_PCER1 : (PMC Offset: 0x0100) Peripheral Clock Enable Register 1 -------- */ |
| 3723 | #define PMC_PCER1_PID32 (0x1u << 0) /**< \brief (PMC_PCER1) Peripheral Clock 32 Enable */ |
| 3724 | #define PMC_PCER1_PID33 (0x1u << 1) /**< \brief (PMC_PCER1) Peripheral Clock 33 Enable */ |
| 3725 | #define PMC_PCER1_PID34 (0x1u << 2) /**< \brief (PMC_PCER1) Peripheral Clock 34 Enable */ |
| 3726 | #define PMC_PCER1_PID35 (0x1u << 3) /**< \brief (PMC_PCER1) Peripheral Clock 35 Enable */ |
| 3727 | #define PMC_PCER1_PID36 (0x1u << 4) /**< \brief (PMC_PCER1) Peripheral Clock 36 Enable */ |
| 3728 | #define PMC_PCER1_PID37 (0x1u << 5) /**< \brief (PMC_PCER1) Peripheral Clock 37 Enable */ |
| 3729 | #define PMC_PCER1_PID38 (0x1u << 6) /**< \brief (PMC_PCER1) Peripheral Clock 38 Enable */ |
| 3730 | #define PMC_PCER1_PID39 (0x1u << 7) /**< \brief (PMC_PCER1) Peripheral Clock 39 Enable */ |
| 3731 | #define PMC_PCER1_PID40 (0x1u << 8) /**< \brief (PMC_PCER1) Peripheral Clock 40 Enable */ |
| 3732 | #define PMC_PCER1_PID41 (0x1u << 9) /**< \brief (PMC_PCER1) Peripheral Clock 41 Enable */ |
| 3733 | #define PMC_PCER1_PID42 (0x1u << 10) /**< \brief (PMC_PCER1) Peripheral Clock 42 Enable */ |
| 3734 | #define PMC_PCER1_PID43 (0x1u << 11) /**< \brief (PMC_PCER1) Peripheral Clock 43 Enable */ |
| 3735 | #define PMC_PCER1_PID44 (0x1u << 12) /**< \brief (PMC_PCER1) Peripheral Clock 44 Enable */ |
| 3736 | #define PMC_PCER1_PID45 (0x1u << 13) /**< \brief (PMC_PCER1) Peripheral Clock 45 Enable */ |
| 3737 | #define PMC_PCER1_PID46 (0x1u << 14) /**< \brief (PMC_PCER1) Peripheral Clock 46 Enable */ |
| 3738 | #define PMC_PCER1_PID47 (0x1u << 15) /**< \brief (PMC_PCER1) Peripheral Clock 47 Enable */ |
| 3739 | #define PMC_PCER1_PID48 (0x1u << 16) /**< \brief (PMC_PCER1) Peripheral Clock 48 Enable */ |
| 3740 | #define PMC_PCER1_PID49 (0x1u << 17) /**< \brief (PMC_PCER1) Peripheral Clock 49 Enable */ |
| 3741 | #define PMC_PCER1_PID50 (0x1u << 18) /**< \brief (PMC_PCER1) Peripheral Clock 50 Enable */ |
| 3742 | #define PMC_PCER1_PID51 (0x1u << 19) /**< \brief (PMC_PCER1) Peripheral Clock 51 Enable */ |
| 3743 | #define PMC_PCER1_PID52 (0x1u << 20) /**< \brief (PMC_PCER1) Peripheral Clock 52 Enable */ |
| 3744 | #define PMC_PCER1_PID53 (0x1u << 21) /**< \brief (PMC_PCER1) Peripheral Clock 53 Enable */ |
| 3745 | #define PMC_PCER1_PID54 (0x1u << 22) /**< \brief (PMC_PCER1) Peripheral Clock 54 Enable */ |
| 3746 | #define PMC_PCER1_PID55 (0x1u << 23) /**< \brief (PMC_PCER1) Peripheral Clock 55 Enable */ |
| 3747 | #define PMC_PCER1_PID56 (0x1u << 24) /**< \brief (PMC_PCER1) Peripheral Clock 56 Enable */ |
| 3748 | #define PMC_PCER1_PID57 (0x1u << 25) /**< \brief (PMC_PCER1) Peripheral Clock 57 Enable */ |
| 3749 | #define PMC_PCER1_PID58 (0x1u << 26) /**< \brief (PMC_PCER1) Peripheral Clock 58 Enable */ |
| 3750 | #define PMC_PCER1_PID59 (0x1u << 27) /**< \brief (PMC_PCER1) Peripheral Clock 59 Enable */ |
| 3751 | #define PMC_PCER1_PID60 (0x1u << 28) /**< \brief (PMC_PCER1) Peripheral Clock 60 Enable */ |
| 3752 | #define PMC_PCER1_PID61 (0x1u << 29) /**< \brief (PMC_PCER1) Peripheral Clock 61 Enable */ |
| 3753 | #define PMC_PCER1_PID62 (0x1u << 30) /**< \brief (PMC_PCER1) Peripheral Clock 62 Enable */ |
| 3754 | #define PMC_PCER1_PID63 (0x1u << 31) /**< \brief (PMC_PCER1) Peripheral Clock 63 Enable */ |
| 3755 | /* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */ |
| 3756 | #define PMC_PCDR1_PID32 (0x1u << 0) /**< \brief (PMC_PCDR1) Peripheral Clock 32 Disable */ |
| 3757 | #define PMC_PCDR1_PID33 (0x1u << 1) /**< \brief (PMC_PCDR1) Peripheral Clock 33 Disable */ |
| 3758 | #define PMC_PCDR1_PID34 (0x1u << 2) /**< \brief (PMC_PCDR1) Peripheral Clock 34 Disable */ |
| 3759 | #define PMC_PCDR1_PID35 (0x1u << 3) /**< \brief (PMC_PCDR1) Peripheral Clock 35 Disable */ |
| 3760 | #define PMC_PCDR1_PID36 (0x1u << 4) /**< \brief (PMC_PCDR1) Peripheral Clock 36 Disable */ |
| 3761 | #define PMC_PCDR1_PID37 (0x1u << 5) /**< \brief (PMC_PCDR1) Peripheral Clock 37 Disable */ |
| 3762 | #define PMC_PCDR1_PID38 (0x1u << 6) /**< \brief (PMC_PCDR1) Peripheral Clock 38 Disable */ |
| 3763 | #define PMC_PCDR1_PID39 (0x1u << 7) /**< \brief (PMC_PCDR1) Peripheral Clock 39 Disable */ |
| 3764 | #define PMC_PCDR1_PID40 (0x1u << 8) /**< \brief (PMC_PCDR1) Peripheral Clock 40 Disable */ |
| 3765 | #define PMC_PCDR1_PID41 (0x1u << 9) /**< \brief (PMC_PCDR1) Peripheral Clock 41 Disable */ |
| 3766 | #define PMC_PCDR1_PID42 (0x1u << 10) /**< \brief (PMC_PCDR1) Peripheral Clock 42 Disable */ |
| 3767 | #define PMC_PCDR1_PID43 (0x1u << 11) /**< \brief (PMC_PCDR1) Peripheral Clock 43 Disable */ |
| 3768 | #define PMC_PCDR1_PID44 (0x1u << 12) /**< \brief (PMC_PCDR1) Peripheral Clock 44 Disable */ |
| 3769 | #define PMC_PCDR1_PID45 (0x1u << 13) /**< \brief (PMC_PCDR1) Peripheral Clock 45 Disable */ |
| 3770 | #define PMC_PCDR1_PID46 (0x1u << 14) /**< \brief (PMC_PCDR1) Peripheral Clock 46 Disable */ |
| 3771 | #define PMC_PCDR1_PID47 (0x1u << 15) /**< \brief (PMC_PCDR1) Peripheral Clock 47 Disable */ |
| 3772 | #define PMC_PCDR1_PID48 (0x1u << 16) /**< \brief (PMC_PCDR1) Peripheral Clock 48 Disable */ |
| 3773 | #define PMC_PCDR1_PID49 (0x1u << 17) /**< \brief (PMC_PCDR1) Peripheral Clock 49 Disable */ |
| 3774 | #define PMC_PCDR1_PID50 (0x1u << 18) /**< \brief (PMC_PCDR1) Peripheral Clock 50 Disable */ |
| 3775 | #define PMC_PCDR1_PID51 (0x1u << 19) /**< \brief (PMC_PCDR1) Peripheral Clock 51 Disable */ |
| 3776 | #define PMC_PCDR1_PID52 (0x1u << 20) /**< \brief (PMC_PCDR1) Peripheral Clock 52 Disable */ |
| 3777 | #define PMC_PCDR1_PID53 (0x1u << 21) /**< \brief (PMC_PCDR1) Peripheral Clock 53 Disable */ |
| 3778 | #define PMC_PCDR1_PID54 (0x1u << 22) /**< \brief (PMC_PCDR1) Peripheral Clock 54 Disable */ |
| 3779 | #define PMC_PCDR1_PID55 (0x1u << 23) /**< \brief (PMC_PCDR1) Peripheral Clock 55 Disable */ |
| 3780 | #define PMC_PCDR1_PID56 (0x1u << 24) /**< \brief (PMC_PCDR1) Peripheral Clock 56 Disable */ |
| 3781 | #define PMC_PCDR1_PID57 (0x1u << 25) /**< \brief (PMC_PCDR1) Peripheral Clock 57 Disable */ |
| 3782 | #define PMC_PCDR1_PID58 (0x1u << 26) /**< \brief (PMC_PCDR1) Peripheral Clock 58 Disable */ |
| 3783 | #define PMC_PCDR1_PID59 (0x1u << 27) /**< \brief (PMC_PCDR1) Peripheral Clock 59 Disable */ |
| 3784 | #define PMC_PCDR1_PID60 (0x1u << 28) /**< \brief (PMC_PCDR1) Peripheral Clock 60 Disable */ |
| 3785 | #define PMC_PCDR1_PID61 (0x1u << 29) /**< \brief (PMC_PCDR1) Peripheral Clock 61 Disable */ |
| 3786 | #define PMC_PCDR1_PID62 (0x1u << 30) /**< \brief (PMC_PCDR1) Peripheral Clock 62 Disable */ |
| 3787 | #define PMC_PCDR1_PID63 (0x1u << 31) /**< \brief (PMC_PCDR1) Peripheral Clock 63 Disable */ |
| 3788 | /* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */ |
| 3789 | #define PMC_PCSR1_PID32 (0x1u << 0) /**< \brief (PMC_PCSR1) Peripheral Clock 32 Status */ |
| 3790 | #define PMC_PCSR1_PID33 (0x1u << 1) /**< \brief (PMC_PCSR1) Peripheral Clock 33 Status */ |
| 3791 | #define PMC_PCSR1_PID34 (0x1u << 2) /**< \brief (PMC_PCSR1) Peripheral Clock 34 Status */ |
| 3792 | #define PMC_PCSR1_PID35 (0x1u << 3) /**< \brief (PMC_PCSR1) Peripheral Clock 35 Status */ |
| 3793 | #define PMC_PCSR1_PID36 (0x1u << 4) /**< \brief (PMC_PCSR1) Peripheral Clock 36 Status */ |
| 3794 | #define PMC_PCSR1_PID37 (0x1u << 5) /**< \brief (PMC_PCSR1) Peripheral Clock 37 Status */ |
| 3795 | #define PMC_PCSR1_PID38 (0x1u << 6) /**< \brief (PMC_PCSR1) Peripheral Clock 38 Status */ |
| 3796 | #define PMC_PCSR1_PID39 (0x1u << 7) /**< \brief (PMC_PCSR1) Peripheral Clock 39 Status */ |
| 3797 | #define PMC_PCSR1_PID40 (0x1u << 8) /**< \brief (PMC_PCSR1) Peripheral Clock 40 Status */ |
| 3798 | #define PMC_PCSR1_PID41 (0x1u << 9) /**< \brief (PMC_PCSR1) Peripheral Clock 41 Status */ |
| 3799 | #define PMC_PCSR1_PID42 (0x1u << 10) /**< \brief (PMC_PCSR1) Peripheral Clock 42 Status */ |
| 3800 | #define PMC_PCSR1_PID43 (0x1u << 11) /**< \brief (PMC_PCSR1) Peripheral Clock 43 Status */ |
| 3801 | #define PMC_PCSR1_PID44 (0x1u << 12) /**< \brief (PMC_PCSR1) Peripheral Clock 44 Status */ |
| 3802 | #define PMC_PCSR1_PID45 (0x1u << 13) /**< \brief (PMC_PCSR1) Peripheral Clock 45 Status */ |
| 3803 | #define PMC_PCSR1_PID46 (0x1u << 14) /**< \brief (PMC_PCSR1) Peripheral Clock 46 Status */ |
| 3804 | #define PMC_PCSR1_PID47 (0x1u << 15) /**< \brief (PMC_PCSR1) Peripheral Clock 47 Status */ |
| 3805 | #define PMC_PCSR1_PID48 (0x1u << 16) /**< \brief (PMC_PCSR1) Peripheral Clock 48 Status */ |
| 3806 | #define PMC_PCSR1_PID49 (0x1u << 17) /**< \brief (PMC_PCSR1) Peripheral Clock 49 Status */ |
| 3807 | #define PMC_PCSR1_PID50 (0x1u << 18) /**< \brief (PMC_PCSR1) Peripheral Clock 50 Status */ |
| 3808 | #define PMC_PCSR1_PID51 (0x1u << 19) /**< \brief (PMC_PCSR1) Peripheral Clock 51 Status */ |
| 3809 | #define PMC_PCSR1_PID52 (0x1u << 20) /**< \brief (PMC_PCSR1) Peripheral Clock 52 Status */ |
| 3810 | #define PMC_PCSR1_PID53 (0x1u << 21) /**< \brief (PMC_PCSR1) Peripheral Clock 53 Status */ |
| 3811 | #define PMC_PCSR1_PID54 (0x1u << 22) /**< \brief (PMC_PCSR1) Peripheral Clock 54 Status */ |
| 3812 | #define PMC_PCSR1_PID55 (0x1u << 23) /**< \brief (PMC_PCSR1) Peripheral Clock 55 Status */ |
| 3813 | #define PMC_PCSR1_PID56 (0x1u << 24) /**< \brief (PMC_PCSR1) Peripheral Clock 56 Status */ |
| 3814 | #define PMC_PCSR1_PID57 (0x1u << 25) /**< \brief (PMC_PCSR1) Peripheral Clock 57 Status */ |
| 3815 | #define PMC_PCSR1_PID58 (0x1u << 26) /**< \brief (PMC_PCSR1) Peripheral Clock 58 Status */ |
| 3816 | #define PMC_PCSR1_PID59 (0x1u << 27) /**< \brief (PMC_PCSR1) Peripheral Clock 59 Status */ |
| 3817 | #define PMC_PCSR1_PID60 (0x1u << 28) /**< \brief (PMC_PCSR1) Peripheral Clock 60 Status */ |
| 3818 | #define PMC_PCSR1_PID61 (0x1u << 29) /**< \brief (PMC_PCSR1) Peripheral Clock 61 Status */ |
| 3819 | #define PMC_PCSR1_PID62 (0x1u << 30) /**< \brief (PMC_PCSR1) Peripheral Clock 62 Status */ |
| 3820 | #define PMC_PCSR1_PID63 (0x1u << 31) /**< \brief (PMC_PCSR1) Peripheral Clock 63 Status */ |
| 3821 | /* -------- PMC_OCR : (PMC Offset: 0x0110) Oscillator Calibration Register -------- */ |
| 3822 | #define PMC_OCR_CAL4_Pos 0 |
| 3823 | #define PMC_OCR_CAL4_Msk (0x7fu << PMC_OCR_CAL4_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 4 Mhz */ |
| 3824 | #define PMC_OCR_CAL4(value) ((PMC_OCR_CAL4_Msk & ((value) << PMC_OCR_CAL4_Pos))) |
| 3825 | #define PMC_OCR_SEL4 (0x1u << 7) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 4 Mhz */ |
| 3826 | #define PMC_OCR_CAL8_Pos 8 |
| 3827 | #define PMC_OCR_CAL8_Msk (0x7fu << PMC_OCR_CAL8_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 8 Mhz */ |
| 3828 | #define PMC_OCR_CAL8(value) ((PMC_OCR_CAL8_Msk & ((value) << PMC_OCR_CAL8_Pos))) |
| 3829 | #define PMC_OCR_SEL8 (0x1u << 15) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 8 Mhz */ |
| 3830 | #define PMC_OCR_CAL12_Pos 16 |
| 3831 | #define PMC_OCR_CAL12_Msk (0x7fu << PMC_OCR_CAL12_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 12 Mhz */ |
| 3832 | #define PMC_OCR_CAL12(value) ((PMC_OCR_CAL12_Msk & ((value) << PMC_OCR_CAL12_Pos))) |
| 3833 | #define PMC_OCR_SEL12 (0x1u << 23) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 12 Mhz */ |
| 3834 | |
| 3835 | /*@}*/ |
| 3836 | |
| 3837 | /* ============================================================================= */ |
| 3838 | /** SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */ |
| 3839 | /* ============================================================================= */ |
| 3840 | /** \addtogroup SAM3S_PWM Pulse Width Modulation Controller */ |
| 3841 | /*@{*/ |
| 3842 | |
| 3843 | #ifndef __ASSEMBLY__ |
| 3844 | /** \brief PwmCh_num hardware registers */ |
| 3845 | typedef struct { |
| 3846 | RwReg PWM_CMR; /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */ |
| 3847 | RwReg PWM_CDTY; /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */ |
| 3848 | RwReg PWM_CDTYUPD; /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */ |
| 3849 | RwReg PWM_CPRD; /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */ |
| 3850 | RwReg PWM_CPRDUPD; /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */ |
| 3851 | RwReg PWM_CCNT; /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */ |
| 3852 | RwReg PWM_DT; /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */ |
| 3853 | RwReg PWM_DTUPD; /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */ |
| 3854 | } PwmCh_num; |
| 3855 | /** \brief PwmCmp hardware registers */ |
| 3856 | typedef struct { |
| 3857 | RwReg PWM_CMPxV; /**< \brief (PwmCmp Offset: 0x0) PWM Comparison 0 Value Register */ |
| 3858 | RwReg PWM_CMPxVUPD; /**< \brief (PwmCmp Offset: 0x4) PWM Comparison 0 Value Update Register */ |
| 3859 | RwReg PWM_CMPxM; /**< \brief (PwmCmp Offset: 0x8) PWM Comparison 0 Mode Register */ |
| 3860 | RwReg PWM_CMPxMUPD; /**< \brief (PwmCmp Offset: 0xC) PWM Comparison 0 Mode Update Register */ |
| 3861 | } PwmCmp; |
| 3862 | /** \brief Pwm hardware registers */ |
| 3863 | typedef struct { |
| 3864 | RwReg PWM_CLK; /**< \brief (Pwm Offset: 0x00) PWM Clock Register */ |
| 3865 | WoReg PWM_ENA; /**< \brief (Pwm Offset: 0x04) PWM Enable Register */ |
| 3866 | WoReg PWM_DIS; /**< \brief (Pwm Offset: 0x08) PWM Disable Register */ |
| 3867 | RoReg PWM_SR; /**< \brief (Pwm Offset: 0x0C) PWM Status Register */ |
| 3868 | WoReg PWM_IER1; /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */ |
| 3869 | WoReg PWM_IDR1; /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */ |
| 3870 | RoReg PWM_IMR1; /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */ |
| 3871 | RoReg PWM_ISR1; /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */ |
| 3872 | RwReg PWM_SCM; /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */ |
| 3873 | RwReg Reserved1[1]; |
| 3874 | RwReg PWM_SCUC; /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */ |
| 3875 | RwReg PWM_SCUP; /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */ |
| 3876 | WoReg PWM_SCUPUPD; /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */ |
| 3877 | WoReg PWM_IER2; /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */ |
| 3878 | WoReg PWM_IDR2; /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */ |
| 3879 | RoReg PWM_IMR2; /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */ |
| 3880 | RoReg PWM_ISR2; /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */ |
| 3881 | RwReg PWM_OOV; /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */ |
| 3882 | RwReg PWM_OS; /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */ |
| 3883 | WoReg PWM_OSS; /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */ |
| 3884 | WoReg PWM_OSC; /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */ |
| 3885 | WoReg PWM_OSSUPD; /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */ |
| 3886 | WoReg PWM_OSCUPD; /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */ |
| 3887 | RwReg PWM_FMR; /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */ |
| 3888 | RoReg PWM_FSR; /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */ |
| 3889 | WoReg PWM_FCR; /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */ |
| 3890 | RwReg PWM_FPV; /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register */ |
| 3891 | RwReg PWM_FPE; /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register */ |
| 3892 | RwReg Reserved2[3]; |
| 3893 | RwReg PWM_ELxMR[2]; /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */ |
| 3894 | RwReg Reserved3[11]; |
| 3895 | RwReg PWM_SMMR; /**< \brief (Pwm Offset: 0xB0) PWM Stepper Motor Mode Register */ |
| 3896 | RwReg Reserved4[12]; |
| 3897 | WoReg PWM_WPCR; /**< \brief (Pwm Offset: 0xE4) PWM Write Protect Control Register */ |
| 3898 | RoReg PWM_WPSR; /**< \brief (Pwm Offset: 0xE8) PWM Write Protect Status Register */ |
| 3899 | RwReg Reserved5[5]; |
| 3900 | RwReg PWM_RPR; /**< \brief (Pwm Offset: 0x100) Receive Pointer Register */ |
| 3901 | RwReg PWM_RCR; /**< \brief (Pwm Offset: 0x104) Receive Counter Register */ |
| 3902 | RwReg PWM_TPR; /**< \brief (Pwm Offset: 0x108) Transmit Pointer Register */ |
| 3903 | RwReg PWM_TCR; /**< \brief (Pwm Offset: 0x10C) Transmit Counter Register */ |
| 3904 | RwReg PWM_RNPR; /**< \brief (Pwm Offset: 0x110) Receive Next Pointer Register */ |
| 3905 | RwReg PWM_RNCR; /**< \brief (Pwm Offset: 0x114) Receive Next Counter Register */ |
| 3906 | RwReg PWM_TNPR; /**< \brief (Pwm Offset: 0x118) Transmit Next Pointer Register */ |
| 3907 | RwReg PWM_TNCR; /**< \brief (Pwm Offset: 0x11C) Transmit Next Counter Register */ |
| 3908 | WoReg PWM_PTCR; /**< \brief (Pwm Offset: 0x120) Transfer Control Register */ |
| 3909 | RoReg PWM_PTSR; /**< \brief (Pwm Offset: 0x124) Transfer Status Register */ |
| 3910 | RwReg Reserved6[2]; |
| 3911 | PwmCmp PWM_CMP[8]; /**< \brief (Pwm Offset: 0x130) cmp = 0 .. 7 */ |
| 3912 | RwReg Reserved7[20]; |
| 3913 | PwmCh_num PWM_CH_NUM[4]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 3 */ |
| 3914 | } Pwm; |
| 3915 | #endif /* __ASSEMBLY__ */ |
| 3916 | /* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */ |
| 3917 | #define PWM_CLK_DIVA_Pos 0 |
| 3918 | #define PWM_CLK_DIVA_Msk (0xffu << PWM_CLK_DIVA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */ |
| 3919 | #define PWM_CLK_DIVA(value) ((PWM_CLK_DIVA_Msk & ((value) << PWM_CLK_DIVA_Pos))) |
| 3920 | #define PWM_CLK_PREA_Pos 8 |
| 3921 | #define PWM_CLK_PREA_Msk (0xfu << PWM_CLK_PREA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */ |
| 3922 | #define PWM_CLK_PREA(value) ((PWM_CLK_PREA_Msk & ((value) << PWM_CLK_PREA_Pos))) |
| 3923 | #define PWM_CLK_DIVB_Pos 16 |
| 3924 | #define PWM_CLK_DIVB_Msk (0xffu << PWM_CLK_DIVB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */ |
| 3925 | #define PWM_CLK_DIVB(value) ((PWM_CLK_DIVB_Msk & ((value) << PWM_CLK_DIVB_Pos))) |
| 3926 | #define PWM_CLK_PREB_Pos 24 |
| 3927 | #define PWM_CLK_PREB_Msk (0xfu << PWM_CLK_PREB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */ |
| 3928 | #define PWM_CLK_PREB(value) ((PWM_CLK_PREB_Msk & ((value) << PWM_CLK_PREB_Pos))) |
| 3929 | /* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */ |
| 3930 | #define PWM_ENA_CHID0 (0x1u << 0) /**< \brief (PWM_ENA) Channel ID */ |
| 3931 | #define PWM_ENA_CHID1 (0x1u << 1) /**< \brief (PWM_ENA) Channel ID */ |
| 3932 | #define PWM_ENA_CHID2 (0x1u << 2) /**< \brief (PWM_ENA) Channel ID */ |
| 3933 | #define PWM_ENA_CHID3 (0x1u << 3) /**< \brief (PWM_ENA) Channel ID */ |
| 3934 | /* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */ |
| 3935 | #define PWM_DIS_CHID0 (0x1u << 0) /**< \brief (PWM_DIS) Channel ID */ |
| 3936 | #define PWM_DIS_CHID1 (0x1u << 1) /**< \brief (PWM_DIS) Channel ID */ |
| 3937 | #define PWM_DIS_CHID2 (0x1u << 2) /**< \brief (PWM_DIS) Channel ID */ |
| 3938 | #define PWM_DIS_CHID3 (0x1u << 3) /**< \brief (PWM_DIS) Channel ID */ |
| 3939 | /* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */ |
| 3940 | #define PWM_SR_CHID0 (0x1u << 0) /**< \brief (PWM_SR) Channel ID */ |
| 3941 | #define PWM_SR_CHID1 (0x1u << 1) /**< \brief (PWM_SR) Channel ID */ |
| 3942 | #define PWM_SR_CHID2 (0x1u << 2) /**< \brief (PWM_SR) Channel ID */ |
| 3943 | #define PWM_SR_CHID3 (0x1u << 3) /**< \brief (PWM_SR) Channel ID */ |
| 3944 | /* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */ |
| 3945 | #define PWM_IER1_CHID0 (0x1u << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */ |
| 3946 | #define PWM_IER1_CHID1 (0x1u << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */ |
| 3947 | #define PWM_IER1_CHID2 (0x1u << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */ |
| 3948 | #define PWM_IER1_CHID3 (0x1u << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */ |
| 3949 | #define PWM_IER1_FCHID0 (0x1u << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */ |
| 3950 | #define PWM_IER1_FCHID1 (0x1u << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */ |
| 3951 | #define PWM_IER1_FCHID2 (0x1u << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */ |
| 3952 | #define PWM_IER1_FCHID3 (0x1u << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */ |
| 3953 | /* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */ |
| 3954 | #define PWM_IDR1_CHID0 (0x1u << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */ |
| 3955 | #define PWM_IDR1_CHID1 (0x1u << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */ |
| 3956 | #define PWM_IDR1_CHID2 (0x1u << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */ |
| 3957 | #define PWM_IDR1_CHID3 (0x1u << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */ |
| 3958 | #define PWM_IDR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */ |
| 3959 | #define PWM_IDR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */ |
| 3960 | #define PWM_IDR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */ |
| 3961 | #define PWM_IDR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */ |
| 3962 | /* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */ |
| 3963 | #define PWM_IMR1_CHID0 (0x1u << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */ |
| 3964 | #define PWM_IMR1_CHID1 (0x1u << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */ |
| 3965 | #define PWM_IMR1_CHID2 (0x1u << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */ |
| 3966 | #define PWM_IMR1_CHID3 (0x1u << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */ |
| 3967 | #define PWM_IMR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */ |
| 3968 | #define PWM_IMR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */ |
| 3969 | #define PWM_IMR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */ |
| 3970 | #define PWM_IMR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */ |
| 3971 | /* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */ |
| 3972 | #define PWM_ISR1_CHID0 (0x1u << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */ |
| 3973 | #define PWM_ISR1_CHID1 (0x1u << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */ |
| 3974 | #define PWM_ISR1_CHID2 (0x1u << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */ |
| 3975 | #define PWM_ISR1_CHID3 (0x1u << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */ |
| 3976 | #define PWM_ISR1_FCHID0 (0x1u << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */ |
| 3977 | #define PWM_ISR1_FCHID1 (0x1u << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */ |
| 3978 | #define PWM_ISR1_FCHID2 (0x1u << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */ |
| 3979 | #define PWM_ISR1_FCHID3 (0x1u << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */ |
| 3980 | /* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */ |
| 3981 | #define PWM_SCM_SYNC0 (0x1u << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */ |
| 3982 | #define PWM_SCM_SYNC1 (0x1u << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */ |
| 3983 | #define PWM_SCM_SYNC2 (0x1u << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */ |
| 3984 | #define PWM_SCM_SYNC3 (0x1u << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */ |
| 3985 | #define PWM_SCM_UPDM_Pos 16 |
| 3986 | #define PWM_SCM_UPDM_Msk (0x3u << PWM_SCM_UPDM_Pos) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */ |
| 3987 | #define PWM_SCM_UPDM_MODE0 (0x0u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and manual update of synchronous channels. The update occurs at the begin- ning of the next PWM period, when the bit UPDULOCK in "PWM Sync Channels Update Control Register" on page 55 is set. */ |
| 3988 | #define PWM_SCM_UPDM_MODE1 (0x1u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and automatic update of synchronous channels. The update occurs when the Update Period is elapsed. */ |
| 3989 | #define PWM_SCM_UPDM_MODE2 (0x2u << 16) /**< \brief (PWM_SCM) Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels. The update occurs when the Update Period is elapsed. */ |
| 3990 | #define PWM_SCM_PTRM (0x1u << 20) /**< \brief (PWM_SCM) PDC Transfer Request Mode */ |
| 3991 | #define PWM_SCM_PTRCS_Pos 21 |
| 3992 | #define PWM_SCM_PTRCS_Msk (0x7u << PWM_SCM_PTRCS_Pos) /**< \brief (PWM_SCM) PDC Transfer Request Comparison Selection */ |
| 3993 | #define PWM_SCM_PTRCS(value) ((PWM_SCM_PTRCS_Msk & ((value) << PWM_SCM_PTRCS_Pos))) |
| 3994 | /* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */ |
| 3995 | #define PWM_SCUC_UPDULOCK (0x1u << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */ |
| 3996 | /* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */ |
| 3997 | #define PWM_SCUP_UPR_Pos 0 |
| 3998 | #define PWM_SCUP_UPR_Msk (0xfu << PWM_SCUP_UPR_Pos) /**< \brief (PWM_SCUP) Update Period */ |
| 3999 | #define PWM_SCUP_UPR(value) ((PWM_SCUP_UPR_Msk & ((value) << PWM_SCUP_UPR_Pos))) |
| 4000 | #define PWM_SCUP_UPRCNT_Pos 4 |
| 4001 | #define PWM_SCUP_UPRCNT_Msk (0xfu << PWM_SCUP_UPRCNT_Pos) /**< \brief (PWM_SCUP) Update Period Counter */ |
| 4002 | #define PWM_SCUP_UPRCNT(value) ((PWM_SCUP_UPRCNT_Msk & ((value) << PWM_SCUP_UPRCNT_Pos))) |
| 4003 | /* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */ |
| 4004 | #define PWM_SCUPUPD_UPRUPD_Pos 0 |
| 4005 | #define PWM_SCUPUPD_UPRUPD_Msk (0xfu << PWM_SCUPUPD_UPRUPD_Pos) /**< \brief (PWM_SCUPUPD) Update Period Update */ |
| 4006 | #define PWM_SCUPUPD_UPRUPD(value) ((PWM_SCUPUPD_UPRUPD_Msk & ((value) << PWM_SCUPUPD_UPRUPD_Pos))) |
| 4007 | /* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */ |
| 4008 | #define PWM_IER2_WRDY (0x1u << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */ |
| 4009 | #define PWM_IER2_ENDTX (0x1u << 1) /**< \brief (PWM_IER2) PDC End of TX Buffer Interrupt Enable */ |
| 4010 | #define PWM_IER2_TXBUFE (0x1u << 2) /**< \brief (PWM_IER2) PDC TX Buffer Empty Interrupt Enable */ |
| 4011 | #define PWM_IER2_UNRE (0x1u << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */ |
| 4012 | #define PWM_IER2_CMPM0 (0x1u << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */ |
| 4013 | #define PWM_IER2_CMPM1 (0x1u << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */ |
| 4014 | #define PWM_IER2_CMPM2 (0x1u << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */ |
| 4015 | #define PWM_IER2_CMPM3 (0x1u << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */ |
| 4016 | #define PWM_IER2_CMPM4 (0x1u << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */ |
| 4017 | #define PWM_IER2_CMPM5 (0x1u << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */ |
| 4018 | #define PWM_IER2_CMPM6 (0x1u << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */ |
| 4019 | #define PWM_IER2_CMPM7 (0x1u << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */ |
| 4020 | #define PWM_IER2_CMPU0 (0x1u << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */ |
| 4021 | #define PWM_IER2_CMPU1 (0x1u << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */ |
| 4022 | #define PWM_IER2_CMPU2 (0x1u << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */ |
| 4023 | #define PWM_IER2_CMPU3 (0x1u << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */ |
| 4024 | #define PWM_IER2_CMPU4 (0x1u << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */ |
| 4025 | #define PWM_IER2_CMPU5 (0x1u << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */ |
| 4026 | #define PWM_IER2_CMPU6 (0x1u << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */ |
| 4027 | #define PWM_IER2_CMPU7 (0x1u << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */ |
| 4028 | /* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */ |
| 4029 | #define PWM_IDR2_WRDY (0x1u << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */ |
| 4030 | #define PWM_IDR2_ENDTX (0x1u << 1) /**< \brief (PWM_IDR2) PDC End of TX Buffer Interrupt Disable */ |
| 4031 | #define PWM_IDR2_TXBUFE (0x1u << 2) /**< \brief (PWM_IDR2) PDC TX Buffer Empty Interrupt Disable */ |
| 4032 | #define PWM_IDR2_UNRE (0x1u << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */ |
| 4033 | #define PWM_IDR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */ |
| 4034 | #define PWM_IDR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */ |
| 4035 | #define PWM_IDR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */ |
| 4036 | #define PWM_IDR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */ |
| 4037 | #define PWM_IDR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */ |
| 4038 | #define PWM_IDR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */ |
| 4039 | #define PWM_IDR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */ |
| 4040 | #define PWM_IDR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */ |
| 4041 | #define PWM_IDR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */ |
| 4042 | #define PWM_IDR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */ |
| 4043 | #define PWM_IDR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */ |
| 4044 | #define PWM_IDR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */ |
| 4045 | #define PWM_IDR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */ |
| 4046 | #define PWM_IDR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */ |
| 4047 | #define PWM_IDR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */ |
| 4048 | #define PWM_IDR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */ |
| 4049 | /* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */ |
| 4050 | #define PWM_IMR2_WRDY (0x1u << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */ |
| 4051 | #define PWM_IMR2_ENDTX (0x1u << 1) /**< \brief (PWM_IMR2) PDC End of TX Buffer Interrupt Mask */ |
| 4052 | #define PWM_IMR2_TXBUFE (0x1u << 2) /**< \brief (PWM_IMR2) PDC TX Buffer Empty Interrupt Mask */ |
| 4053 | #define PWM_IMR2_UNRE (0x1u << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */ |
| 4054 | #define PWM_IMR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */ |
| 4055 | #define PWM_IMR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */ |
| 4056 | #define PWM_IMR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */ |
| 4057 | #define PWM_IMR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */ |
| 4058 | #define PWM_IMR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */ |
| 4059 | #define PWM_IMR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */ |
| 4060 | #define PWM_IMR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */ |
| 4061 | #define PWM_IMR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */ |
| 4062 | #define PWM_IMR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */ |
| 4063 | #define PWM_IMR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */ |
| 4064 | #define PWM_IMR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */ |
| 4065 | #define PWM_IMR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */ |
| 4066 | #define PWM_IMR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */ |
| 4067 | #define PWM_IMR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */ |
| 4068 | #define PWM_IMR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */ |
| 4069 | #define PWM_IMR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */ |
| 4070 | /* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */ |
| 4071 | #define PWM_ISR2_WRDY (0x1u << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */ |
| 4072 | #define PWM_ISR2_ENDTX (0x1u << 1) /**< \brief (PWM_ISR2) PDC End of TX Buffer */ |
| 4073 | #define PWM_ISR2_TXBUFE (0x1u << 2) /**< \brief (PWM_ISR2) PDC TX Buffer Empty */ |
| 4074 | #define PWM_ISR2_UNRE (0x1u << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */ |
| 4075 | #define PWM_ISR2_CMPM0 (0x1u << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */ |
| 4076 | #define PWM_ISR2_CMPM1 (0x1u << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */ |
| 4077 | #define PWM_ISR2_CMPM2 (0x1u << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */ |
| 4078 | #define PWM_ISR2_CMPM3 (0x1u << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */ |
| 4079 | #define PWM_ISR2_CMPM4 (0x1u << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */ |
| 4080 | #define PWM_ISR2_CMPM5 (0x1u << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */ |
| 4081 | #define PWM_ISR2_CMPM6 (0x1u << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */ |
| 4082 | #define PWM_ISR2_CMPM7 (0x1u << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */ |
| 4083 | #define PWM_ISR2_CMPU0 (0x1u << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */ |
| 4084 | #define PWM_ISR2_CMPU1 (0x1u << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */ |
| 4085 | #define PWM_ISR2_CMPU2 (0x1u << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */ |
| 4086 | #define PWM_ISR2_CMPU3 (0x1u << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */ |
| 4087 | #define PWM_ISR2_CMPU4 (0x1u << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */ |
| 4088 | #define PWM_ISR2_CMPU5 (0x1u << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */ |
| 4089 | #define PWM_ISR2_CMPU6 (0x1u << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */ |
| 4090 | #define PWM_ISR2_CMPU7 (0x1u << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */ |
| 4091 | /* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */ |
| 4092 | #define PWM_OOV_OOVH0 (0x1u << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */ |
| 4093 | #define PWM_OOV_OOVH1 (0x1u << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */ |
| 4094 | #define PWM_OOV_OOVH2 (0x1u << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */ |
| 4095 | #define PWM_OOV_OOVH3 (0x1u << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */ |
| 4096 | #define PWM_OOV_OOVL0 (0x1u << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */ |
| 4097 | #define PWM_OOV_OOVL1 (0x1u << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */ |
| 4098 | #define PWM_OOV_OOVL2 (0x1u << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */ |
| 4099 | #define PWM_OOV_OOVL3 (0x1u << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */ |
| 4100 | /* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */ |
| 4101 | #define PWM_OS_OSH0 (0x1u << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */ |
| 4102 | #define PWM_OS_OSH1 (0x1u << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */ |
| 4103 | #define PWM_OS_OSH2 (0x1u << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */ |
| 4104 | #define PWM_OS_OSH3 (0x1u << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */ |
| 4105 | #define PWM_OS_OSL0 (0x1u << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */ |
| 4106 | #define PWM_OS_OSL1 (0x1u << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */ |
| 4107 | #define PWM_OS_OSL2 (0x1u << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */ |
| 4108 | #define PWM_OS_OSL3 (0x1u << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */ |
| 4109 | /* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */ |
| 4110 | #define PWM_OSS_OSSH0 (0x1u << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */ |
| 4111 | #define PWM_OSS_OSSH1 (0x1u << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */ |
| 4112 | #define PWM_OSS_OSSH2 (0x1u << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */ |
| 4113 | #define PWM_OSS_OSSH3 (0x1u << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */ |
| 4114 | #define PWM_OSS_OSSL0 (0x1u << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */ |
| 4115 | #define PWM_OSS_OSSL1 (0x1u << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */ |
| 4116 | #define PWM_OSS_OSSL2 (0x1u << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */ |
| 4117 | #define PWM_OSS_OSSL3 (0x1u << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */ |
| 4118 | /* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */ |
| 4119 | #define PWM_OSC_OSCH0 (0x1u << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */ |
| 4120 | #define PWM_OSC_OSCH1 (0x1u << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */ |
| 4121 | #define PWM_OSC_OSCH2 (0x1u << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */ |
| 4122 | #define PWM_OSC_OSCH3 (0x1u << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */ |
| 4123 | #define PWM_OSC_OSCL0 (0x1u << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */ |
| 4124 | #define PWM_OSC_OSCL1 (0x1u << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */ |
| 4125 | #define PWM_OSC_OSCL2 (0x1u << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */ |
| 4126 | #define PWM_OSC_OSCL3 (0x1u << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */ |
| 4127 | /* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */ |
| 4128 | #define PWM_OSSUPD_OSSUPH0 (0x1u << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */ |
| 4129 | #define PWM_OSSUPD_OSSUPH1 (0x1u << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */ |
| 4130 | #define PWM_OSSUPD_OSSUPH2 (0x1u << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */ |
| 4131 | #define PWM_OSSUPD_OSSUPH3 (0x1u << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */ |
| 4132 | #define PWM_OSSUPD_OSSUPL0 (0x1u << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */ |
| 4133 | #define PWM_OSSUPD_OSSUPL1 (0x1u << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */ |
| 4134 | #define PWM_OSSUPD_OSSUPL2 (0x1u << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */ |
| 4135 | #define PWM_OSSUPD_OSSUPL3 (0x1u << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */ |
| 4136 | /* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */ |
| 4137 | #define PWM_OSCUPD_OSCUPH0 (0x1u << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */ |
| 4138 | #define PWM_OSCUPD_OSCUPH1 (0x1u << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */ |
| 4139 | #define PWM_OSCUPD_OSCUPH2 (0x1u << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */ |
| 4140 | #define PWM_OSCUPD_OSCUPH3 (0x1u << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */ |
| 4141 | #define PWM_OSCUPD_OSCUPL0 (0x1u << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */ |
| 4142 | #define PWM_OSCUPD_OSCUPL1 (0x1u << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */ |
| 4143 | #define PWM_OSCUPD_OSCUPL2 (0x1u << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */ |
| 4144 | #define PWM_OSCUPD_OSCUPL3 (0x1u << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */ |
| 4145 | /* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */ |
| 4146 | #define PWM_FMR_FPOL_Pos 0 |
| 4147 | #define PWM_FMR_FPOL_Msk (0xffu << PWM_FMR_FPOL_Pos) /**< \brief (PWM_FMR) Fault Polarity (fault input bit varies from 0 to 5) */ |
| 4148 | #define PWM_FMR_FPOL(value) ((PWM_FMR_FPOL_Msk & ((value) << PWM_FMR_FPOL_Pos))) |
| 4149 | #define PWM_FMR_FMOD_Pos 8 |
| 4150 | #define PWM_FMR_FMOD_Msk (0xffu << PWM_FMR_FMOD_Pos) /**< \brief (PWM_FMR) Fault Activation Mode (fault input bit varies from 0 to 5) */ |
| 4151 | #define PWM_FMR_FMOD(value) ((PWM_FMR_FMOD_Msk & ((value) << PWM_FMR_FMOD_Pos))) |
| 4152 | #define PWM_FMR_FFIL_Pos 16 |
| 4153 | #define PWM_FMR_FFIL_Msk (0xffu << PWM_FMR_FFIL_Pos) /**< \brief (PWM_FMR) Fault Filtering (fault input bit varies from 0 to 5) */ |
| 4154 | #define PWM_FMR_FFIL(value) ((PWM_FMR_FFIL_Msk & ((value) << PWM_FMR_FFIL_Pos))) |
| 4155 | /* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */ |
| 4156 | #define PWM_FSR_FIV_Pos 0 |
| 4157 | #define PWM_FSR_FIV_Msk (0xffu << PWM_FSR_FIV_Pos) /**< \brief (PWM_FSR) Fault Input Value (fault input bit varies from 0 to 5) */ |
| 4158 | #define PWM_FSR_FS_Pos 8 |
| 4159 | #define PWM_FSR_FS_Msk (0xffu << PWM_FSR_FS_Pos) /**< \brief (PWM_FSR) Fault Status (fault input bit varies from 0 to 5) */ |
| 4160 | /* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */ |
| 4161 | #define PWM_FCR_FCLR_Pos 0 |
| 4162 | #define PWM_FCR_FCLR_Msk (0xffu << PWM_FCR_FCLR_Pos) /**< \brief (PWM_FCR) Fault Clear (fault input bit varies from 0 to 5) */ |
| 4163 | #define PWM_FCR_FCLR(value) ((PWM_FCR_FCLR_Msk & ((value) << PWM_FCR_FCLR_Pos))) |
| 4164 | /* -------- PWM_FPV : (PWM Offset: 0x68) PWM Fault Protection Value Register -------- */ |
| 4165 | #define PWM_FPV_FPVH0 (0x1u << 0) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 0 */ |
| 4166 | #define PWM_FPV_FPVH1 (0x1u << 1) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 1 */ |
| 4167 | #define PWM_FPV_FPVH2 (0x1u << 2) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 2 */ |
| 4168 | #define PWM_FPV_FPVH3 (0x1u << 3) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 3 */ |
| 4169 | #define PWM_FPV_FPVL0 (0x1u << 16) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 0 */ |
| 4170 | #define PWM_FPV_FPVL1 (0x1u << 17) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 1 */ |
| 4171 | #define PWM_FPV_FPVL2 (0x1u << 18) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 2 */ |
| 4172 | #define PWM_FPV_FPVL3 (0x1u << 19) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 3 */ |
| 4173 | /* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */ |
| 4174 | #define PWM_FPE_FPE0_Pos 0 |
| 4175 | #define PWM_FPE_FPE0_Msk (0xffu << PWM_FPE_FPE0_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 0 (fault input bit varies from 0 to 5) */ |
| 4176 | #define PWM_FPE_FPE0(value) ((PWM_FPE_FPE0_Msk & ((value) << PWM_FPE_FPE0_Pos))) |
| 4177 | #define PWM_FPE_FPE1_Pos 8 |
| 4178 | #define PWM_FPE_FPE1_Msk (0xffu << PWM_FPE_FPE1_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 1 (fault input bit varies from 0 to 5) */ |
| 4179 | #define PWM_FPE_FPE1(value) ((PWM_FPE_FPE1_Msk & ((value) << PWM_FPE_FPE1_Pos))) |
| 4180 | #define PWM_FPE_FPE2_Pos 16 |
| 4181 | #define PWM_FPE_FPE2_Msk (0xffu << PWM_FPE_FPE2_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 2 (fault input bit varies from 0 to 5) */ |
| 4182 | #define PWM_FPE_FPE2(value) ((PWM_FPE_FPE2_Msk & ((value) << PWM_FPE_FPE2_Pos))) |
| 4183 | #define PWM_FPE_FPE3_Pos 24 |
| 4184 | #define PWM_FPE_FPE3_Msk (0xffu << PWM_FPE_FPE3_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 3 (fault input bit varies from 0 to 5) */ |
| 4185 | #define PWM_FPE_FPE3(value) ((PWM_FPE_FPE3_Msk & ((value) << PWM_FPE_FPE3_Pos))) |
| 4186 | /* -------- PWM_EL0MR : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */ |
| 4187 | #define PWM_EL0MR_CSEL0 (0x1u << 0) /**< \brief (PWM_EL0MR) Comparison 0 Selection */ |
| 4188 | #define PWM_EL0MR_CSEL1 (0x1u << 1) /**< \brief (PWM_EL0MR) Comparison 1 Selection */ |
| 4189 | #define PWM_EL0MR_CSEL2 (0x1u << 2) /**< \brief (PWM_EL0MR) Comparison 2 Selection */ |
| 4190 | #define PWM_EL0MR_CSEL3 (0x1u << 3) /**< \brief (PWM_EL0MR) Comparison 3 Selection */ |
| 4191 | #define PWM_EL0MR_CSEL4 (0x1u << 4) /**< \brief (PWM_EL0MR) Comparison 4 Selection */ |
| 4192 | #define PWM_EL0MR_CSEL5 (0x1u << 5) /**< \brief (PWM_EL0MR) Comparison 5 Selection */ |
| 4193 | #define PWM_EL0MR_CSEL6 (0x1u << 6) /**< \brief (PWM_EL0MR) Comparison 6 Selection */ |
| 4194 | #define PWM_EL0MR_CSEL7 (0x1u << 7) /**< \brief (PWM_EL0MR) Comparison 7 Selection */ |
| 4195 | /* -------- PWM_EL1MR : (PWM Offset: 0x80) PWM Event Line 1 Mode Register -------- */ |
| 4196 | #define PWM_EL1MR_CSEL0 (0x1u << 0) /**< \brief (PWM_EL1MR) Comparison 0 Selection */ |
| 4197 | #define PWM_EL1MR_CSEL1 (0x1u << 1) /**< \brief (PWM_EL1MR) Comparison 1 Selection */ |
| 4198 | #define PWM_EL1MR_CSEL2 (0x1u << 2) /**< \brief (PWM_EL1MR) Comparison 2 Selection */ |
| 4199 | #define PWM_EL1MR_CSEL3 (0x1u << 3) /**< \brief (PWM_EL1MR) Comparison 3 Selection */ |
| 4200 | #define PWM_EL1MR_CSEL4 (0x1u << 4) /**< \brief (PWM_EL1MR) Comparison 4 Selection */ |
| 4201 | #define PWM_EL1MR_CSEL5 (0x1u << 5) /**< \brief (PWM_EL1MR) Comparison 5 Selection */ |
| 4202 | #define PWM_EL1MR_CSEL6 (0x1u << 6) /**< \brief (PWM_EL1MR) Comparison 6 Selection */ |
| 4203 | #define PWM_EL1MR_CSEL7 (0x1u << 7) /**< \brief (PWM_EL1MR) Comparison 7 Selection */ |
| 4204 | /* -------- PWM_SMMR : (PWM Offset: 0xB0) PWM Stepper Motor Mode Register -------- */ |
| 4205 | #define PWM_SMMR_GCEN0 (0x1u << 0) /**< \brief (PWM_SMMR) Gray Count ENable */ |
| 4206 | #define PWM_SMMR_GCEN1 (0x1u << 1) /**< \brief (PWM_SMMR) Gray Count ENable */ |
| 4207 | #define PWM_SMMR_DOWN0 (0x1u << 16) /**< \brief (PWM_SMMR) DOWN Count */ |
| 4208 | #define PWM_SMMR_DOWN1 (0x1u << 17) /**< \brief (PWM_SMMR) DOWN Count */ |
| 4209 | /* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protect Control Register -------- */ |
| 4210 | #define PWM_WPCR_WPCMD_Pos 0 |
| 4211 | #define PWM_WPCR_WPCMD_Msk (0x3u << PWM_WPCR_WPCMD_Pos) /**< \brief (PWM_WPCR) Write Protect Command */ |
| 4212 | #define PWM_WPCR_WPCMD(value) ((PWM_WPCR_WPCMD_Msk & ((value) << PWM_WPCR_WPCMD_Pos))) |
| 4213 | #define PWM_WPCR_WPRG0 (0x1u << 2) /**< \brief (PWM_WPCR) Write Protect Register Group 0 */ |
| 4214 | #define PWM_WPCR_WPRG1 (0x1u << 3) /**< \brief (PWM_WPCR) Write Protect Register Group 1 */ |
| 4215 | #define PWM_WPCR_WPRG2 (0x1u << 4) /**< \brief (PWM_WPCR) Write Protect Register Group 2 */ |
| 4216 | #define PWM_WPCR_WPRG3 (0x1u << 5) /**< \brief (PWM_WPCR) Write Protect Register Group 3 */ |
| 4217 | #define PWM_WPCR_WPRG4 (0x1u << 6) /**< \brief (PWM_WPCR) Write Protect Register Group 4 */ |
| 4218 | #define PWM_WPCR_WPRG5 (0x1u << 7) /**< \brief (PWM_WPCR) Write Protect Register Group 5 */ |
| 4219 | #define PWM_WPCR_WPKEY_Pos 8 |
| 4220 | #define PWM_WPCR_WPKEY_Msk (0xffffffu << PWM_WPCR_WPKEY_Pos) /**< \brief (PWM_WPCR) Write Protect Key */ |
| 4221 | #define PWM_WPCR_WPKEY(value) ((PWM_WPCR_WPKEY_Msk & ((value) << PWM_WPCR_WPKEY_Pos))) |
| 4222 | /* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protect Status Register -------- */ |
| 4223 | #define PWM_WPSR_WPSWS0 (0x1u << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */ |
| 4224 | #define PWM_WPSR_WPSWS1 (0x1u << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */ |
| 4225 | #define PWM_WPSR_WPSWS2 (0x1u << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */ |
| 4226 | #define PWM_WPSR_WPSWS3 (0x1u << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */ |
| 4227 | #define PWM_WPSR_WPSWS4 (0x1u << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */ |
| 4228 | #define PWM_WPSR_WPSWS5 (0x1u << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */ |
| 4229 | #define PWM_WPSR_WPVS (0x1u << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */ |
| 4230 | #define PWM_WPSR_WPHWS0 (0x1u << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */ |
| 4231 | #define PWM_WPSR_WPHWS1 (0x1u << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */ |
| 4232 | #define PWM_WPSR_WPHWS2 (0x1u << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */ |
| 4233 | #define PWM_WPSR_WPHWS3 (0x1u << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */ |
| 4234 | #define PWM_WPSR_WPHWS4 (0x1u << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */ |
| 4235 | #define PWM_WPSR_WPHWS5 (0x1u << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */ |
| 4236 | #define PWM_WPSR_WPVSRC_Pos 16 |
| 4237 | #define PWM_WPSR_WPVSRC_Msk (0xffffu << PWM_WPSR_WPVSRC_Pos) /**< \brief (PWM_WPSR) Write Protect Violation Source */ |
| 4238 | /* -------- PWM_RPR : (PWM Offset: 0x100) Receive Pointer Register -------- */ |
| 4239 | #define PWM_RPR_RXPTR_Pos 0 |
| 4240 | #define PWM_RPR_RXPTR_Msk (0xffffffffu << PWM_RPR_RXPTR_Pos) /**< \brief (PWM_RPR) Receive Pointer Register */ |
| 4241 | #define PWM_RPR_RXPTR(value) ((PWM_RPR_RXPTR_Msk & ((value) << PWM_RPR_RXPTR_Pos))) |
| 4242 | /* -------- PWM_RCR : (PWM Offset: 0x104) Receive Counter Register -------- */ |
| 4243 | #define PWM_RCR_RXCTR_Pos 0 |
| 4244 | #define PWM_RCR_RXCTR_Msk (0xffffu << PWM_RCR_RXCTR_Pos) /**< \brief (PWM_RCR) Receive Counter Register */ |
| 4245 | #define PWM_RCR_RXCTR(value) ((PWM_RCR_RXCTR_Msk & ((value) << PWM_RCR_RXCTR_Pos))) |
| 4246 | /* -------- PWM_TPR : (PWM Offset: 0x108) Transmit Pointer Register -------- */ |
| 4247 | #define PWM_TPR_TXPTR_Pos 0 |
| 4248 | #define PWM_TPR_TXPTR_Msk (0xffffffffu << PWM_TPR_TXPTR_Pos) /**< \brief (PWM_TPR) Transmit Counter Register */ |
| 4249 | #define PWM_TPR_TXPTR(value) ((PWM_TPR_TXPTR_Msk & ((value) << PWM_TPR_TXPTR_Pos))) |
| 4250 | /* -------- PWM_TCR : (PWM Offset: 0x10C) Transmit Counter Register -------- */ |
| 4251 | #define PWM_TCR_TXCTR_Pos 0 |
| 4252 | #define PWM_TCR_TXCTR_Msk (0xffffu << PWM_TCR_TXCTR_Pos) /**< \brief (PWM_TCR) Transmit Counter Register */ |
| 4253 | #define PWM_TCR_TXCTR(value) ((PWM_TCR_TXCTR_Msk & ((value) << PWM_TCR_TXCTR_Pos))) |
| 4254 | /* -------- PWM_RNPR : (PWM Offset: 0x110) Receive Next Pointer Register -------- */ |
| 4255 | #define PWM_RNPR_RXNPTR_Pos 0 |
| 4256 | #define PWM_RNPR_RXNPTR_Msk (0xffffffffu << PWM_RNPR_RXNPTR_Pos) /**< \brief (PWM_RNPR) Receive Next Pointer */ |
| 4257 | #define PWM_RNPR_RXNPTR(value) ((PWM_RNPR_RXNPTR_Msk & ((value) << PWM_RNPR_RXNPTR_Pos))) |
| 4258 | /* -------- PWM_RNCR : (PWM Offset: 0x114) Receive Next Counter Register -------- */ |
| 4259 | #define PWM_RNCR_RXNCTR_Pos 0 |
| 4260 | #define PWM_RNCR_RXNCTR_Msk (0xffffu << PWM_RNCR_RXNCTR_Pos) /**< \brief (PWM_RNCR) Receive Next Counter */ |
| 4261 | #define PWM_RNCR_RXNCTR(value) ((PWM_RNCR_RXNCTR_Msk & ((value) << PWM_RNCR_RXNCTR_Pos))) |
| 4262 | /* -------- PWM_TNPR : (PWM Offset: 0x118) Transmit Next Pointer Register -------- */ |
| 4263 | #define PWM_TNPR_TXNPTR_Pos 0 |
| 4264 | #define PWM_TNPR_TXNPTR_Msk (0xffffffffu << PWM_TNPR_TXNPTR_Pos) /**< \brief (PWM_TNPR) Transmit Next Pointer */ |
| 4265 | #define PWM_TNPR_TXNPTR(value) ((PWM_TNPR_TXNPTR_Msk & ((value) << PWM_TNPR_TXNPTR_Pos))) |
| 4266 | /* -------- PWM_TNCR : (PWM Offset: 0x11C) Transmit Next Counter Register -------- */ |
| 4267 | #define PWM_TNCR_TXNCTR_Pos 0 |
| 4268 | #define PWM_TNCR_TXNCTR_Msk (0xffffu << PWM_TNCR_TXNCTR_Pos) /**< \brief (PWM_TNCR) Transmit Counter Next */ |
| 4269 | #define PWM_TNCR_TXNCTR(value) ((PWM_TNCR_TXNCTR_Msk & ((value) << PWM_TNCR_TXNCTR_Pos))) |
| 4270 | /* -------- PWM_PTCR : (PWM Offset: 0x120) Transfer Control Register -------- */ |
| 4271 | #define PWM_PTCR_RXTEN (0x1u << 0) /**< \brief (PWM_PTCR) Receiver Transfer Enable */ |
| 4272 | #define PWM_PTCR_RXTDIS (0x1u << 1) /**< \brief (PWM_PTCR) Receiver Transfer Disable */ |
| 4273 | #define PWM_PTCR_TXTEN (0x1u << 8) /**< \brief (PWM_PTCR) Transmitter Transfer Enable */ |
| 4274 | #define PWM_PTCR_TXTDIS (0x1u << 9) /**< \brief (PWM_PTCR) Transmitter Transfer Disable */ |
| 4275 | /* -------- PWM_PTSR : (PWM Offset: 0x124) Transfer Status Register -------- */ |
| 4276 | #define PWM_PTSR_RXTEN (0x1u << 0) /**< \brief (PWM_PTSR) Receiver Transfer Enable */ |
| 4277 | #define PWM_PTSR_TXTEN (0x1u << 8) /**< \brief (PWM_PTSR) Transmitter Transfer Enable */ |
| 4278 | /* -------- PWM_CMPxV : (PWM Offset: N/A) PWM Comparison 0 Value Register -------- */ |
| 4279 | #define PWM_CMPxV_CV_Pos 0 |
| 4280 | #define PWM_CMPxV_CV_Msk (0xffffffu << PWM_CMPxV_CV_Pos) /**< \brief (PWM_CMPxV) Comparison x Value */ |
| 4281 | #define PWM_CMPxV_CV(value) ((PWM_CMPxV_CV_Msk & ((value) << PWM_CMPxV_CV_Pos))) |
| 4282 | #define PWM_CMPxV_CVM (0x1u << 24) /**< \brief (PWM_CMPxV) Comparison x Value Mode */ |
| 4283 | /* -------- PWM_CMPxVUPD : (PWM Offset: N/A) PWM Comparison 0 Value Update Register -------- */ |
| 4284 | #define PWM_CMPxVUPD_CVUPD_Pos 0 |
| 4285 | #define PWM_CMPxVUPD_CVUPD_Msk (0xffffffu << PWM_CMPxVUPD_CVUPD_Pos) /**< \brief (PWM_CMPxVUPD) Comparison x Value Update */ |
| 4286 | #define PWM_CMPxVUPD_CVUPD(value) ((PWM_CMPxVUPD_CVUPD_Msk & ((value) << PWM_CMPxVUPD_CVUPD_Pos))) |
| 4287 | #define PWM_CMPxVUPD_CVMUPD (0x1u << 24) /**< \brief (PWM_CMPxVUPD) Comparison x Value Mode Update */ |
| 4288 | /* -------- PWM_CMPxM : (PWM Offset: N/A) PWM Comparison 0 Mode Register -------- */ |
| 4289 | #define PWM_CMPxM_CEN (0x1u << 0) /**< \brief (PWM_CMPxM) Comparison x Enable */ |
| 4290 | #define PWM_CMPxM_CTR_Pos 4 |
| 4291 | #define PWM_CMPxM_CTR_Msk (0xfu << PWM_CMPxM_CTR_Pos) /**< \brief (PWM_CMPxM) Comparison x Trigger */ |
| 4292 | #define PWM_CMPxM_CTR(value) ((PWM_CMPxM_CTR_Msk & ((value) << PWM_CMPxM_CTR_Pos))) |
| 4293 | #define PWM_CMPxM_CPR_Pos 8 |
| 4294 | #define PWM_CMPxM_CPR_Msk (0xfu << PWM_CMPxM_CPR_Pos) /**< \brief (PWM_CMPxM) Comparison x Period */ |
| 4295 | #define PWM_CMPxM_CPR(value) ((PWM_CMPxM_CPR_Msk & ((value) << PWM_CMPxM_CPR_Pos))) |
| 4296 | #define PWM_CMPxM_CPRCNT_Pos 12 |
| 4297 | #define PWM_CMPxM_CPRCNT_Msk (0xfu << PWM_CMPxM_CPRCNT_Pos) /**< \brief (PWM_CMPxM) Comparison x Period Counter */ |
| 4298 | #define PWM_CMPxM_CPRCNT(value) ((PWM_CMPxM_CPRCNT_Msk & ((value) << PWM_CMPxM_CPRCNT_Pos))) |
| 4299 | #define PWM_CMPxM_CUPR_Pos 16 |
| 4300 | #define PWM_CMPxM_CUPR_Msk (0xfu << PWM_CMPxM_CUPR_Pos) /**< \brief (PWM_CMPxM) Comparison x Update Period */ |
| 4301 | #define PWM_CMPxM_CUPR(value) ((PWM_CMPxM_CUPR_Msk & ((value) << PWM_CMPxM_CUPR_Pos))) |
| 4302 | #define PWM_CMPxM_CUPRCNT_Pos 20 |
| 4303 | #define PWM_CMPxM_CUPRCNT_Msk (0xfu << PWM_CMPxM_CUPRCNT_Pos) /**< \brief (PWM_CMPxM) Comparison x Update Period Counter */ |
| 4304 | #define PWM_CMPxM_CUPRCNT(value) ((PWM_CMPxM_CUPRCNT_Msk & ((value) << PWM_CMPxM_CUPRCNT_Pos))) |
| 4305 | /* -------- PWM_CMPxMUPD : (PWM Offset: N/A) PWM Comparison 0 Mode Update Register -------- */ |
| 4306 | #define PWM_CMPxMUPD_CENUPD (0x1u << 0) /**< \brief (PWM_CMPxMUPD) Comparison x Enable Update */ |
| 4307 | #define PWM_CMPxMUPD_CTRUPD_Pos 4 |
| 4308 | #define PWM_CMPxMUPD_CTRUPD_Msk (0xfu << PWM_CMPxMUPD_CTRUPD_Pos) /**< \brief (PWM_CMPxMUPD) Comparison x Trigger Update */ |
| 4309 | #define PWM_CMPxMUPD_CTRUPD(value) ((PWM_CMPxMUPD_CTRUPD_Msk & ((value) << PWM_CMPxMUPD_CTRUPD_Pos))) |
| 4310 | #define PWM_CMPxMUPD_CPRUPD_Pos 8 |
| 4311 | #define PWM_CMPxMUPD_CPRUPD_Msk (0xfu << PWM_CMPxMUPD_CPRUPD_Pos) /**< \brief (PWM_CMPxMUPD) Comparison x Period Update */ |
| 4312 | #define PWM_CMPxMUPD_CPRUPD(value) ((PWM_CMPxMUPD_CPRUPD_Msk & ((value) << PWM_CMPxMUPD_CPRUPD_Pos))) |
| 4313 | #define PWM_CMPxMUPD_CUPRUPD_Pos 16 |
| 4314 | #define PWM_CMPxMUPD_CUPRUPD_Msk (0xfu << PWM_CMPxMUPD_CUPRUPD_Pos) /**< \brief (PWM_CMPxMUPD) Comparison x Update Period Update */ |
| 4315 | #define PWM_CMPxMUPD_CUPRUPD(value) ((PWM_CMPxMUPD_CUPRUPD_Msk & ((value) << PWM_CMPxMUPD_CUPRUPD_Pos))) |
| 4316 | /* -------- PWM_CMR : (PWM Offset: N/A) PWM Channel Mode Register -------- */ |
| 4317 | #define PWM_CMR_CPRE_Pos 0 |
| 4318 | #define PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos) /**< \brief (PWM_CMR) Channel Pre-scaler */ |
| 4319 | #define PWM_CMR_CPRE_MCK (0x0u << 0) /**< \brief (PWM_CMR) MCK */ |
| 4320 | #define PWM_CMR_CPRE_MCK_DIV_2 (0x1u << 0) /**< \brief (PWM_CMR) MCK/2 */ |
| 4321 | #define PWM_CMR_CPRE_MCK_DIV_4 (0x2u << 0) /**< \brief (PWM_CMR) MCK/4 */ |
| 4322 | #define PWM_CMR_CPRE_MCK_DIV_8 (0x3u << 0) /**< \brief (PWM_CMR) MCK/8 */ |
| 4323 | #define PWM_CMR_CPRE_MCK_DIV_16 (0x4u << 0) /**< \brief (PWM_CMR) MCK/16 */ |
| 4324 | #define PWM_CMR_CPRE_MCK_DIV_32 (0x5u << 0) /**< \brief (PWM_CMR) MCK/32 */ |
| 4325 | #define PWM_CMR_CPRE_MCK_DIV_64 (0x6u << 0) /**< \brief (PWM_CMR) MCK/64 */ |
| 4326 | #define PWM_CMR_CPRE_MCK_DIV_128 (0x7u << 0) /**< \brief (PWM_CMR) MCK/128 */ |
| 4327 | #define PWM_CMR_CPRE_MCK_DIV_256 (0x8u << 0) /**< \brief (PWM_CMR) MCK/256 */ |
| 4328 | #define PWM_CMR_CPRE_MCK_DIV_512 (0x9u << 0) /**< \brief (PWM_CMR) MCK/512 */ |
| 4329 | #define PWM_CMR_CPRE_MCK_DIV_1024 (0xAu << 0) /**< \brief (PWM_CMR) MCK/1024 */ |
| 4330 | #define PWM_CMR_CPRE_CKA (0xBu << 0) /**< \brief (PWM_CMR) CLKA */ |
| 4331 | #define PWM_CMR_CPRE_CKB (0xCu << 0) /**< \brief (PWM_CMR) CLKB */ |
| 4332 | #define PWM_CMR_CALG (0x1u << 8) /**< \brief (PWM_CMR) Channel Alignment */ |
| 4333 | #define PWM_CMR_CPOL (0x1u << 9) /**< \brief (PWM_CMR) Channel Polarity */ |
| 4334 | #define PWM_CMR_CES (0x1u << 10) /**< \brief (PWM_CMR) Counter Event Selection */ |
| 4335 | #define PWM_CMR_DTE (0x1u << 16) /**< \brief (PWM_CMR) Dead-Time Generator Enable */ |
| 4336 | #define PWM_CMR_DTHI (0x1u << 17) /**< \brief (PWM_CMR) Dead-Time PWMHx Output Inverted */ |
| 4337 | #define PWM_CMR_DTLI (0x1u << 18) /**< \brief (PWM_CMR) Dead-Time PWMLx Output Inverted */ |
| 4338 | /* -------- PWM_CDTY : (PWM Offset: N/A) PWM Channel Duty Cycle Register -------- */ |
| 4339 | #define PWM_CDTY_CDTY_Pos 0 |
| 4340 | #define PWM_CDTY_CDTY_Msk (0xffffffu << PWM_CDTY_CDTY_Pos) /**< \brief (PWM_CDTY) Channel Duty-Cycle */ |
| 4341 | #define PWM_CDTY_CDTY(value) ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos))) |
| 4342 | /* -------- PWM_CDTYUPD : (PWM Offset: N/A) PWM Channel Duty Cycle Update Register -------- */ |
| 4343 | #define PWM_CDTYUPD_CDTYUPD_Pos 0 |
| 4344 | #define PWM_CDTYUPD_CDTYUPD_Msk (0xffffffu << PWM_CDTYUPD_CDTYUPD_Pos) /**< \brief (PWM_CDTYUPD) Channel Duty-Cycle Update */ |
| 4345 | #define PWM_CDTYUPD_CDTYUPD(value) ((PWM_CDTYUPD_CDTYUPD_Msk & ((value) << PWM_CDTYUPD_CDTYUPD_Pos))) |
| 4346 | /* -------- PWM_CPRD : (PWM Offset: N/A) PWM Channel Period Register -------- */ |
| 4347 | #define PWM_CPRD_CPRD_Pos 0 |
| 4348 | #define PWM_CPRD_CPRD_Msk (0xffffffu << PWM_CPRD_CPRD_Pos) /**< \brief (PWM_CPRD) Channel Period */ |
| 4349 | #define PWM_CPRD_CPRD(value) ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos))) |
| 4350 | /* -------- PWM_CPRDUPD : (PWM Offset: N/A) PWM Channel Period Update Register -------- */ |
| 4351 | #define PWM_CPRDUPD_CPRDUPD_Pos 0 |
| 4352 | #define PWM_CPRDUPD_CPRDUPD_Msk (0xffffffu << PWM_CPRDUPD_CPRDUPD_Pos) /**< \brief (PWM_CPRDUPD) Channel Period Update */ |
| 4353 | #define PWM_CPRDUPD_CPRDUPD(value) ((PWM_CPRDUPD_CPRDUPD_Msk & ((value) << PWM_CPRDUPD_CPRDUPD_Pos))) |
| 4354 | /* -------- PWM_CCNT : (PWM Offset: N/A) PWM Channel Counter Register -------- */ |
| 4355 | #define PWM_CCNT_CNT_Pos 0 |
| 4356 | #define PWM_CCNT_CNT_Msk (0xffffffu << PWM_CCNT_CNT_Pos) /**< \brief (PWM_CCNT) Channel Counter Register */ |
| 4357 | /* -------- PWM_DT : (PWM Offset: N/A) PWM Channel Dead Time Register -------- */ |
| 4358 | #define PWM_DT_DTH_Pos 0 |
| 4359 | #define PWM_DT_DTH_Msk (0xffffu << PWM_DT_DTH_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMHx Output */ |
| 4360 | #define PWM_DT_DTH(value) ((PWM_DT_DTH_Msk & ((value) << PWM_DT_DTH_Pos))) |
| 4361 | #define PWM_DT_DTL_Pos 16 |
| 4362 | #define PWM_DT_DTL_Msk (0xffffu << PWM_DT_DTL_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMLx Output */ |
| 4363 | #define PWM_DT_DTL(value) ((PWM_DT_DTL_Msk & ((value) << PWM_DT_DTL_Pos))) |
| 4364 | /* -------- PWM_DTUPD : (PWM Offset: N/A) PWM Channel Dead Time Update Register -------- */ |
| 4365 | #define PWM_DTUPD_DTHUPD_Pos 0 |
| 4366 | #define PWM_DTUPD_DTHUPD_Msk (0xffffu << PWM_DTUPD_DTHUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMHx Output */ |
| 4367 | #define PWM_DTUPD_DTHUPD(value) ((PWM_DTUPD_DTHUPD_Msk & ((value) << PWM_DTUPD_DTHUPD_Pos))) |
| 4368 | #define PWM_DTUPD_DTLUPD_Pos 16 |
| 4369 | #define PWM_DTUPD_DTLUPD_Msk (0xffffu << PWM_DTUPD_DTLUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMLx Output */ |
| 4370 | #define PWM_DTUPD_DTLUPD(value) ((PWM_DTUPD_DTLUPD_Msk & ((value) << PWM_DTUPD_DTLUPD_Pos))) |
| 4371 | |
| 4372 | /*@}*/ |
| 4373 | |
| 4374 | /* ============================================================================= */ |
| 4375 | /** SOFTWARE API DEFINITION FOR Reset Controller */ |
| 4376 | /* ============================================================================= */ |
| 4377 | /** \addtogroup SAM3S_RSTC Reset Controller */ |
| 4378 | /*@{*/ |
| 4379 | |
| 4380 | #ifndef __ASSEMBLY__ |
| 4381 | /** \brief Rstc hardware registers */ |
| 4382 | typedef struct { |
| 4383 | WoReg RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */ |
| 4384 | RoReg RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */ |
| 4385 | RwReg RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */ |
| 4386 | } Rstc; |
| 4387 | #endif /* __ASSEMBLY__ */ |
| 4388 | /* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */ |
| 4389 | #define RSTC_CR_PROCRST (0x1u << 0) /**< \brief (RSTC_CR) Processor Reset */ |
| 4390 | #define RSTC_CR_PERRST (0x1u << 2) /**< \brief (RSTC_CR) Peripheral Reset */ |
| 4391 | #define RSTC_CR_EXTRST (0x1u << 3) /**< \brief (RSTC_CR) External Reset */ |
| 4392 | #define RSTC_CR_KEY_Pos 24 |
| 4393 | #define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) /**< \brief (RSTC_CR) Password */ |
| 4394 | #define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos))) |
| 4395 | /* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */ |
| 4396 | #define RSTC_SR_URSTS (0x1u << 0) /**< \brief (RSTC_SR) User Reset Status */ |
| 4397 | #define RSTC_SR_RSTTYP_Pos 8 |
| 4398 | #define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) /**< \brief (RSTC_SR) Reset Type */ |
| 4399 | #define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */ |
| 4400 | #define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */ |
| 4401 | /* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */ |
| 4402 | #define RSTC_MR_URSTEN (0x1u << 0) /**< \brief (RSTC_MR) User Reset Enable */ |
| 4403 | #define RSTC_MR_URSTIEN (0x1u << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */ |
| 4404 | #define RSTC_MR_ERSTL_Pos 8 |
| 4405 | #define RSTC_MR_ERSTL_Msk (0xfu << RSTC_MR_ERSTL_Pos) /**< \brief (RSTC_MR) External Reset Length */ |
| 4406 | #define RSTC_MR_ERSTL(value) ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos))) |
| 4407 | #define RSTC_MR_KEY_Pos 24 |
| 4408 | #define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) /**< \brief (RSTC_MR) Password */ |
| 4409 | #define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos))) |
| 4410 | |
| 4411 | /*@}*/ |
| 4412 | |
| 4413 | /* ============================================================================= */ |
| 4414 | /** SOFTWARE API DEFINITION FOR Real-time Clock */ |
| 4415 | /* ============================================================================= */ |
| 4416 | /** \addtogroup SAM3S_RTC Real-time Clock */ |
| 4417 | /*@{*/ |
| 4418 | |
| 4419 | #ifndef __ASSEMBLY__ |
| 4420 | /** \brief Rtc hardware registers */ |
| 4421 | typedef struct { |
| 4422 | RwReg RTC_CR; /**< \brief (Rtc Offset: 0x00) Control Register */ |
| 4423 | RwReg RTC_MR; /**< \brief (Rtc Offset: 0x04) Mode Register */ |
| 4424 | RwReg RTC_TIMR; /**< \brief (Rtc Offset: 0x08) Time Register */ |
| 4425 | RwReg RTC_CALR; /**< \brief (Rtc Offset: 0x0C) Calendar Register */ |
| 4426 | RwReg RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */ |
| 4427 | RwReg RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */ |
| 4428 | RoReg RTC_SR; /**< \brief (Rtc Offset: 0x18) Status Register */ |
| 4429 | WoReg RTC_SCCR; /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */ |
| 4430 | WoReg RTC_IER; /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */ |
| 4431 | WoReg RTC_IDR; /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */ |
| 4432 | RoReg RTC_IMR; /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */ |
| 4433 | RoReg RTC_VER; /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */ |
| 4434 | } Rtc; |
| 4435 | #endif /* __ASSEMBLY__ */ |
| 4436 | /* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */ |
| 4437 | #define RTC_CR_UPDTIM (0x1u << 0) /**< \brief (RTC_CR) Update Request Time Register */ |
| 4438 | #define RTC_CR_UPDCAL (0x1u << 1) /**< \brief (RTC_CR) Update Request Calendar Register */ |
| 4439 | #define RTC_CR_TIMEVSEL_Pos 8 |
| 4440 | #define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos) /**< \brief (RTC_CR) Time Event Selection */ |
| 4441 | #define RTC_CR_TIMEVSEL_MINUTE (0x0u << 8) /**< \brief (RTC_CR) Minute change */ |
| 4442 | #define RTC_CR_TIMEVSEL_HOUR (0x1u << 8) /**< \brief (RTC_CR) Hour change */ |
| 4443 | #define RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8) /**< \brief (RTC_CR) Every day at midnight */ |
| 4444 | #define RTC_CR_TIMEVSEL_NOON (0x3u << 8) /**< \brief (RTC_CR) Every day at noon */ |
| 4445 | #define RTC_CR_CALEVSEL_Pos 16 |
| 4446 | #define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos) /**< \brief (RTC_CR) Calendar Event Selection */ |
| 4447 | #define RTC_CR_CALEVSEL_WEEK (0x0u << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00) */ |
| 4448 | #define RTC_CR_CALEVSEL_MONTH (0x1u << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00) */ |
| 4449 | #define RTC_CR_CALEVSEL_YEAR (0x2u << 16) /**< \brief (RTC_CR) Year change (every January 1 at time 00:00:00) */ |
| 4450 | /* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */ |
| 4451 | #define RTC_MR_HRMOD (0x1u << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */ |
| 4452 | /* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */ |
| 4453 | #define RTC_TIMR_SEC_Pos 0 |
| 4454 | #define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos) /**< \brief (RTC_TIMR) Current Second */ |
| 4455 | #define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos))) |
| 4456 | #define RTC_TIMR_MIN_Pos 8 |
| 4457 | #define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos) /**< \brief (RTC_TIMR) Current Minute */ |
| 4458 | #define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos))) |
| 4459 | #define RTC_TIMR_HOUR_Pos 16 |
| 4460 | #define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos) /**< \brief (RTC_TIMR) Current Hour */ |
| 4461 | #define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos))) |
| 4462 | #define RTC_TIMR_AMPM (0x1u << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */ |
| 4463 | /* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */ |
| 4464 | #define RTC_CALR_CENT_Pos 0 |
| 4465 | #define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos) /**< \brief (RTC_CALR) Current Century */ |
| 4466 | #define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos))) |
| 4467 | #define RTC_CALR_YEAR_Pos 8 |
| 4468 | #define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos) /**< \brief (RTC_CALR) Current Year */ |
| 4469 | #define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos))) |
| 4470 | #define RTC_CALR_MONTH_Pos 16 |
| 4471 | #define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos) /**< \brief (RTC_CALR) Current Month */ |
| 4472 | #define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos))) |
| 4473 | #define RTC_CALR_DAY_Pos 21 |
| 4474 | #define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos) /**< \brief (RTC_CALR) Current Day in Current Week */ |
| 4475 | #define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos))) |
| 4476 | #define RTC_CALR_DATE_Pos 24 |
| 4477 | #define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos) /**< \brief (RTC_CALR) Current Day in Current Month */ |
| 4478 | #define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos))) |
| 4479 | /* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */ |
| 4480 | #define RTC_TIMALR_SEC_Pos 0 |
| 4481 | #define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos) /**< \brief (RTC_TIMALR) Second Alarm */ |
| 4482 | #define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos))) |
| 4483 | #define RTC_TIMALR_SECEN (0x1u << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */ |
| 4484 | #define RTC_TIMALR_MIN_Pos 8 |
| 4485 | #define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos) /**< \brief (RTC_TIMALR) Minute Alarm */ |
| 4486 | #define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos))) |
| 4487 | #define RTC_TIMALR_MINEN (0x1u << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */ |
| 4488 | #define RTC_TIMALR_HOUR_Pos 16 |
| 4489 | #define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos) /**< \brief (RTC_TIMALR) Hour Alarm */ |
| 4490 | #define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos))) |
| 4491 | #define RTC_TIMALR_AMPM (0x1u << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */ |
| 4492 | #define RTC_TIMALR_HOUREN (0x1u << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */ |
| 4493 | /* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */ |
| 4494 | #define RTC_CALALR_MONTH_Pos 16 |
| 4495 | #define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos) /**< \brief (RTC_CALALR) Month Alarm */ |
| 4496 | #define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos))) |
| 4497 | #define RTC_CALALR_MTHEN (0x1u << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */ |
| 4498 | #define RTC_CALALR_DATE_Pos 24 |
| 4499 | #define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos) /**< \brief (RTC_CALALR) Date Alarm */ |
| 4500 | #define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos))) |
| 4501 | #define RTC_CALALR_DATEEN (0x1u << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */ |
| 4502 | /* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */ |
| 4503 | #define RTC_SR_ACKUPD (0x1u << 0) /**< \brief (RTC_SR) Acknowledge for Update */ |
| 4504 | #define RTC_SR_ALARM (0x1u << 1) /**< \brief (RTC_SR) Alarm Flag */ |
| 4505 | #define RTC_SR_SEC (0x1u << 2) /**< \brief (RTC_SR) Second Event */ |
| 4506 | #define RTC_SR_TIMEV (0x1u << 3) /**< \brief (RTC_SR) Time Event */ |
| 4507 | #define RTC_SR_CALEV (0x1u << 4) /**< \brief (RTC_SR) Calendar Event */ |
| 4508 | /* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */ |
| 4509 | #define RTC_SCCR_ACKCLR (0x1u << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */ |
| 4510 | #define RTC_SCCR_ALRCLR (0x1u << 1) /**< \brief (RTC_SCCR) Alarm Clear */ |
| 4511 | #define RTC_SCCR_SECCLR (0x1u << 2) /**< \brief (RTC_SCCR) Second Clear */ |
| 4512 | #define RTC_SCCR_TIMCLR (0x1u << 3) /**< \brief (RTC_SCCR) Time Clear */ |
| 4513 | #define RTC_SCCR_CALCLR (0x1u << 4) /**< \brief (RTC_SCCR) Calendar Clear */ |
| 4514 | /* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */ |
| 4515 | #define RTC_IER_ACKEN (0x1u << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */ |
| 4516 | #define RTC_IER_ALREN (0x1u << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */ |
| 4517 | #define RTC_IER_SECEN (0x1u << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */ |
| 4518 | #define RTC_IER_TIMEN (0x1u << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */ |
| 4519 | #define RTC_IER_CALEN (0x1u << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */ |
| 4520 | /* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */ |
| 4521 | #define RTC_IDR_ACKDIS (0x1u << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */ |
| 4522 | #define RTC_IDR_ALRDIS (0x1u << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */ |
| 4523 | #define RTC_IDR_SECDIS (0x1u << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */ |
| 4524 | #define RTC_IDR_TIMDIS (0x1u << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */ |
| 4525 | #define RTC_IDR_CALDIS (0x1u << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */ |
| 4526 | /* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */ |
| 4527 | #define RTC_IMR_ACK (0x1u << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */ |
| 4528 | #define RTC_IMR_ALR (0x1u << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */ |
| 4529 | #define RTC_IMR_SEC (0x1u << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */ |
| 4530 | #define RTC_IMR_TIM (0x1u << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */ |
| 4531 | #define RTC_IMR_CAL (0x1u << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */ |
| 4532 | /* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */ |
| 4533 | #define RTC_VER_NVTIM (0x1u << 0) /**< \brief (RTC_VER) Non-valid Time */ |
| 4534 | #define RTC_VER_NVCAL (0x1u << 1) /**< \brief (RTC_VER) Non-valid Calendar */ |
| 4535 | #define RTC_VER_NVTIMALR (0x1u << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */ |
| 4536 | #define RTC_VER_NVCALALR (0x1u << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */ |
| 4537 | |
| 4538 | /*@}*/ |
| 4539 | |
| 4540 | /* ============================================================================= */ |
| 4541 | /** SOFTWARE API DEFINITION FOR Real-time Timer */ |
| 4542 | /* ============================================================================= */ |
| 4543 | /** \addtogroup SAM3S_RTT Real-time Timer */ |
| 4544 | /*@{*/ |
| 4545 | |
| 4546 | #ifndef __ASSEMBLY__ |
| 4547 | /** \brief Rtt hardware registers */ |
| 4548 | typedef struct { |
| 4549 | RwReg RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */ |
| 4550 | RwReg RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */ |
| 4551 | RoReg RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */ |
| 4552 | RoReg RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */ |
| 4553 | } Rtt; |
| 4554 | #endif /* __ASSEMBLY__ */ |
| 4555 | /* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */ |
| 4556 | #define RTT_MR_RTPRES_Pos 0 |
| 4557 | #define RTT_MR_RTPRES_Msk (0xffffu << RTT_MR_RTPRES_Pos) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */ |
| 4558 | #define RTT_MR_RTPRES(value) ((RTT_MR_RTPRES_Msk & ((value) << RTT_MR_RTPRES_Pos))) |
| 4559 | #define RTT_MR_ALMIEN (0x1u << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */ |
| 4560 | #define RTT_MR_RTTINCIEN (0x1u << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */ |
| 4561 | #define RTT_MR_RTTRST (0x1u << 18) /**< \brief (RTT_MR) Real-time Timer Restart */ |
| 4562 | /* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */ |
| 4563 | #define RTT_AR_ALMV_Pos 0 |
| 4564 | #define RTT_AR_ALMV_Msk (0xffffffffu << RTT_AR_ALMV_Pos) /**< \brief (RTT_AR) Alarm Value */ |
| 4565 | #define RTT_AR_ALMV(value) ((RTT_AR_ALMV_Msk & ((value) << RTT_AR_ALMV_Pos))) |
| 4566 | /* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */ |
| 4567 | #define RTT_VR_CRTV_Pos 0 |
| 4568 | #define RTT_VR_CRTV_Msk (0xffffffffu << RTT_VR_CRTV_Pos) /**< \brief (RTT_VR) Current Real-time Value */ |
| 4569 | /* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */ |
| 4570 | #define RTT_SR_ALMS (0x1u << 0) /**< \brief (RTT_SR) Real-time Alarm Status */ |
| 4571 | #define RTT_SR_RTTINC (0x1u << 1) /**< \brief (RTT_SR) Real-time Timer Increment */ |
| 4572 | |
| 4573 | /*@}*/ |
| 4574 | |
| 4575 | /* ============================================================================= */ |
| 4576 | /** SOFTWARE API DEFINITION FOR Static Memory Controller */ |
| 4577 | /* ============================================================================= */ |
| 4578 | /** \addtogroup SAM3S_SMC Static Memory Controller */ |
| 4579 | /*@{*/ |
| 4580 | |
| 4581 | #ifndef __ASSEMBLY__ |
| 4582 | /** \brief SmcCs_number hardware registers */ |
| 4583 | typedef struct { |
| 4584 | RwReg SMC_SETUP; /**< \brief (SmcCs_number Offset: 0x0) SMC Setup Register */ |
| 4585 | RwReg SMC_PULSE; /**< \brief (SmcCs_number Offset: 0x4) SMC Pulse Register */ |
| 4586 | RwReg SMC_CYCLE; /**< \brief (SmcCs_number Offset: 0x8) SMC Cycle Register */ |
| 4587 | RwReg SMC_MODE; /**< \brief (SmcCs_number Offset: 0xC) SMC Mode Register */ |
| 4588 | } SmcCs_number; |
| 4589 | /** \brief Smc hardware registers */ |
| 4590 | typedef struct { |
| 4591 | SmcCs_number SMC_CS_NUMBER[5]; /**< \brief (Smc Offset: 0x0) CS_number = 0 .. 4 */ |
| 4592 | RwReg Reserved1[12]; |
| 4593 | RwReg SMC_OCMS; /**< \brief (Smc Offset: 0x80) SMC OCMS MODE Register */ |
| 4594 | WoReg SMC_KEY1; /**< \brief (Smc Offset: 0x84) SMC OCMS KEY1 Register */ |
| 4595 | WoReg SMC_KEY2; /**< \brief (Smc Offset: 0x88) SMC OCMS KEY2 Register */ |
| 4596 | RwReg Reserved2[22]; |
| 4597 | RwReg SMC_WPMR; /**< \brief (Smc Offset: 0xE4) SMC Write Protect Mode Register */ |
| 4598 | RoReg SMC_WPSR; /**< \brief (Smc Offset: 0xE8) SMC Write Protect Status Register */ |
| 4599 | } Smc; |
| 4600 | #endif /* __ASSEMBLY__ */ |
| 4601 | /* -------- SMC_SETUP : (SMC Offset: N/A) SMC Setup Register -------- */ |
| 4602 | #define SMC_SETUP_NWE_SETUP_Pos 0 |
| 4603 | #define SMC_SETUP_NWE_SETUP_Msk (0x3fu << SMC_SETUP_NWE_SETUP_Pos) /**< \brief (SMC_SETUP) NWE Setup Length */ |
| 4604 | #define SMC_SETUP_NWE_SETUP(value) ((SMC_SETUP_NWE_SETUP_Msk & ((value) << SMC_SETUP_NWE_SETUP_Pos))) |
| 4605 | #define SMC_SETUP_NCS_WR_SETUP_Pos 8 |
| 4606 | #define SMC_SETUP_NCS_WR_SETUP_Msk (0x3fu << SMC_SETUP_NCS_WR_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in WRITE Access */ |
| 4607 | #define SMC_SETUP_NCS_WR_SETUP(value) ((SMC_SETUP_NCS_WR_SETUP_Msk & ((value) << SMC_SETUP_NCS_WR_SETUP_Pos))) |
| 4608 | #define SMC_SETUP_NRD_SETUP_Pos 16 |
| 4609 | #define SMC_SETUP_NRD_SETUP_Msk (0x3fu << SMC_SETUP_NRD_SETUP_Pos) /**< \brief (SMC_SETUP) NRD Setup Length */ |
| 4610 | #define SMC_SETUP_NRD_SETUP(value) ((SMC_SETUP_NRD_SETUP_Msk & ((value) << SMC_SETUP_NRD_SETUP_Pos))) |
| 4611 | #define SMC_SETUP_NCS_RD_SETUP_Pos 24 |
| 4612 | #define SMC_SETUP_NCS_RD_SETUP_Msk (0x3fu << SMC_SETUP_NCS_RD_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in READ Access */ |
| 4613 | #define SMC_SETUP_NCS_RD_SETUP(value) ((SMC_SETUP_NCS_RD_SETUP_Msk & ((value) << SMC_SETUP_NCS_RD_SETUP_Pos))) |
| 4614 | /* -------- SMC_PULSE : (SMC Offset: N/A) SMC Pulse Register -------- */ |
| 4615 | #define SMC_PULSE_NWE_PULSE_Pos 0 |
| 4616 | #define SMC_PULSE_NWE_PULSE_Msk (0x7fu << SMC_PULSE_NWE_PULSE_Pos) /**< \brief (SMC_PULSE) NWE Pulse Length */ |
| 4617 | #define SMC_PULSE_NWE_PULSE(value) ((SMC_PULSE_NWE_PULSE_Msk & ((value) << SMC_PULSE_NWE_PULSE_Pos))) |
| 4618 | #define SMC_PULSE_NCS_WR_PULSE_Pos 8 |
| 4619 | #define SMC_PULSE_NCS_WR_PULSE_Msk (0x7fu << SMC_PULSE_NCS_WR_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in WRITE Access */ |
| 4620 | #define SMC_PULSE_NCS_WR_PULSE(value) ((SMC_PULSE_NCS_WR_PULSE_Msk & ((value) << SMC_PULSE_NCS_WR_PULSE_Pos))) |
| 4621 | #define SMC_PULSE_NRD_PULSE_Pos 16 |
| 4622 | #define SMC_PULSE_NRD_PULSE_Msk (0x7fu << SMC_PULSE_NRD_PULSE_Pos) /**< \brief (SMC_PULSE) NRD Pulse Length */ |
| 4623 | #define SMC_PULSE_NRD_PULSE(value) ((SMC_PULSE_NRD_PULSE_Msk & ((value) << SMC_PULSE_NRD_PULSE_Pos))) |
| 4624 | #define SMC_PULSE_NCS_RD_PULSE_Pos 24 |
| 4625 | #define SMC_PULSE_NCS_RD_PULSE_Msk (0x7fu << SMC_PULSE_NCS_RD_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in READ Access */ |
| 4626 | #define SMC_PULSE_NCS_RD_PULSE(value) ((SMC_PULSE_NCS_RD_PULSE_Msk & ((value) << SMC_PULSE_NCS_RD_PULSE_Pos))) |
| 4627 | /* -------- SMC_CYCLE : (SMC Offset: N/A) SMC Cycle Register -------- */ |
| 4628 | #define SMC_CYCLE_NWE_CYCLE_Pos 0 |
| 4629 | #define SMC_CYCLE_NWE_CYCLE_Msk (0x1ffu << SMC_CYCLE_NWE_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Write Cycle Length */ |
| 4630 | #define SMC_CYCLE_NWE_CYCLE(value) ((SMC_CYCLE_NWE_CYCLE_Msk & ((value) << SMC_CYCLE_NWE_CYCLE_Pos))) |
| 4631 | #define SMC_CYCLE_NRD_CYCLE_Pos 16 |
| 4632 | #define SMC_CYCLE_NRD_CYCLE_Msk (0x1ffu << SMC_CYCLE_NRD_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Read Cycle Length */ |
| 4633 | #define SMC_CYCLE_NRD_CYCLE(value) ((SMC_CYCLE_NRD_CYCLE_Msk & ((value) << SMC_CYCLE_NRD_CYCLE_Pos))) |
| 4634 | /* -------- SMC_MODE : (SMC Offset: N/A) SMC Mode Register -------- */ |
| 4635 | #define SMC_MODE_READ_MODE (0x1u << 0) /**< \brief (SMC_MODE) */ |
| 4636 | #define SMC_MODE_WRITE_MODE (0x1u << 1) /**< \brief (SMC_MODE) */ |
| 4637 | #define SMC_MODE_EXNW_MODE_Pos 4 |
| 4638 | #define SMC_MODE_EXNW_MODE_Msk (0x3u << SMC_MODE_EXNW_MODE_Pos) /**< \brief (SMC_MODE) NWAIT Mode */ |
| 4639 | #define SMC_MODE_EXNW_MODE_DISABLED (0x0u << 4) /**< \brief (SMC_MODE) Disabled */ |
| 4640 | #define SMC_MODE_EXNW_MODE_FROZEN (0x2u << 4) /**< \brief (SMC_MODE) Frozen Mode */ |
| 4641 | #define SMC_MODE_EXNW_MODE_READY (0x3u << 4) /**< \brief (SMC_MODE) Ready Mode */ |
| 4642 | #define SMC_MODE_DBW_Pos 12 |
| 4643 | #define SMC_MODE_DBW_Msk (0x3u << SMC_MODE_DBW_Pos) /**< \brief (SMC_MODE) Data Bus Width */ |
| 4644 | #define SMC_MODE_DBW_8_BIT (0x0u << 12) /**< \brief (SMC_MODE) 8-bit bus */ |
| 4645 | #define SMC_MODE_DBW_16_BIT (0x1u << 12) /**< \brief (SMC_MODE) 16-bit bus */ |
| 4646 | #define SMC_MODE_DBW_32_BIT (0x2u << 12) /**< \brief (SMC_MODE) 32-bit bus */ |
| 4647 | #define SMC_MODE_TDF_CYCLES_Pos 16 |
| 4648 | #define SMC_MODE_TDF_CYCLES_Msk (0xfu << SMC_MODE_TDF_CYCLES_Pos) /**< \brief (SMC_MODE) Data Float Time */ |
| 4649 | #define SMC_MODE_TDF_CYCLES(value) ((SMC_MODE_TDF_CYCLES_Msk & ((value) << SMC_MODE_TDF_CYCLES_Pos))) |
| 4650 | #define SMC_MODE_TDF_MODE (0x1u << 20) /**< \brief (SMC_MODE) TDF Optimization */ |
| 4651 | #define SMC_MODE_PMEN (0x1u << 24) /**< \brief (SMC_MODE) Page Mode Enabled */ |
| 4652 | #define SMC_MODE_PS_Pos 28 |
| 4653 | #define SMC_MODE_PS_Msk (0x3u << SMC_MODE_PS_Pos) /**< \brief (SMC_MODE) Page Size */ |
| 4654 | #define SMC_MODE_PS_4_BYTE (0x0u << 28) /**< \brief (SMC_MODE) 4-byte page */ |
| 4655 | #define SMC_MODE_PS_8_BYTE (0x1u << 28) /**< \brief (SMC_MODE) 8-byte page */ |
| 4656 | #define SMC_MODE_PS_16_BYTE (0x2u << 28) /**< \brief (SMC_MODE) 16-byte page */ |
| 4657 | #define SMC_MODE_PS_32_BYTE (0x3u << 28) /**< \brief (SMC_MODE) 32-byte page */ |
| 4658 | /* -------- SMC_OCMS : (SMC Offset: 0x80) SMC OCMS MODE Register -------- */ |
| 4659 | #define SMC_OCMS_SMSE (0x1u << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */ |
| 4660 | #define SMC_OCMS_CS0SE (0x1u << 16) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ |
| 4661 | #define SMC_OCMS_CS1SE (0x1u << 17) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ |
| 4662 | #define SMC_OCMS_CS2SE (0x1u << 18) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ |
| 4663 | #define SMC_OCMS_CS3SE (0x1u << 19) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ |
| 4664 | /* -------- SMC_KEY1 : (SMC Offset: 0x84) SMC OCMS KEY1 Register -------- */ |
| 4665 | #define SMC_KEY1_KEY1_Pos 0 |
| 4666 | #define SMC_KEY1_KEY1_Msk (0xffffffffu << SMC_KEY1_KEY1_Pos) /**< \brief (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */ |
| 4667 | #define SMC_KEY1_KEY1(value) ((SMC_KEY1_KEY1_Msk & ((value) << SMC_KEY1_KEY1_Pos))) |
| 4668 | /* -------- SMC_KEY2 : (SMC Offset: 0x88) SMC OCMS KEY2 Register -------- */ |
| 4669 | #define SMC_KEY2_KEY2_Pos 0 |
| 4670 | #define SMC_KEY2_KEY2_Msk (0xffffffffu << SMC_KEY2_KEY2_Pos) /**< \brief (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */ |
| 4671 | #define SMC_KEY2_KEY2(value) ((SMC_KEY2_KEY2_Msk & ((value) << SMC_KEY2_KEY2_Pos))) |
| 4672 | /* -------- SMC_WPMR : (SMC Offset: 0xE4) SMC Write Protect Mode Register -------- */ |
| 4673 | #define SMC_WPMR_WPEN (0x1u << 0) /**< \brief (SMC_WPMR) Write Protect Enable */ |
| 4674 | #define SMC_WPMR_WPKEY_Pos 8 |
| 4675 | #define SMC_WPMR_WPKEY_Msk (0xffffffu << SMC_WPMR_WPKEY_Pos) /**< \brief (SMC_WPMR) Write Protect KEY */ |
| 4676 | #define SMC_WPMR_WPKEY(value) ((SMC_WPMR_WPKEY_Msk & ((value) << SMC_WPMR_WPKEY_Pos))) |
| 4677 | /* -------- SMC_WPSR : (SMC Offset: 0xE8) SMC Write Protect Status Register -------- */ |
| 4678 | #define SMC_WPSR_WPVS (0x1u << 0) /**< \brief (SMC_WPSR) Write Protect Enable */ |
| 4679 | #define SMC_WPSR_WPVSRC_Pos 8 |
| 4680 | #define SMC_WPSR_WPVSRC_Msk (0xffffu << SMC_WPSR_WPVSRC_Pos) /**< \brief (SMC_WPSR) Write Protect Violation Source */ |
| 4681 | |
| 4682 | /*@}*/ |
| 4683 | |
| 4684 | /* ============================================================================= */ |
| 4685 | /** SOFTWARE API DEFINITION FOR Serial Peripheral Interface */ |
| 4686 | /* ============================================================================= */ |
| 4687 | /** \addtogroup SAM3S_SPI Serial Peripheral Interface */ |
| 4688 | /*@{*/ |
| 4689 | |
| 4690 | #ifndef __ASSEMBLY__ |
| 4691 | /** \brief Spi hardware registers */ |
| 4692 | typedef struct { |
| 4693 | WoReg SPI_CR; /**< \brief (Spi Offset: 0x00) Control Register */ |
| 4694 | RwReg SPI_MR; /**< \brief (Spi Offset: 0x04) Mode Register */ |
| 4695 | RoReg SPI_RDR; /**< \brief (Spi Offset: 0x08) Receive Data Register */ |
| 4696 | WoReg SPI_TDR; /**< \brief (Spi Offset: 0x0C) Transmit Data Register */ |
| 4697 | RoReg SPI_SR; /**< \brief (Spi Offset: 0x10) Status Register */ |
| 4698 | WoReg SPI_IER; /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */ |
| 4699 | WoReg SPI_IDR; /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */ |
| 4700 | RoReg SPI_IMR; /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */ |
| 4701 | RwReg Reserved1[4]; |
| 4702 | RwReg SPI_CSR[4]; /**< \brief (Spi Offset: 0x30) Chip Select Register */ |
| 4703 | RwReg Reserved2[41]; |
| 4704 | RwReg SPI_WPMR; /**< \brief (Spi Offset: 0xE4) Write Protection Control Register */ |
| 4705 | RoReg SPI_WPSR; /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */ |
| 4706 | RwReg Reserved3[5]; |
| 4707 | RwReg SPI_RPR; /**< \brief (Spi Offset: 0x100) Receive Pointer Register */ |
| 4708 | RwReg SPI_RCR; /**< \brief (Spi Offset: 0x104) Receive Counter Register */ |
| 4709 | RwReg SPI_TPR; /**< \brief (Spi Offset: 0x108) Transmit Pointer Register */ |
| 4710 | RwReg SPI_TCR; /**< \brief (Spi Offset: 0x10C) Transmit Counter Register */ |
| 4711 | RwReg SPI_RNPR; /**< \brief (Spi Offset: 0x110) Receive Next Pointer Register */ |
| 4712 | RwReg SPI_RNCR; /**< \brief (Spi Offset: 0x114) Receive Next Counter Register */ |
| 4713 | RwReg SPI_TNPR; /**< \brief (Spi Offset: 0x118) Transmit Next Pointer Register */ |
| 4714 | RwReg SPI_TNCR; /**< \brief (Spi Offset: 0x11C) Transmit Next Counter Register */ |
| 4715 | WoReg SPI_PTCR; /**< \brief (Spi Offset: 0x120) Transfer Control Register */ |
| 4716 | RoReg SPI_PTSR; /**< \brief (Spi Offset: 0x124) Transfer Status Register */ |
| 4717 | } Spi; |
| 4718 | #endif /* __ASSEMBLY__ */ |
| 4719 | /* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */ |
| 4720 | #define SPI_CR_SPIEN (0x1u << 0) /**< \brief (SPI_CR) SPI Enable */ |
| 4721 | #define SPI_CR_SPIDIS (0x1u << 1) /**< \brief (SPI_CR) SPI Disable */ |
| 4722 | #define SPI_CR_SWRST (0x1u << 7) /**< \brief (SPI_CR) SPI Software Reset */ |
| 4723 | #define SPI_CR_LASTXFER (0x1u << 24) /**< \brief (SPI_CR) Last Transfer */ |
| 4724 | /* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */ |
| 4725 | #define SPI_MR_MSTR (0x1u << 0) /**< \brief (SPI_MR) Master/Slave Mode */ |
| 4726 | #define SPI_MR_PS (0x1u << 1) /**< \brief (SPI_MR) Peripheral Select */ |
| 4727 | #define SPI_MR_PCSDEC (0x1u << 2) /**< \brief (SPI_MR) Chip Select Decode */ |
| 4728 | #define SPI_MR_MODFDIS (0x1u << 4) /**< \brief (SPI_MR) Mode Fault Detection */ |
| 4729 | #define SPI_MR_WDRBT (0x1u << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */ |
| 4730 | #define SPI_MR_LLB (0x1u << 7) /**< \brief (SPI_MR) Local Loopback Enable */ |
| 4731 | #define SPI_MR_PCS_Pos 16 |
| 4732 | #define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos) /**< \brief (SPI_MR) Peripheral Chip Select */ |
| 4733 | #define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos))) |
| 4734 | #define SPI_MR_DLYBCS_Pos 24 |
| 4735 | #define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos) /**< \brief (SPI_MR) Delay Between Chip Selects */ |
| 4736 | #define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos))) |
| 4737 | /* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */ |
| 4738 | #define SPI_RDR_RD_Pos 0 |
| 4739 | #define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos) /**< \brief (SPI_RDR) Receive Data */ |
| 4740 | #define SPI_RDR_PCS_Pos 16 |
| 4741 | #define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos) /**< \brief (SPI_RDR) Peripheral Chip Select */ |
| 4742 | /* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */ |
| 4743 | #define SPI_TDR_TD_Pos 0 |
| 4744 | #define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos) /**< \brief (SPI_TDR) Transmit Data */ |
| 4745 | #define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos))) |
| 4746 | #define SPI_TDR_PCS_Pos 16 |
| 4747 | #define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos) /**< \brief (SPI_TDR) Peripheral Chip Select */ |
| 4748 | #define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos))) |
| 4749 | #define SPI_TDR_LASTXFER (0x1u << 24) /**< \brief (SPI_TDR) Last Transfer */ |
| 4750 | /* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ |
| 4751 | #define SPI_SR_RDRF (0x1u << 0) /**< \brief (SPI_SR) Receive Data Register Full */ |
| 4752 | #define SPI_SR_TDRE (0x1u << 1) /**< \brief (SPI_SR) Transmit Data Register Empty */ |
| 4753 | #define SPI_SR_MODF (0x1u << 2) /**< \brief (SPI_SR) Mode Fault Error */ |
| 4754 | #define SPI_SR_OVRES (0x1u << 3) /**< \brief (SPI_SR) Overrun Error Status */ |
| 4755 | #define SPI_SR_ENDRX (0x1u << 4) /**< \brief (SPI_SR) End of RX buffer */ |
| 4756 | #define SPI_SR_ENDTX (0x1u << 5) /**< \brief (SPI_SR) End of TX buffer */ |
| 4757 | #define SPI_SR_RXBUFF (0x1u << 6) /**< \brief (SPI_SR) RX Buffer Full */ |
| 4758 | #define SPI_SR_TXBUFE (0x1u << 7) /**< \brief (SPI_SR) TX Buffer Empty */ |
| 4759 | #define SPI_SR_NSSR (0x1u << 8) /**< \brief (SPI_SR) NSS Rising */ |
| 4760 | #define SPI_SR_TXEMPTY (0x1u << 9) /**< \brief (SPI_SR) Transmission Registers Empty */ |
| 4761 | #define SPI_SR_UNDES (0x1u << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave Mode Only) */ |
| 4762 | #define SPI_SR_SPIENS (0x1u << 16) /**< \brief (SPI_SR) SPI Enable Status */ |
| 4763 | /* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ |
| 4764 | #define SPI_IER_RDRF (0x1u << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */ |
| 4765 | #define SPI_IER_TDRE (0x1u << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */ |
| 4766 | #define SPI_IER_MODF (0x1u << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */ |
| 4767 | #define SPI_IER_OVRES (0x1u << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */ |
| 4768 | #define SPI_IER_ENDRX (0x1u << 4) /**< \brief (SPI_IER) End of Receive Buffer Interrupt Enable */ |
| 4769 | #define SPI_IER_ENDTX (0x1u << 5) /**< \brief (SPI_IER) End of Transmit Buffer Interrupt Enable */ |
| 4770 | #define SPI_IER_RXBUFF (0x1u << 6) /**< \brief (SPI_IER) Receive Buffer Full Interrupt Enable */ |
| 4771 | #define SPI_IER_TXBUFE (0x1u << 7) /**< \brief (SPI_IER) Transmit Buffer Empty Interrupt Enable */ |
| 4772 | #define SPI_IER_NSSR (0x1u << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */ |
| 4773 | #define SPI_IER_TXEMPTY (0x1u << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */ |
| 4774 | #define SPI_IER_UNDES (0x1u << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */ |
| 4775 | /* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ |
| 4776 | #define SPI_IDR_RDRF (0x1u << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */ |
| 4777 | #define SPI_IDR_TDRE (0x1u << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */ |
| 4778 | #define SPI_IDR_MODF (0x1u << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */ |
| 4779 | #define SPI_IDR_OVRES (0x1u << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */ |
| 4780 | #define SPI_IDR_ENDRX (0x1u << 4) /**< \brief (SPI_IDR) End of Receive Buffer Interrupt Disable */ |
| 4781 | #define SPI_IDR_ENDTX (0x1u << 5) /**< \brief (SPI_IDR) End of Transmit Buffer Interrupt Disable */ |
| 4782 | #define SPI_IDR_RXBUFF (0x1u << 6) /**< \brief (SPI_IDR) Receive Buffer Full Interrupt Disable */ |
| 4783 | #define SPI_IDR_TXBUFE (0x1u << 7) /**< \brief (SPI_IDR) Transmit Buffer Empty Interrupt Disable */ |
| 4784 | #define SPI_IDR_NSSR (0x1u << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */ |
| 4785 | #define SPI_IDR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */ |
| 4786 | #define SPI_IDR_UNDES (0x1u << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */ |
| 4787 | /* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */ |
| 4788 | #define SPI_IMR_RDRF (0x1u << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */ |
| 4789 | #define SPI_IMR_TDRE (0x1u << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */ |
| 4790 | #define SPI_IMR_MODF (0x1u << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */ |
| 4791 | #define SPI_IMR_OVRES (0x1u << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */ |
| 4792 | #define SPI_IMR_ENDRX (0x1u << 4) /**< \brief (SPI_IMR) End of Receive Buffer Interrupt Mask */ |
| 4793 | #define SPI_IMR_ENDTX (0x1u << 5) /**< \brief (SPI_IMR) End of Transmit Buffer Interrupt Mask */ |
| 4794 | #define SPI_IMR_RXBUFF (0x1u << 6) /**< \brief (SPI_IMR) Receive Buffer Full Interrupt Mask */ |
| 4795 | #define SPI_IMR_TXBUFE (0x1u << 7) /**< \brief (SPI_IMR) Transmit Buffer Empty Interrupt Mask */ |
| 4796 | #define SPI_IMR_NSSR (0x1u << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */ |
| 4797 | #define SPI_IMR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */ |
| 4798 | #define SPI_IMR_UNDES (0x1u << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */ |
| 4799 | /* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */ |
| 4800 | #define SPI_CSR_CPOL (0x1u << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */ |
| 4801 | #define SPI_CSR_NCPHA (0x1u << 1) /**< \brief (SPI_CSR[4]) Clock Phase */ |
| 4802 | #define SPI_CSR_CSNAAT (0x1u << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */ |
| 4803 | #define SPI_CSR_CSAAT (0x1u << 3) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */ |
| 4804 | #define SPI_CSR_BITS_Pos 4 |
| 4805 | #define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos) /**< \brief (SPI_CSR[4]) Bits Per Transfer */ |
| 4806 | #define SPI_CSR_BITS_8_BIT (0x0u << 4) /**< \brief (SPI_CSR[4]) 8_bits for transfer */ |
| 4807 | #define SPI_CSR_BITS_9_BIT (0x1u << 4) /**< \brief (SPI_CSR[4]) 9_bits for transfer */ |
| 4808 | #define SPI_CSR_BITS_10_BIT (0x2u << 4) /**< \brief (SPI_CSR[4]) 8_bits for transfer */ |
| 4809 | #define SPI_CSR_BITS_11_BIT (0x3u << 4) /**< \brief (SPI_CSR[4]) 8_bits for transfer */ |
| 4810 | #define SPI_CSR_BITS_12_BIT (0x4u << 4) /**< \brief (SPI_CSR[4]) 8_bits for transfer */ |
| 4811 | #define SPI_CSR_BITS_13_BIT (0x5u << 4) /**< \brief (SPI_CSR[4]) 8_bits for transfer */ |
| 4812 | #define SPI_CSR_BITS_14_BIT (0x6u << 4) /**< \brief (SPI_CSR[4]) 8_bits for transfer */ |
| 4813 | #define SPI_CSR_BITS_15_BIT (0x7u << 4) /**< \brief (SPI_CSR[4]) 8_bits for transfer */ |
| 4814 | #define SPI_CSR_BITS_16_BIT (0x8u << 4) /**< \brief (SPI_CSR[4]) 8_bits for transfer */ |
| 4815 | #define SPI_CSR_SCBR_Pos 8 |
| 4816 | #define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos) /**< \brief (SPI_CSR[4]) Serial Clock Baud Rate */ |
| 4817 | #define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos))) |
| 4818 | #define SPI_CSR_DLYBS_Pos 16 |
| 4819 | #define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos) /**< \brief (SPI_CSR[4]) Delay Before SPCK */ |
| 4820 | #define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos))) |
| 4821 | #define SPI_CSR_DLYBCT_Pos 24 |
| 4822 | #define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */ |
| 4823 | #define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos))) |
| 4824 | /* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Control Register -------- */ |
| 4825 | #define SPI_WPMR_SPIWPEN (0x1u << 0) /**< \brief (SPI_WPMR) SPI Write Protection Enable */ |
| 4826 | #define SPI_WPMR_SPIWPKEY_Pos 8 |
| 4827 | #define SPI_WPMR_SPIWPKEY_Msk (0xffffffu << SPI_WPMR_SPIWPKEY_Pos) /**< \brief (SPI_WPMR) SPI Write Protection Key Password */ |
| 4828 | #define SPI_WPMR_SPIWPKEY(value) ((SPI_WPMR_SPIWPKEY_Msk & ((value) << SPI_WPMR_SPIWPKEY_Pos))) |
| 4829 | /* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */ |
| 4830 | #define SPI_WPSR_SPIWPVS_Pos 0 |
| 4831 | #define SPI_WPSR_SPIWPVS_Msk (0x7u << SPI_WPSR_SPIWPVS_Pos) /**< \brief (SPI_WPSR) SPI Write Protection Violation Status */ |
| 4832 | #define SPI_WPSR_SPIWPVSRC_Pos 8 |
| 4833 | #define SPI_WPSR_SPIWPVSRC_Msk (0xffu << SPI_WPSR_SPIWPVSRC_Pos) /**< \brief (SPI_WPSR) SPI Write Protection Violation Source */ |
| 4834 | /* -------- SPI_RPR : (SPI Offset: 0x100) Receive Pointer Register -------- */ |
| 4835 | #define SPI_RPR_RXPTR_Pos 0 |
| 4836 | #define SPI_RPR_RXPTR_Msk (0xffffffffu << SPI_RPR_RXPTR_Pos) /**< \brief (SPI_RPR) Receive Pointer Register */ |
| 4837 | #define SPI_RPR_RXPTR(value) ((SPI_RPR_RXPTR_Msk & ((value) << SPI_RPR_RXPTR_Pos))) |
| 4838 | /* -------- SPI_RCR : (SPI Offset: 0x104) Receive Counter Register -------- */ |
| 4839 | #define SPI_RCR_RXCTR_Pos 0 |
| 4840 | #define SPI_RCR_RXCTR_Msk (0xffffu << SPI_RCR_RXCTR_Pos) /**< \brief (SPI_RCR) Receive Counter Register */ |
| 4841 | #define SPI_RCR_RXCTR(value) ((SPI_RCR_RXCTR_Msk & ((value) << SPI_RCR_RXCTR_Pos))) |
| 4842 | /* -------- SPI_TPR : (SPI Offset: 0x108) Transmit Pointer Register -------- */ |
| 4843 | #define SPI_TPR_TXPTR_Pos 0 |
| 4844 | #define SPI_TPR_TXPTR_Msk (0xffffffffu << SPI_TPR_TXPTR_Pos) /**< \brief (SPI_TPR) Transmit Counter Register */ |
| 4845 | #define SPI_TPR_TXPTR(value) ((SPI_TPR_TXPTR_Msk & ((value) << SPI_TPR_TXPTR_Pos))) |
| 4846 | /* -------- SPI_TCR : (SPI Offset: 0x10C) Transmit Counter Register -------- */ |
| 4847 | #define SPI_TCR_TXCTR_Pos 0 |
| 4848 | #define SPI_TCR_TXCTR_Msk (0xffffu << SPI_TCR_TXCTR_Pos) /**< \brief (SPI_TCR) Transmit Counter Register */ |
| 4849 | #define SPI_TCR_TXCTR(value) ((SPI_TCR_TXCTR_Msk & ((value) << SPI_TCR_TXCTR_Pos))) |
| 4850 | /* -------- SPI_RNPR : (SPI Offset: 0x110) Receive Next Pointer Register -------- */ |
| 4851 | #define SPI_RNPR_RXNPTR_Pos 0 |
| 4852 | #define SPI_RNPR_RXNPTR_Msk (0xffffffffu << SPI_RNPR_RXNPTR_Pos) /**< \brief (SPI_RNPR) Receive Next Pointer */ |
| 4853 | #define SPI_RNPR_RXNPTR(value) ((SPI_RNPR_RXNPTR_Msk & ((value) << SPI_RNPR_RXNPTR_Pos))) |
| 4854 | /* -------- SPI_RNCR : (SPI Offset: 0x114) Receive Next Counter Register -------- */ |
| 4855 | #define SPI_RNCR_RXNCTR_Pos 0 |
| 4856 | #define SPI_RNCR_RXNCTR_Msk (0xffffu << SPI_RNCR_RXNCTR_Pos) /**< \brief (SPI_RNCR) Receive Next Counter */ |
| 4857 | #define SPI_RNCR_RXNCTR(value) ((SPI_RNCR_RXNCTR_Msk & ((value) << SPI_RNCR_RXNCTR_Pos))) |
| 4858 | /* -------- SPI_TNPR : (SPI Offset: 0x118) Transmit Next Pointer Register -------- */ |
| 4859 | #define SPI_TNPR_TXNPTR_Pos 0 |
| 4860 | #define SPI_TNPR_TXNPTR_Msk (0xffffffffu << SPI_TNPR_TXNPTR_Pos) /**< \brief (SPI_TNPR) Transmit Next Pointer */ |
| 4861 | #define SPI_TNPR_TXNPTR(value) ((SPI_TNPR_TXNPTR_Msk & ((value) << SPI_TNPR_TXNPTR_Pos))) |
| 4862 | /* -------- SPI_TNCR : (SPI Offset: 0x11C) Transmit Next Counter Register -------- */ |
| 4863 | #define SPI_TNCR_TXNCTR_Pos 0 |
| 4864 | #define SPI_TNCR_TXNCTR_Msk (0xffffu << SPI_TNCR_TXNCTR_Pos) /**< \brief (SPI_TNCR) Transmit Counter Next */ |
| 4865 | #define SPI_TNCR_TXNCTR(value) ((SPI_TNCR_TXNCTR_Msk & ((value) << SPI_TNCR_TXNCTR_Pos))) |
| 4866 | /* -------- SPI_PTCR : (SPI Offset: 0x120) Transfer Control Register -------- */ |
| 4867 | #define SPI_PTCR_RXTEN (0x1u << 0) /**< \brief (SPI_PTCR) Receiver Transfer Enable */ |
| 4868 | #define SPI_PTCR_RXTDIS (0x1u << 1) /**< \brief (SPI_PTCR) Receiver Transfer Disable */ |
| 4869 | #define SPI_PTCR_TXTEN (0x1u << 8) /**< \brief (SPI_PTCR) Transmitter Transfer Enable */ |
| 4870 | #define SPI_PTCR_TXTDIS (0x1u << 9) /**< \brief (SPI_PTCR) Transmitter Transfer Disable */ |
| 4871 | /* -------- SPI_PTSR : (SPI Offset: 0x124) Transfer Status Register -------- */ |
| 4872 | #define SPI_PTSR_RXTEN (0x1u << 0) /**< \brief (SPI_PTSR) Receiver Transfer Enable */ |
| 4873 | #define SPI_PTSR_TXTEN (0x1u << 8) /**< \brief (SPI_PTSR) Transmitter Transfer Enable */ |
| 4874 | |
| 4875 | /*@}*/ |
| 4876 | |
| 4877 | /* ============================================================================= */ |
| 4878 | /** SOFTWARE API DEFINITION FOR Synchronous Serial Controller */ |
| 4879 | /* ============================================================================= */ |
| 4880 | /** \addtogroup SAM3S_SSC Synchronous Serial Controller */ |
| 4881 | /*@{*/ |
| 4882 | |
| 4883 | #ifndef __ASSEMBLY__ |
| 4884 | /** \brief Ssc hardware registers */ |
| 4885 | typedef struct { |
| 4886 | WoReg SSC_CR; /**< \brief (Ssc Offset: 0x0) Control Register */ |
| 4887 | RwReg SSC_CMR; /**< \brief (Ssc Offset: 0x4) Clock Mode Register */ |
| 4888 | RwReg Reserved1[2]; |
| 4889 | RwReg SSC_RCMR; /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */ |
| 4890 | RwReg SSC_RFMR; /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */ |
| 4891 | RwReg SSC_TCMR; /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */ |
| 4892 | RwReg SSC_TFMR; /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */ |
| 4893 | RoReg SSC_RHR; /**< \brief (Ssc Offset: 0x20) Receive Holding Register */ |
| 4894 | WoReg SSC_THR; /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */ |
| 4895 | RwReg Reserved2[2]; |
| 4896 | RoReg SSC_RSHR; /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */ |
| 4897 | RwReg SSC_TSHR; /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */ |
| 4898 | RwReg SSC_RC0R; /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */ |
| 4899 | RwReg SSC_RC1R; /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */ |
| 4900 | RoReg SSC_SR; /**< \brief (Ssc Offset: 0x40) Status Register */ |
| 4901 | WoReg SSC_IER; /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */ |
| 4902 | WoReg SSC_IDR; /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */ |
| 4903 | RoReg SSC_IMR; /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */ |
| 4904 | RwReg Reserved3[37]; |
| 4905 | RwReg SSC_WPMR; /**< \brief (Ssc Offset: 0xE4) Write Protect Mode Register */ |
| 4906 | RoReg SSC_WPSR; /**< \brief (Ssc Offset: 0xE8) Write Protect Status Register */ |
| 4907 | RwReg Reserved4[5]; |
| 4908 | RwReg SSC_RPR; /**< \brief (Ssc Offset: 0x100) Receive Pointer Register */ |
| 4909 | RwReg SSC_RCR; /**< \brief (Ssc Offset: 0x104) Receive Counter Register */ |
| 4910 | RwReg SSC_TPR; /**< \brief (Ssc Offset: 0x108) Transmit Pointer Register */ |
| 4911 | RwReg SSC_TCR; /**< \brief (Ssc Offset: 0x10C) Transmit Counter Register */ |
| 4912 | RwReg SSC_RNPR; /**< \brief (Ssc Offset: 0x110) Receive Next Pointer Register */ |
| 4913 | RwReg SSC_RNCR; /**< \brief (Ssc Offset: 0x114) Receive Next Counter Register */ |
| 4914 | RwReg SSC_TNPR; /**< \brief (Ssc Offset: 0x118) Transmit Next Pointer Register */ |
| 4915 | RwReg SSC_TNCR; /**< \brief (Ssc Offset: 0x11C) Transmit Next Counter Register */ |
| 4916 | WoReg SSC_PTCR; /**< \brief (Ssc Offset: 0x120) Transfer Control Register */ |
| 4917 | RoReg SSC_PTSR; /**< \brief (Ssc Offset: 0x124) Transfer Status Register */ |
| 4918 | } Ssc; |
| 4919 | #endif /* __ASSEMBLY__ */ |
| 4920 | /* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */ |
| 4921 | #define SSC_CR_RXEN (0x1u << 0) /**< \brief (SSC_CR) Receive Enable */ |
| 4922 | #define SSC_CR_RXDIS (0x1u << 1) /**< \brief (SSC_CR) Receive Disable */ |
| 4923 | #define SSC_CR_TXEN (0x1u << 8) /**< \brief (SSC_CR) Transmit Enable */ |
| 4924 | #define SSC_CR_TXDIS (0x1u << 9) /**< \brief (SSC_CR) Transmit Disable */ |
| 4925 | #define SSC_CR_SWRST (0x1u << 15) /**< \brief (SSC_CR) Software Reset */ |
| 4926 | /* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */ |
| 4927 | #define SSC_CMR_DIV_Pos 0 |
| 4928 | #define SSC_CMR_DIV_Msk (0xfffu << SSC_CMR_DIV_Pos) /**< \brief (SSC_CMR) Clock Divider */ |
| 4929 | #define SSC_CMR_DIV(value) ((SSC_CMR_DIV_Msk & ((value) << SSC_CMR_DIV_Pos))) |
| 4930 | /* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */ |
| 4931 | #define SSC_RCMR_CKS_Pos 0 |
| 4932 | #define SSC_RCMR_CKS_Msk (0x3u << SSC_RCMR_CKS_Pos) /**< \brief (SSC_RCMR) Receive Clock Selection */ |
| 4933 | #define SSC_RCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_RCMR) Divided Clock */ |
| 4934 | #define SSC_RCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_RCMR) TK Clock signal */ |
| 4935 | #define SSC_RCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_RCMR) RK pin */ |
| 4936 | #define SSC_RCMR_CKO_Pos 2 |
| 4937 | #define SSC_RCMR_CKO_Msk (0x7u << SSC_RCMR_CKO_Pos) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */ |
| 4938 | #define SSC_RCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_RCMR) None */ |
| 4939 | #define SSC_RCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_RCMR) Continuous Receive Clock */ |
| 4940 | #define SSC_RCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_RCMR) Receive Clock only during data transfers */ |
| 4941 | #define SSC_RCMR_CKI (0x1u << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */ |
| 4942 | #define SSC_RCMR_CKG_Pos 6 |
| 4943 | #define SSC_RCMR_CKG_Msk (0x3u << SSC_RCMR_CKG_Pos) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */ |
| 4944 | #define SSC_RCMR_CKG_NONE (0x0u << 6) /**< \brief (SSC_RCMR) None */ |
| 4945 | #define SSC_RCMR_CKG_CONTINUOUS (0x1u << 6) /**< \brief (SSC_RCMR) Continuous Receive Clock */ |
| 4946 | #define SSC_RCMR_CKG_TRANSFER (0x2u << 6) /**< \brief (SSC_RCMR) Receive Clock only during data transfers */ |
| 4947 | #define SSC_RCMR_START_Pos 8 |
| 4948 | #define SSC_RCMR_START_Msk (0xfu << SSC_RCMR_START_Pos) /**< \brief (SSC_RCMR) Receive Start Selection */ |
| 4949 | #define SSC_RCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_RCMR) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */ |
| 4950 | #define SSC_RCMR_START_TRANSMIT (0x1u << 8) /**< \brief (SSC_RCMR) Transmit start */ |
| 4951 | #define SSC_RCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_RCMR) Detection of a low level on RF signal */ |
| 4952 | #define SSC_RCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_RCMR) Detection of a high level on RF signal */ |
| 4953 | #define SSC_RCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_RCMR) Detection of a falling edge on RF signal */ |
| 4954 | #define SSC_RCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_RCMR) Detection of a rising edge on RF signal */ |
| 4955 | #define SSC_RCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_RCMR) Detection of any level change on RF signal */ |
| 4956 | #define SSC_RCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_RCMR) Detection of any edge on RF signal */ |
| 4957 | #define SSC_RCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_RCMR) Compare 0 */ |
| 4958 | #define SSC_RCMR_STOP (0x1u << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */ |
| 4959 | #define SSC_RCMR_STTDLY_Pos 16 |
| 4960 | #define SSC_RCMR_STTDLY_Msk (0xffu << SSC_RCMR_STTDLY_Pos) /**< \brief (SSC_RCMR) Receive Start Delay */ |
| 4961 | #define SSC_RCMR_STTDLY(value) ((SSC_RCMR_STTDLY_Msk & ((value) << SSC_RCMR_STTDLY_Pos))) |
| 4962 | #define SSC_RCMR_PERIOD_Pos 24 |
| 4963 | #define SSC_RCMR_PERIOD_Msk (0xffu << SSC_RCMR_PERIOD_Pos) /**< \brief (SSC_RCMR) Receive Period Divider Selection */ |
| 4964 | #define SSC_RCMR_PERIOD(value) ((SSC_RCMR_PERIOD_Msk & ((value) << SSC_RCMR_PERIOD_Pos))) |
| 4965 | /* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */ |
| 4966 | #define SSC_RFMR_DATLEN_Pos 0 |
| 4967 | #define SSC_RFMR_DATLEN_Msk (0x1fu << SSC_RFMR_DATLEN_Pos) /**< \brief (SSC_RFMR) Data Length */ |
| 4968 | #define SSC_RFMR_DATLEN(value) ((SSC_RFMR_DATLEN_Msk & ((value) << SSC_RFMR_DATLEN_Pos))) |
| 4969 | #define SSC_RFMR_LOOP (0x1u << 5) /**< \brief (SSC_RFMR) Loop Mode */ |
| 4970 | #define SSC_RFMR_MSBF (0x1u << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */ |
| 4971 | #define SSC_RFMR_DATNB_Pos 8 |
| 4972 | #define SSC_RFMR_DATNB_Msk (0xfu << SSC_RFMR_DATNB_Pos) /**< \brief (SSC_RFMR) Data Number per Frame */ |
| 4973 | #define SSC_RFMR_DATNB(value) ((SSC_RFMR_DATNB_Msk & ((value) << SSC_RFMR_DATNB_Pos))) |
| 4974 | #define SSC_RFMR_FSLEN_Pos 16 |
| 4975 | #define SSC_RFMR_FSLEN_Msk (0xfu << SSC_RFMR_FSLEN_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Length */ |
| 4976 | #define SSC_RFMR_FSLEN(value) ((SSC_RFMR_FSLEN_Msk & ((value) << SSC_RFMR_FSLEN_Pos))) |
| 4977 | #define SSC_RFMR_FSOS_Pos 20 |
| 4978 | #define SSC_RFMR_FSOS_Msk (0x7u << SSC_RFMR_FSOS_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */ |
| 4979 | #define SSC_RFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_RFMR) None */ |
| 4980 | #define SSC_RFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_RFMR) Negative Pulse */ |
| 4981 | #define SSC_RFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_RFMR) Positive Pulse */ |
| 4982 | #define SSC_RFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_RFMR) Driven Low during data transfer */ |
| 4983 | #define SSC_RFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_RFMR) Driven High during data transfer */ |
| 4984 | #define SSC_RFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_RFMR) Toggling at each start of data transfer */ |
| 4985 | #define SSC_RFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */ |
| 4986 | #define SSC_RFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_RFMR) Positive Edge Detection */ |
| 4987 | #define SSC_RFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_RFMR) Negative Edge Detection */ |
| 4988 | #define SSC_RFMR_FSLEN_EXT_Pos 28 |
| 4989 | #define SSC_RFMR_FSLEN_EXT_Msk (0xfu << SSC_RFMR_FSLEN_EXT_Pos) /**< \brief (SSC_RFMR) FSLEN Field Extension */ |
| 4990 | #define SSC_RFMR_FSLEN_EXT(value) ((SSC_RFMR_FSLEN_EXT_Msk & ((value) << SSC_RFMR_FSLEN_EXT_Pos))) |
| 4991 | /* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */ |
| 4992 | #define SSC_TCMR_CKS_Pos 0 |
| 4993 | #define SSC_TCMR_CKS_Msk (0x3u << SSC_TCMR_CKS_Pos) /**< \brief (SSC_TCMR) Transmit Clock Selection */ |
| 4994 | #define SSC_TCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_TCMR) Divided Clock */ |
| 4995 | #define SSC_TCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_TCMR) TK Clock signal */ |
| 4996 | #define SSC_TCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_TCMR) RK pin */ |
| 4997 | #define SSC_TCMR_CKO_Pos 2 |
| 4998 | #define SSC_TCMR_CKO_Msk (0x7u << SSC_TCMR_CKO_Pos) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */ |
| 4999 | #define SSC_TCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_TCMR) None */ |
| 5000 | #define SSC_TCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_TCMR) Continuous Receive Clock */ |
| 5001 | #define SSC_TCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_TCMR) Transmit Clock only during data transfers */ |
| 5002 | #define SSC_TCMR_CKI (0x1u << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */ |
| 5003 | #define SSC_TCMR_CKG_Pos 6 |
| 5004 | #define SSC_TCMR_CKG_Msk (0x3u << SSC_TCMR_CKG_Pos) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */ |
| 5005 | #define SSC_TCMR_CKG_NONE (0x0u << 6) /**< \brief (SSC_TCMR) None */ |
| 5006 | #define SSC_TCMR_CKG_CONTINUOUS (0x1u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF Low */ |
| 5007 | #define SSC_TCMR_CKG_TRANSFER (0x2u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF High */ |
| 5008 | #define SSC_TCMR_START_Pos 8 |
| 5009 | #define SSC_TCMR_START_Msk (0xfu << SSC_TCMR_START_Pos) /**< \brief (SSC_TCMR) Transmit Start Selection */ |
| 5010 | #define SSC_TCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_TCMR) Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data. */ |
| 5011 | #define SSC_TCMR_START_RECEIVE (0x1u << 8) /**< \brief (SSC_TCMR) Receive start */ |
| 5012 | #define SSC_TCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_TCMR) Detection of a low level on TF signal */ |
| 5013 | #define SSC_TCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_TCMR) Detection of a high level on TF signal */ |
| 5014 | #define SSC_TCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_TCMR) Detection of a falling edge on TF signal */ |
| 5015 | #define SSC_TCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_TCMR) Detection of a rising edge on TF signal */ |
| 5016 | #define SSC_TCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_TCMR) Detection of any level change on TF signal */ |
| 5017 | #define SSC_TCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_TCMR) Detection of any edge on TF signal */ |
| 5018 | #define SSC_TCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_TCMR) Compare 0 */ |
| 5019 | #define SSC_TCMR_STTDLY_Pos 16 |
| 5020 | #define SSC_TCMR_STTDLY_Msk (0xffu << SSC_TCMR_STTDLY_Pos) /**< \brief (SSC_TCMR) Transmit Start Delay */ |
| 5021 | #define SSC_TCMR_STTDLY(value) ((SSC_TCMR_STTDLY_Msk & ((value) << SSC_TCMR_STTDLY_Pos))) |
| 5022 | #define SSC_TCMR_PERIOD_Pos 24 |
| 5023 | #define SSC_TCMR_PERIOD_Msk (0xffu << SSC_TCMR_PERIOD_Pos) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */ |
| 5024 | #define SSC_TCMR_PERIOD(value) ((SSC_TCMR_PERIOD_Msk & ((value) << SSC_TCMR_PERIOD_Pos))) |
| 5025 | /* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */ |
| 5026 | #define SSC_TFMR_DATLEN_Pos 0 |
| 5027 | #define SSC_TFMR_DATLEN_Msk (0x1fu << SSC_TFMR_DATLEN_Pos) /**< \brief (SSC_TFMR) Data Length */ |
| 5028 | #define SSC_TFMR_DATLEN(value) ((SSC_TFMR_DATLEN_Msk & ((value) << SSC_TFMR_DATLEN_Pos))) |
| 5029 | #define SSC_TFMR_DATDEF (0x1u << 5) /**< \brief (SSC_TFMR) Data Default Value */ |
| 5030 | #define SSC_TFMR_MSBF (0x1u << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */ |
| 5031 | #define SSC_TFMR_DATNB_Pos 8 |
| 5032 | #define SSC_TFMR_DATNB_Msk (0xfu << SSC_TFMR_DATNB_Pos) /**< \brief (SSC_TFMR) Data Number per frame */ |
| 5033 | #define SSC_TFMR_DATNB(value) ((SSC_TFMR_DATNB_Msk & ((value) << SSC_TFMR_DATNB_Pos))) |
| 5034 | #define SSC_TFMR_FSLEN_Pos 16 |
| 5035 | #define SSC_TFMR_FSLEN_Msk (0xfu << SSC_TFMR_FSLEN_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Length */ |
| 5036 | #define SSC_TFMR_FSLEN(value) ((SSC_TFMR_FSLEN_Msk & ((value) << SSC_TFMR_FSLEN_Pos))) |
| 5037 | #define SSC_TFMR_FSOS_Pos 20 |
| 5038 | #define SSC_TFMR_FSOS_Msk (0x7u << SSC_TFMR_FSOS_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */ |
| 5039 | #define SSC_TFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_TFMR) None */ |
| 5040 | #define SSC_TFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_TFMR) Negative Pulse */ |
| 5041 | #define SSC_TFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_TFMR) Positive Pulse */ |
| 5042 | #define SSC_TFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_TFMR) Driven Low during data transfer */ |
| 5043 | #define SSC_TFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_TFMR) Driven High during data transfer */ |
| 5044 | #define SSC_TFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_TFMR) Toggling at each start of data transfer */ |
| 5045 | #define SSC_TFMR_FSDEN (0x1u << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */ |
| 5046 | #define SSC_TFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */ |
| 5047 | #define SSC_TFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_TFMR) Positive Edge Detection */ |
| 5048 | #define SSC_TFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_TFMR) Negative Edge Detection */ |
| 5049 | #define SSC_TFMR_FSLEN_EXT_Pos 28 |
| 5050 | #define SSC_TFMR_FSLEN_EXT_Msk (0xfu << SSC_TFMR_FSLEN_EXT_Pos) /**< \brief (SSC_TFMR) FSLEN Field Extension */ |
| 5051 | #define SSC_TFMR_FSLEN_EXT(value) ((SSC_TFMR_FSLEN_EXT_Msk & ((value) << SSC_TFMR_FSLEN_EXT_Pos))) |
| 5052 | /* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */ |
| 5053 | #define SSC_RHR_RDAT_Pos 0 |
| 5054 | #define SSC_RHR_RDAT_Msk (0xffffffffu << SSC_RHR_RDAT_Pos) /**< \brief (SSC_RHR) Receive Data */ |
| 5055 | /* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */ |
| 5056 | #define SSC_THR_TDAT_Pos 0 |
| 5057 | #define SSC_THR_TDAT_Msk (0xffffffffu << SSC_THR_TDAT_Pos) /**< \brief (SSC_THR) Transmit Data */ |
| 5058 | #define SSC_THR_TDAT(value) ((SSC_THR_TDAT_Msk & ((value) << SSC_THR_TDAT_Pos))) |
| 5059 | /* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */ |
| 5060 | #define SSC_RSHR_RSDAT_Pos 0 |
| 5061 | #define SSC_RSHR_RSDAT_Msk (0xffffu << SSC_RSHR_RSDAT_Pos) /**< \brief (SSC_RSHR) Receive Synchronization Data */ |
| 5062 | /* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */ |
| 5063 | #define SSC_TSHR_TSDAT_Pos 0 |
| 5064 | #define SSC_TSHR_TSDAT_Msk (0xffffu << SSC_TSHR_TSDAT_Pos) /**< \brief (SSC_TSHR) Transmit Synchronization Data */ |
| 5065 | #define SSC_TSHR_TSDAT(value) ((SSC_TSHR_TSDAT_Msk & ((value) << SSC_TSHR_TSDAT_Pos))) |
| 5066 | /* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */ |
| 5067 | #define SSC_RC0R_CP0_Pos 0 |
| 5068 | #define SSC_RC0R_CP0_Msk (0xffffu << SSC_RC0R_CP0_Pos) /**< \brief (SSC_RC0R) Receive Compare Data 0 */ |
| 5069 | #define SSC_RC0R_CP0(value) ((SSC_RC0R_CP0_Msk & ((value) << SSC_RC0R_CP0_Pos))) |
| 5070 | /* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */ |
| 5071 | #define SSC_RC1R_CP1_Pos 0 |
| 5072 | #define SSC_RC1R_CP1_Msk (0xffffu << SSC_RC1R_CP1_Pos) /**< \brief (SSC_RC1R) Receive Compare Data 1 */ |
| 5073 | #define SSC_RC1R_CP1(value) ((SSC_RC1R_CP1_Msk & ((value) << SSC_RC1R_CP1_Pos))) |
| 5074 | /* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */ |
| 5075 | #define SSC_SR_TXRDY (0x1u << 0) /**< \brief (SSC_SR) Transmit Ready */ |
| 5076 | #define SSC_SR_TXEMPTY (0x1u << 1) /**< \brief (SSC_SR) Transmit Empty */ |
| 5077 | #define SSC_SR_ENDTX (0x1u << 2) /**< \brief (SSC_SR) End of Transmission */ |
| 5078 | #define SSC_SR_TXBUFE (0x1u << 3) /**< \brief (SSC_SR) Transmit Buffer Empty */ |
| 5079 | #define SSC_SR_RXRDY (0x1u << 4) /**< \brief (SSC_SR) Receive Ready */ |
| 5080 | #define SSC_SR_OVRUN (0x1u << 5) /**< \brief (SSC_SR) Receive Overrun */ |
| 5081 | #define SSC_SR_ENDRX (0x1u << 6) /**< \brief (SSC_SR) End of Reception */ |
| 5082 | #define SSC_SR_RXBUFF (0x1u << 7) /**< \brief (SSC_SR) Receive Buffer Full */ |
| 5083 | #define SSC_SR_CP0 (0x1u << 8) /**< \brief (SSC_SR) Compare 0 */ |
| 5084 | #define SSC_SR_CP1 (0x1u << 9) /**< \brief (SSC_SR) Compare 1 */ |
| 5085 | #define SSC_SR_TXSYN (0x1u << 10) /**< \brief (SSC_SR) Transmit Sync */ |
| 5086 | #define SSC_SR_RXSYN (0x1u << 11) /**< \brief (SSC_SR) Receive Sync */ |
| 5087 | #define SSC_SR_TXEN (0x1u << 16) /**< \brief (SSC_SR) Transmit Enable */ |
| 5088 | #define SSC_SR_RXEN (0x1u << 17) /**< \brief (SSC_SR) Receive Enable */ |
| 5089 | /* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */ |
| 5090 | #define SSC_IER_TXRDY (0x1u << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */ |
| 5091 | #define SSC_IER_TXEMPTY (0x1u << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */ |
| 5092 | #define SSC_IER_ENDTX (0x1u << 2) /**< \brief (SSC_IER) End of Transmission Interrupt Enable */ |
| 5093 | #define SSC_IER_TXBUFE (0x1u << 3) /**< \brief (SSC_IER) Transmit Buffer Empty Interrupt Enable */ |
| 5094 | #define SSC_IER_RXRDY (0x1u << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */ |
| 5095 | #define SSC_IER_OVRUN (0x1u << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */ |
| 5096 | #define SSC_IER_ENDRX (0x1u << 6) /**< \brief (SSC_IER) End of Reception Interrupt Enable */ |
| 5097 | #define SSC_IER_RXBUFF (0x1u << 7) /**< \brief (SSC_IER) Receive Buffer Full Interrupt Enable */ |
| 5098 | #define SSC_IER_CP0 (0x1u << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */ |
| 5099 | #define SSC_IER_CP1 (0x1u << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */ |
| 5100 | #define SSC_IER_TXSYN (0x1u << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */ |
| 5101 | #define SSC_IER_RXSYN (0x1u << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */ |
| 5102 | /* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */ |
| 5103 | #define SSC_IDR_TXRDY (0x1u << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */ |
| 5104 | #define SSC_IDR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */ |
| 5105 | #define SSC_IDR_ENDTX (0x1u << 2) /**< \brief (SSC_IDR) End of Transmission Interrupt Disable */ |
| 5106 | #define SSC_IDR_TXBUFE (0x1u << 3) /**< \brief (SSC_IDR) Transmit Buffer Empty Interrupt Disable */ |
| 5107 | #define SSC_IDR_RXRDY (0x1u << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */ |
| 5108 | #define SSC_IDR_OVRUN (0x1u << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */ |
| 5109 | #define SSC_IDR_ENDRX (0x1u << 6) /**< \brief (SSC_IDR) End of Reception Interrupt Disable */ |
| 5110 | #define SSC_IDR_RXBUFF (0x1u << 7) /**< \brief (SSC_IDR) Receive Buffer Full Interrupt Disable */ |
| 5111 | #define SSC_IDR_CP0 (0x1u << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */ |
| 5112 | #define SSC_IDR_CP1 (0x1u << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */ |
| 5113 | #define SSC_IDR_TXSYN (0x1u << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */ |
| 5114 | #define SSC_IDR_RXSYN (0x1u << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */ |
| 5115 | /* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */ |
| 5116 | #define SSC_IMR_TXRDY (0x1u << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */ |
| 5117 | #define SSC_IMR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */ |
| 5118 | #define SSC_IMR_ENDTX (0x1u << 2) /**< \brief (SSC_IMR) End of Transmission Interrupt Mask */ |
| 5119 | #define SSC_IMR_TXBUFE (0x1u << 3) /**< \brief (SSC_IMR) Transmit Buffer Empty Interrupt Mask */ |
| 5120 | #define SSC_IMR_RXRDY (0x1u << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */ |
| 5121 | #define SSC_IMR_OVRUN (0x1u << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */ |
| 5122 | #define SSC_IMR_ENDRX (0x1u << 6) /**< \brief (SSC_IMR) End of Reception Interrupt Mask */ |
| 5123 | #define SSC_IMR_RXBUFF (0x1u << 7) /**< \brief (SSC_IMR) Receive Buffer Full Interrupt Mask */ |
| 5124 | #define SSC_IMR_CP0 (0x1u << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */ |
| 5125 | #define SSC_IMR_CP1 (0x1u << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */ |
| 5126 | #define SSC_IMR_TXSYN (0x1u << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */ |
| 5127 | #define SSC_IMR_RXSYN (0x1u << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */ |
| 5128 | /* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protect Mode Register -------- */ |
| 5129 | #define SSC_WPMR_WPEN (0x1u << 0) /**< \brief (SSC_WPMR) Write Protect Enable */ |
| 5130 | #define SSC_WPMR_WPKEY_Pos 8 |
| 5131 | #define SSC_WPMR_WPKEY_Msk (0xffffffu << SSC_WPMR_WPKEY_Pos) /**< \brief (SSC_WPMR) Write Protect KEY */ |
| 5132 | #define SSC_WPMR_WPKEY(value) ((SSC_WPMR_WPKEY_Msk & ((value) << SSC_WPMR_WPKEY_Pos))) |
| 5133 | /* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protect Status Register -------- */ |
| 5134 | #define SSC_WPSR_WPVS (0x1u << 0) /**< \brief (SSC_WPSR) Write Protect Violation Status */ |
| 5135 | #define SSC_WPSR_WPVSRC_Pos 8 |
| 5136 | #define SSC_WPSR_WPVSRC_Msk (0xffffu << SSC_WPSR_WPVSRC_Pos) /**< \brief (SSC_WPSR) Write Protect Violation Source */ |
| 5137 | /* -------- SSC_RPR : (SSC Offset: 0x100) Receive Pointer Register -------- */ |
| 5138 | #define SSC_RPR_RXPTR_Pos 0 |
| 5139 | #define SSC_RPR_RXPTR_Msk (0xffffffffu << SSC_RPR_RXPTR_Pos) /**< \brief (SSC_RPR) Receive Pointer Register */ |
| 5140 | #define SSC_RPR_RXPTR(value) ((SSC_RPR_RXPTR_Msk & ((value) << SSC_RPR_RXPTR_Pos))) |
| 5141 | /* -------- SSC_RCR : (SSC Offset: 0x104) Receive Counter Register -------- */ |
| 5142 | #define SSC_RCR_RXCTR_Pos 0 |
| 5143 | #define SSC_RCR_RXCTR_Msk (0xffffu << SSC_RCR_RXCTR_Pos) /**< \brief (SSC_RCR) Receive Counter Register */ |
| 5144 | #define SSC_RCR_RXCTR(value) ((SSC_RCR_RXCTR_Msk & ((value) << SSC_RCR_RXCTR_Pos))) |
| 5145 | /* -------- SSC_TPR : (SSC Offset: 0x108) Transmit Pointer Register -------- */ |
| 5146 | #define SSC_TPR_TXPTR_Pos 0 |
| 5147 | #define SSC_TPR_TXPTR_Msk (0xffffffffu << SSC_TPR_TXPTR_Pos) /**< \brief (SSC_TPR) Transmit Counter Register */ |
| 5148 | #define SSC_TPR_TXPTR(value) ((SSC_TPR_TXPTR_Msk & ((value) << SSC_TPR_TXPTR_Pos))) |
| 5149 | /* -------- SSC_TCR : (SSC Offset: 0x10C) Transmit Counter Register -------- */ |
| 5150 | #define SSC_TCR_TXCTR_Pos 0 |
| 5151 | #define SSC_TCR_TXCTR_Msk (0xffffu << SSC_TCR_TXCTR_Pos) /**< \brief (SSC_TCR) Transmit Counter Register */ |
| 5152 | #define SSC_TCR_TXCTR(value) ((SSC_TCR_TXCTR_Msk & ((value) << SSC_TCR_TXCTR_Pos))) |
| 5153 | /* -------- SSC_RNPR : (SSC Offset: 0x110) Receive Next Pointer Register -------- */ |
| 5154 | #define SSC_RNPR_RXNPTR_Pos 0 |
| 5155 | #define SSC_RNPR_RXNPTR_Msk (0xffffffffu << SSC_RNPR_RXNPTR_Pos) /**< \brief (SSC_RNPR) Receive Next Pointer */ |
| 5156 | #define SSC_RNPR_RXNPTR(value) ((SSC_RNPR_RXNPTR_Msk & ((value) << SSC_RNPR_RXNPTR_Pos))) |
| 5157 | /* -------- SSC_RNCR : (SSC Offset: 0x114) Receive Next Counter Register -------- */ |
| 5158 | #define SSC_RNCR_RXNCTR_Pos 0 |
| 5159 | #define SSC_RNCR_RXNCTR_Msk (0xffffu << SSC_RNCR_RXNCTR_Pos) /**< \brief (SSC_RNCR) Receive Next Counter */ |
| 5160 | #define SSC_RNCR_RXNCTR(value) ((SSC_RNCR_RXNCTR_Msk & ((value) << SSC_RNCR_RXNCTR_Pos))) |
| 5161 | /* -------- SSC_TNPR : (SSC Offset: 0x118) Transmit Next Pointer Register -------- */ |
| 5162 | #define SSC_TNPR_TXNPTR_Pos 0 |
| 5163 | #define SSC_TNPR_TXNPTR_Msk (0xffffffffu << SSC_TNPR_TXNPTR_Pos) /**< \brief (SSC_TNPR) Transmit Next Pointer */ |
| 5164 | #define SSC_TNPR_TXNPTR(value) ((SSC_TNPR_TXNPTR_Msk & ((value) << SSC_TNPR_TXNPTR_Pos))) |
| 5165 | /* -------- SSC_TNCR : (SSC Offset: 0x11C) Transmit Next Counter Register -------- */ |
| 5166 | #define SSC_TNCR_TXNCTR_Pos 0 |
| 5167 | #define SSC_TNCR_TXNCTR_Msk (0xffffu << SSC_TNCR_TXNCTR_Pos) /**< \brief (SSC_TNCR) Transmit Counter Next */ |
| 5168 | #define SSC_TNCR_TXNCTR(value) ((SSC_TNCR_TXNCTR_Msk & ((value) << SSC_TNCR_TXNCTR_Pos))) |
| 5169 | /* -------- SSC_PTCR : (SSC Offset: 0x120) Transfer Control Register -------- */ |
| 5170 | #define SSC_PTCR_RXTEN (0x1u << 0) /**< \brief (SSC_PTCR) Receiver Transfer Enable */ |
| 5171 | #define SSC_PTCR_RXTDIS (0x1u << 1) /**< \brief (SSC_PTCR) Receiver Transfer Disable */ |
| 5172 | #define SSC_PTCR_TXTEN (0x1u << 8) /**< \brief (SSC_PTCR) Transmitter Transfer Enable */ |
| 5173 | #define SSC_PTCR_TXTDIS (0x1u << 9) /**< \brief (SSC_PTCR) Transmitter Transfer Disable */ |
| 5174 | /* -------- SSC_PTSR : (SSC Offset: 0x124) Transfer Status Register -------- */ |
| 5175 | #define SSC_PTSR_RXTEN (0x1u << 0) /**< \brief (SSC_PTSR) Receiver Transfer Enable */ |
| 5176 | #define SSC_PTSR_TXTEN (0x1u << 8) /**< \brief (SSC_PTSR) Transmitter Transfer Enable */ |
| 5177 | |
| 5178 | /*@}*/ |
| 5179 | |
| 5180 | /* ============================================================================= */ |
| 5181 | /** SOFTWARE API DEFINITION FOR Supply Controller */ |
| 5182 | /* ============================================================================= */ |
| 5183 | /** \addtogroup SAM3S_SUPC Supply Controller */ |
| 5184 | /*@{*/ |
| 5185 | |
| 5186 | #ifndef __ASSEMBLY__ |
| 5187 | /** \brief Supc hardware registers */ |
| 5188 | typedef struct { |
| 5189 | WoReg SUPC_CR; /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */ |
| 5190 | RwReg SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */ |
| 5191 | RwReg SUPC_MR; /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */ |
| 5192 | RwReg SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake Up Mode Register */ |
| 5193 | RwReg SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake Up Inputs Register */ |
| 5194 | RoReg SUPC_SR; /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */ |
| 5195 | } Supc; |
| 5196 | #endif /* __ASSEMBLY__ */ |
| 5197 | /* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */ |
| 5198 | #define SUPC_CR_VROFF (0x1u << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */ |
| 5199 | #define SUPC_CR_VROFF_NO_EFFECT (0x0u << 2) /**< \brief (SUPC_CR) no effect. */ |
| 5200 | #define SUPC_CR_VROFF_STOP_VREG (0x1u << 2) /**< \brief (SUPC_CR) if KEY is correct, asserts vddcore_nreset and stops the voltage regulator. */ |
| 5201 | #define SUPC_CR_XTALSEL (0x1u << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */ |
| 5202 | #define SUPC_CR_XTALSEL_NO_EFFECT (0x0u << 3) /**< \brief (SUPC_CR) no effect. */ |
| 5203 | #define SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1u << 3) /**< \brief (SUPC_CR) if KEY is correct, switches the slow clock on the crystal oscillator output. */ |
| 5204 | #define SUPC_CR_KEY_Pos 24 |
| 5205 | #define SUPC_CR_KEY_Msk (0xffu << SUPC_CR_KEY_Pos) /**< \brief (SUPC_CR) Password */ |
| 5206 | #define SUPC_CR_KEY(value) ((uint32_t)(SUPC_CR_KEY_Msk & ((value) << SUPC_CR_KEY_Pos))) |
| 5207 | /* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */ |
| 5208 | #define SUPC_SMMR_SMTH_Pos 0 |
| 5209 | #define SUPC_SMMR_SMTH_Msk (0xfu << SUPC_SMMR_SMTH_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */ |
| 5210 | #define SUPC_SMMR_SMTH_1_9V (0x0u << 0) /**< \brief (SUPC_SMMR) 1.9 V */ |
| 5211 | #define SUPC_SMMR_SMTH_2_0V (0x1u << 0) /**< \brief (SUPC_SMMR) 2.0 V */ |
| 5212 | #define SUPC_SMMR_SMTH_2_1V (0x2u << 0) /**< \brief (SUPC_SMMR) 2.1 V */ |
| 5213 | #define SUPC_SMMR_SMTH_2_2V (0x3u << 0) /**< \brief (SUPC_SMMR) 2.2 V */ |
| 5214 | #define SUPC_SMMR_SMTH_2_3V (0x4u << 0) /**< \brief (SUPC_SMMR) 2.3 V */ |
| 5215 | #define SUPC_SMMR_SMTH_2_4V (0x5u << 0) /**< \brief (SUPC_SMMR) 2.4 V */ |
| 5216 | #define SUPC_SMMR_SMTH_2_5V (0x6u << 0) /**< \brief (SUPC_SMMR) 2.5 V */ |
| 5217 | #define SUPC_SMMR_SMTH_2_6V (0x7u << 0) /**< \brief (SUPC_SMMR) 2.6 V */ |
| 5218 | #define SUPC_SMMR_SMTH_2_7V (0x8u << 0) /**< \brief (SUPC_SMMR) 2.7 V */ |
| 5219 | #define SUPC_SMMR_SMTH_2_8V (0x9u << 0) /**< \brief (SUPC_SMMR) 2.8 V */ |
| 5220 | #define SUPC_SMMR_SMTH_2_9V (0xAu << 0) /**< \brief (SUPC_SMMR) 2.9 V */ |
| 5221 | #define SUPC_SMMR_SMTH_3_0V (0xBu << 0) /**< \brief (SUPC_SMMR) 3.0 V */ |
| 5222 | #define SUPC_SMMR_SMTH_3_1V (0xCu << 0) /**< \brief (SUPC_SMMR) 3.1 V */ |
| 5223 | #define SUPC_SMMR_SMTH_3_2V (0xDu << 0) /**< \brief (SUPC_SMMR) 3.2 V */ |
| 5224 | #define SUPC_SMMR_SMTH_3_3V (0xEu << 0) /**< \brief (SUPC_SMMR) 3.3 V */ |
| 5225 | #define SUPC_SMMR_SMTH_3_4V (0xFu << 0) /**< \brief (SUPC_SMMR) 3.4 V */ |
| 5226 | #define SUPC_SMMR_SMSMPL_Pos 8 |
| 5227 | #define SUPC_SMMR_SMSMPL_Msk (0x7u << SUPC_SMMR_SMSMPL_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */ |
| 5228 | #define SUPC_SMMR_SMSMPL_SMD (0x0u << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */ |
| 5229 | #define SUPC_SMMR_SMSMPL_CSM (0x1u << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */ |
| 5230 | #define SUPC_SMMR_SMSMPL_32SLCK (0x2u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */ |
| 5231 | #define SUPC_SMMR_SMSMPL_256SLCK (0x3u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */ |
| 5232 | #define SUPC_SMMR_SMSMPL_2048SLCK (0x4u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */ |
| 5233 | #define SUPC_SMMR_SMRSTEN (0x1u << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */ |
| 5234 | #define SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_SMMR) the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. */ |
| 5235 | #define SUPC_SMMR_SMRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_SMMR) the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */ |
| 5236 | #define SUPC_SMMR_SMIEN (0x1u << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */ |
| 5237 | #define SUPC_SMMR_SMIEN_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is not affected when a supply monitor detection occurs. */ |
| 5238 | #define SUPC_SMMR_SMIEN_ENABLE (0x1u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is asserted when a supply monitor detection occurs. */ |
| 5239 | /* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */ |
| 5240 | #define SUPC_MR_BODRSTEN (0x1u << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */ |
| 5241 | #define SUPC_MR_BODRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_MR) the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. */ |
| 5242 | #define SUPC_MR_BODRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_MR) the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */ |
| 5243 | #define SUPC_MR_BODDIS (0x1u << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */ |
| 5244 | #define SUPC_MR_BODDIS_ENABLE (0x0u << 13) /**< \brief (SUPC_MR) the core brownout detector is enabled. */ |
| 5245 | #define SUPC_MR_BODDIS_DISABLE (0x1u << 13) /**< \brief (SUPC_MR) the core brownout detector is disabled. */ |
| 5246 | #define SUPC_MR_ONREG (0x1u << 14) /**< \brief (SUPC_MR) Voltage Regulator enable */ |
| 5247 | #define SUPC_MR_ONREG_ONREG_UNUSED (0x0u << 14) /**< \brief (SUPC_MR) Voltage Regulator is not used */ |
| 5248 | #define SUPC_MR_ONREG_ONREG_USED (0x1u << 14) /**< \brief (SUPC_MR) Voltage Regulator is used */ |
| 5249 | #define SUPC_MR_OSCBYPASS (0x1u << 20) /**< \brief (SUPC_MR) Oscillator Bypass */ |
| 5250 | #define SUPC_MR_OSCBYPASS_NO_EFFECT (0x0u << 20) /**< \brief (SUPC_MR) no effect. Clock selection depends on XTALSEL value. */ |
| 5251 | #define SUPC_MR_OSCBYPASS_BYPASS (0x1u << 20) /**< \brief (SUPC_MR) the 32-KHz XTAL oscillator is selected and is put in bypass mode. */ |
| 5252 | #define SUPC_MR_KEY_Pos 24 |
| 5253 | #define SUPC_MR_KEY_Msk (0xffu << SUPC_MR_KEY_Pos) /**< \brief (SUPC_MR) Password Key */ |
| 5254 | #define SUPC_MR_KEY(value) ((SUPC_MR_KEY_Msk & ((value) << SUPC_MR_KEY_Pos))) |
| 5255 | /* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake Up Mode Register -------- */ |
| 5256 | #define SUPC_WUMR_SMEN (0x1u << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake Up Enable */ |
| 5257 | #define SUPC_WUMR_SMEN_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection has no wake up effect. */ |
| 5258 | #define SUPC_WUMR_SMEN_ENABLE (0x1u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection forces the wake up of the core power supply. */ |
| 5259 | #define SUPC_WUMR_RTTEN (0x1u << 2) /**< \brief (SUPC_WUMR) Real Time Timer Wake Up Enable */ |
| 5260 | #define SUPC_WUMR_RTTEN_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal has no wake up effect. */ |
| 5261 | #define SUPC_WUMR_RTTEN_ENABLE (0x1u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal forces the wake up of the core power supply. */ |
| 5262 | #define SUPC_WUMR_RTCEN (0x1u << 3) /**< \brief (SUPC_WUMR) Real Time Clock Wake Up Enable */ |
| 5263 | #define SUPC_WUMR_RTCEN_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal has no wake up effect. */ |
| 5264 | #define SUPC_WUMR_RTCEN_ENABLE (0x1u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal forces the wake up of the core power supply. */ |
| 5265 | #define SUPC_WUMR_WKUPDBC_Pos 12 |
| 5266 | #define SUPC_WUMR_WKUPDBC_Msk (0x7u << SUPC_WUMR_WKUPDBC_Pos) /**< \brief (SUPC_WUMR) Wake Up Inputs Debouncer Period */ |
| 5267 | #define SUPC_WUMR_WKUPDBC_IMMEDIATE (0x0u << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */ |
| 5268 | #define SUPC_WUMR_WKUPDBC_3_SCLK (0x1u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods */ |
| 5269 | #define SUPC_WUMR_WKUPDBC_32_SCLK (0x2u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods */ |
| 5270 | #define SUPC_WUMR_WKUPDBC_512_SCLK (0x3u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods */ |
| 5271 | #define SUPC_WUMR_WKUPDBC_4096_SCLK (0x4u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods */ |
| 5272 | #define SUPC_WUMR_WKUPDBC_32768_SCLK (0x5u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods */ |
| 5273 | /* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake Up Inputs Register -------- */ |
| 5274 | #define SUPC_WUIR_WKUPEN0 (0x1u << 0) /**< \brief (SUPC_WUIR) Wake Up Input Enable 0 */ |
| 5275 | #define SUPC_WUIR_WKUPEN0_NOT_ENABLE (0x0u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ |
| 5276 | #define SUPC_WUIR_WKUPEN0_ENABLE (0x1u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ |
| 5277 | #define SUPC_WUIR_WKUPEN1 (0x1u << 1) /**< \brief (SUPC_WUIR) Wake Up Input Enable 1 */ |
| 5278 | #define SUPC_WUIR_WKUPEN1_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ |
| 5279 | #define SUPC_WUIR_WKUPEN1_ENABLE (0x1u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ |
| 5280 | #define SUPC_WUIR_WKUPEN2 (0x1u << 2) /**< \brief (SUPC_WUIR) Wake Up Input Enable 2 */ |
| 5281 | #define SUPC_WUIR_WKUPEN2_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ |
| 5282 | #define SUPC_WUIR_WKUPEN2_ENABLE (0x1u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ |
| 5283 | #define SUPC_WUIR_WKUPEN3 (0x1u << 3) /**< \brief (SUPC_WUIR) Wake Up Input Enable 3 */ |
| 5284 | #define SUPC_WUIR_WKUPEN3_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ |
| 5285 | #define SUPC_WUIR_WKUPEN3_ENABLE (0x1u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ |
| 5286 | #define SUPC_WUIR_WKUPEN4 (0x1u << 4) /**< \brief (SUPC_WUIR) Wake Up Input Enable 4 */ |
| 5287 | #define SUPC_WUIR_WKUPEN4_NOT_ENABLE (0x0u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ |
| 5288 | #define SUPC_WUIR_WKUPEN4_ENABLE (0x1u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ |
| 5289 | #define SUPC_WUIR_WKUPEN5 (0x1u << 5) /**< \brief (SUPC_WUIR) Wake Up Input Enable 5 */ |
| 5290 | #define SUPC_WUIR_WKUPEN5_NOT_ENABLE (0x0u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ |
| 5291 | #define SUPC_WUIR_WKUPEN5_ENABLE (0x1u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ |
| 5292 | #define SUPC_WUIR_WKUPEN6 (0x1u << 6) /**< \brief (SUPC_WUIR) Wake Up Input Enable 6 */ |
| 5293 | #define SUPC_WUIR_WKUPEN6_NOT_ENABLE (0x0u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ |
| 5294 | #define SUPC_WUIR_WKUPEN6_ENABLE (0x1u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ |
| 5295 | #define SUPC_WUIR_WKUPEN7 (0x1u << 7) /**< \brief (SUPC_WUIR) Wake Up Input Enable 7 */ |
| 5296 | #define SUPC_WUIR_WKUPEN7_NOT_ENABLE (0x0u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ |
| 5297 | #define SUPC_WUIR_WKUPEN7_ENABLE (0x1u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ |
| 5298 | #define SUPC_WUIR_WKUPEN8 (0x1u << 8) /**< \brief (SUPC_WUIR) Wake Up Input Enable 8 */ |
| 5299 | #define SUPC_WUIR_WKUPEN8_NOT_ENABLE (0x0u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ |
| 5300 | #define SUPC_WUIR_WKUPEN8_ENABLE (0x1u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ |
| 5301 | #define SUPC_WUIR_WKUPEN9 (0x1u << 9) /**< \brief (SUPC_WUIR) Wake Up Input Enable 9 */ |
| 5302 | #define SUPC_WUIR_WKUPEN9_NOT_ENABLE (0x0u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ |
| 5303 | #define SUPC_WUIR_WKUPEN9_ENABLE (0x1u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ |
| 5304 | #define SUPC_WUIR_WKUPEN10 (0x1u << 10) /**< \brief (SUPC_WUIR) Wake Up Input Enable 10 */ |
| 5305 | #define SUPC_WUIR_WKUPEN10_NOT_ENABLE (0x0u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ |
| 5306 | #define SUPC_WUIR_WKUPEN10_ENABLE (0x1u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ |
| 5307 | #define SUPC_WUIR_WKUPEN11 (0x1u << 11) /**< \brief (SUPC_WUIR) Wake Up Input Enable 11 */ |
| 5308 | #define SUPC_WUIR_WKUPEN11_NOT_ENABLE (0x0u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ |
| 5309 | #define SUPC_WUIR_WKUPEN11_ENABLE (0x1u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ |
| 5310 | #define SUPC_WUIR_WKUPEN12 (0x1u << 12) /**< \brief (SUPC_WUIR) Wake Up Input Enable 12 */ |
| 5311 | #define SUPC_WUIR_WKUPEN12_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ |
| 5312 | #define SUPC_WUIR_WKUPEN12_ENABLE (0x1u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ |
| 5313 | #define SUPC_WUIR_WKUPEN13 (0x1u << 13) /**< \brief (SUPC_WUIR) Wake Up Input Enable 13 */ |
| 5314 | #define SUPC_WUIR_WKUPEN13_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ |
| 5315 | #define SUPC_WUIR_WKUPEN13_ENABLE (0x1u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ |
| 5316 | #define SUPC_WUIR_WKUPEN14 (0x1u << 14) /**< \brief (SUPC_WUIR) Wake Up Input Enable 14 */ |
| 5317 | #define SUPC_WUIR_WKUPEN14_NOT_ENABLE (0x0u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ |
| 5318 | #define SUPC_WUIR_WKUPEN14_ENABLE (0x1u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ |
| 5319 | #define SUPC_WUIR_WKUPEN15 (0x1u << 15) /**< \brief (SUPC_WUIR) Wake Up Input Enable 15 */ |
| 5320 | #define SUPC_WUIR_WKUPEN15_NOT_ENABLE (0x0u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ |
| 5321 | #define SUPC_WUIR_WKUPEN15_ENABLE (0x1u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ |
| 5322 | #define SUPC_WUIR_WKUPT0 (0x1u << 16) /**< \brief (SUPC_WUIR) Wake Up Input Transition 0 */ |
| 5323 | #define SUPC_WUIR_WKUPT0_HIGH_TO_LOW (0x0u << 16) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ |
| 5324 | #define SUPC_WUIR_WKUPT0_LOW_TO_HIGH (0x1u << 16) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ |
| 5325 | #define SUPC_WUIR_WKUPT1 (0x1u << 17) /**< \brief (SUPC_WUIR) Wake Up Input Transition 1 */ |
| 5326 | #define SUPC_WUIR_WKUPT1_HIGH_TO_LOW (0x0u << 17) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ |
| 5327 | #define SUPC_WUIR_WKUPT1_LOW_TO_HIGH (0x1u << 17) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ |
| 5328 | #define SUPC_WUIR_WKUPT2 (0x1u << 18) /**< \brief (SUPC_WUIR) Wake Up Input Transition 2 */ |
| 5329 | #define SUPC_WUIR_WKUPT2_HIGH_TO_LOW (0x0u << 18) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ |
| 5330 | #define SUPC_WUIR_WKUPT2_LOW_TO_HIGH (0x1u << 18) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ |
| 5331 | #define SUPC_WUIR_WKUPT3 (0x1u << 19) /**< \brief (SUPC_WUIR) Wake Up Input Transition 3 */ |
| 5332 | #define SUPC_WUIR_WKUPT3_HIGH_TO_LOW (0x0u << 19) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ |
| 5333 | #define SUPC_WUIR_WKUPT3_LOW_TO_HIGH (0x1u << 19) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ |
| 5334 | #define SUPC_WUIR_WKUPT4 (0x1u << 20) /**< \brief (SUPC_WUIR) Wake Up Input Transition 4 */ |
| 5335 | #define SUPC_WUIR_WKUPT4_HIGH_TO_LOW (0x0u << 20) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ |
| 5336 | #define SUPC_WUIR_WKUPT4_LOW_TO_HIGH (0x1u << 20) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ |
| 5337 | #define SUPC_WUIR_WKUPT5 (0x1u << 21) /**< \brief (SUPC_WUIR) Wake Up Input Transition 5 */ |
| 5338 | #define SUPC_WUIR_WKUPT5_HIGH_TO_LOW (0x0u << 21) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ |
| 5339 | #define SUPC_WUIR_WKUPT5_LOW_TO_HIGH (0x1u << 21) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ |
| 5340 | #define SUPC_WUIR_WKUPT6 (0x1u << 22) /**< \brief (SUPC_WUIR) Wake Up Input Transition 6 */ |
| 5341 | #define SUPC_WUIR_WKUPT6_HIGH_TO_LOW (0x0u << 22) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ |
| 5342 | #define SUPC_WUIR_WKUPT6_LOW_TO_HIGH (0x1u << 22) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ |
| 5343 | #define SUPC_WUIR_WKUPT7 (0x1u << 23) /**< \brief (SUPC_WUIR) Wake Up Input Transition 7 */ |
| 5344 | #define SUPC_WUIR_WKUPT7_HIGH_TO_LOW (0x0u << 23) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ |
| 5345 | #define SUPC_WUIR_WKUPT7_LOW_TO_HIGH (0x1u << 23) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ |
| 5346 | #define SUPC_WUIR_WKUPT8 (0x1u << 24) /**< \brief (SUPC_WUIR) Wake Up Input Transition 8 */ |
| 5347 | #define SUPC_WUIR_WKUPT8_HIGH_TO_LOW (0x0u << 24) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ |
| 5348 | #define SUPC_WUIR_WKUPT8_LOW_TO_HIGH (0x1u << 24) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ |
| 5349 | #define SUPC_WUIR_WKUPT9 (0x1u << 25) /**< \brief (SUPC_WUIR) Wake Up Input Transition 9 */ |
| 5350 | #define SUPC_WUIR_WKUPT9_HIGH_TO_LOW (0x0u << 25) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ |
| 5351 | #define SUPC_WUIR_WKUPT9_LOW_TO_HIGH (0x1u << 25) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ |
| 5352 | #define SUPC_WUIR_WKUPT10 (0x1u << 26) /**< \brief (SUPC_WUIR) Wake Up Input Transition 10 */ |
| 5353 | #define SUPC_WUIR_WKUPT10_HIGH_TO_LOW (0x0u << 26) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ |
| 5354 | #define SUPC_WUIR_WKUPT10_LOW_TO_HIGH (0x1u << 26) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ |
| 5355 | #define SUPC_WUIR_WKUPT11 (0x1u << 27) /**< \brief (SUPC_WUIR) Wake Up Input Transition 11 */ |
| 5356 | #define SUPC_WUIR_WKUPT11_HIGH_TO_LOW (0x0u << 27) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ |
| 5357 | #define SUPC_WUIR_WKUPT11_LOW_TO_HIGH (0x1u << 27) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ |
| 5358 | #define SUPC_WUIR_WKUPT12 (0x1u << 28) /**< \brief (SUPC_WUIR) Wake Up Input Transition 12 */ |
| 5359 | #define SUPC_WUIR_WKUPT12_HIGH_TO_LOW (0x0u << 28) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ |
| 5360 | #define SUPC_WUIR_WKUPT12_LOW_TO_HIGH (0x1u << 28) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ |
| 5361 | #define SUPC_WUIR_WKUPT13 (0x1u << 29) /**< \brief (SUPC_WUIR) Wake Up Input Transition 13 */ |
| 5362 | #define SUPC_WUIR_WKUPT13_HIGH_TO_LOW (0x0u << 29) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ |
| 5363 | #define SUPC_WUIR_WKUPT13_LOW_TO_HIGH (0x1u << 29) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ |
| 5364 | #define SUPC_WUIR_WKUPT14 (0x1u << 30) /**< \brief (SUPC_WUIR) Wake Up Input Transition 14 */ |
| 5365 | #define SUPC_WUIR_WKUPT14_HIGH_TO_LOW (0x0u << 30) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ |
| 5366 | #define SUPC_WUIR_WKUPT14_LOW_TO_HIGH (0x1u << 30) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ |
| 5367 | #define SUPC_WUIR_WKUPT15 (0x1u << 31) /**< \brief (SUPC_WUIR) Wake Up Input Transition 15 */ |
| 5368 | #define SUPC_WUIR_WKUPT15_HIGH_TO_LOW (0x0u << 31) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ |
| 5369 | #define SUPC_WUIR_WKUPT15_LOW_TO_HIGH (0x1u << 31) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ |
| 5370 | /* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */ |
| 5371 | #define SUPC_SR_WKUPS (0x1u << 1) /**< \brief (SUPC_SR) WKUP Wake Up Status */ |
| 5372 | #define SUPC_SR_WKUPS_NO (0x0u << 1) /**< \brief (SUPC_SR) no wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ |
| 5373 | #define SUPC_SR_WKUPS_PRESENT (0x1u << 1) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ |
| 5374 | #define SUPC_SR_SMWS (0x1u << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake Up Status */ |
| 5375 | #define SUPC_SR_SMWS_NO (0x0u << 2) /**< \brief (SUPC_SR) no wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ |
| 5376 | #define SUPC_SR_SMWS_PRESENT (0x1u << 2) /**< \brief (SUPC_SR) at least one wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ |
| 5377 | #define SUPC_SR_BODRSTS (0x1u << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status */ |
| 5378 | #define SUPC_SR_BODRSTS_NO (0x0u << 3) /**< \brief (SUPC_SR) no core brownout rising edge event has been detected since the last read of the SUPC_SR. */ |
| 5379 | #define SUPC_SR_BODRSTS_PRESENT (0x1u << 3) /**< \brief (SUPC_SR) at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */ |
| 5380 | #define SUPC_SR_SMRSTS (0x1u << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status */ |
| 5381 | #define SUPC_SR_SMRSTS_NO (0x0u << 4) /**< \brief (SUPC_SR) no supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ |
| 5382 | #define SUPC_SR_SMRSTS_PRESENT (0x1u << 4) /**< \brief (SUPC_SR) at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ |
| 5383 | #define SUPC_SR_SMS (0x1u << 5) /**< \brief (SUPC_SR) Supply Monitor Status */ |
| 5384 | #define SUPC_SR_SMS_NO (0x0u << 5) /**< \brief (SUPC_SR) no supply monitor detection since the last read of SUPC_SR. */ |
| 5385 | #define SUPC_SR_SMS_PRESENT (0x1u << 5) /**< \brief (SUPC_SR) at least one supply monitor detection since the last read of SUPC_SR. */ |
| 5386 | #define SUPC_SR_SMOS (0x1u << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */ |
| 5387 | #define SUPC_SR_SMOS_HIGH (0x0u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO higher than its threshold at its last measurement. */ |
| 5388 | #define SUPC_SR_SMOS_LOW (0x1u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO lower than its threshold at its last measurement. */ |
| 5389 | #define SUPC_SR_OSCSEL (0x1u << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */ |
| 5390 | #define SUPC_SR_OSCSEL_RC (0x0u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. */ |
| 5391 | #define SUPC_SR_OSCSEL_CRYST (0x1u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the 32-kHz crystal oscillator. */ |
| 5392 | #define SUPC_SR_WKUPIS0 (0x1u << 16) /**< \brief (SUPC_SR) WKUP Input Status 0 */ |
| 5393 | #define SUPC_SR_WKUPIS0_DIS (0x0u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ |
| 5394 | #define SUPC_SR_WKUPIS0_EN (0x1u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ |
| 5395 | #define SUPC_SR_WKUPIS1 (0x1u << 17) /**< \brief (SUPC_SR) WKUP Input Status 1 */ |
| 5396 | #define SUPC_SR_WKUPIS1_DIS (0x0u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ |
| 5397 | #define SUPC_SR_WKUPIS1_EN (0x1u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ |
| 5398 | #define SUPC_SR_WKUPIS2 (0x1u << 18) /**< \brief (SUPC_SR) WKUP Input Status 2 */ |
| 5399 | #define SUPC_SR_WKUPIS2_DIS (0x0u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ |
| 5400 | #define SUPC_SR_WKUPIS2_EN (0x1u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ |
| 5401 | #define SUPC_SR_WKUPIS3 (0x1u << 19) /**< \brief (SUPC_SR) WKUP Input Status 3 */ |
| 5402 | #define SUPC_SR_WKUPIS3_DIS (0x0u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ |
| 5403 | #define SUPC_SR_WKUPIS3_EN (0x1u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ |
| 5404 | #define SUPC_SR_WKUPIS4 (0x1u << 20) /**< \brief (SUPC_SR) WKUP Input Status 4 */ |
| 5405 | #define SUPC_SR_WKUPIS4_DIS (0x0u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ |
| 5406 | #define SUPC_SR_WKUPIS4_EN (0x1u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ |
| 5407 | #define SUPC_SR_WKUPIS5 (0x1u << 21) /**< \brief (SUPC_SR) WKUP Input Status 5 */ |
| 5408 | #define SUPC_SR_WKUPIS5_DIS (0x0u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ |
| 5409 | #define SUPC_SR_WKUPIS5_EN (0x1u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ |
| 5410 | #define SUPC_SR_WKUPIS6 (0x1u << 22) /**< \brief (SUPC_SR) WKUP Input Status 6 */ |
| 5411 | #define SUPC_SR_WKUPIS6_DIS (0x0u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ |
| 5412 | #define SUPC_SR_WKUPIS6_EN (0x1u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ |
| 5413 | #define SUPC_SR_WKUPIS7 (0x1u << 23) /**< \brief (SUPC_SR) WKUP Input Status 7 */ |
| 5414 | #define SUPC_SR_WKUPIS7_DIS (0x0u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ |
| 5415 | #define SUPC_SR_WKUPIS7_EN (0x1u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ |
| 5416 | #define SUPC_SR_WKUPIS8 (0x1u << 24) /**< \brief (SUPC_SR) WKUP Input Status 8 */ |
| 5417 | #define SUPC_SR_WKUPIS8_DIS (0x0u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ |
| 5418 | #define SUPC_SR_WKUPIS8_EN (0x1u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ |
| 5419 | #define SUPC_SR_WKUPIS9 (0x1u << 25) /**< \brief (SUPC_SR) WKUP Input Status 9 */ |
| 5420 | #define SUPC_SR_WKUPIS9_DIS (0x0u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ |
| 5421 | #define SUPC_SR_WKUPIS9_EN (0x1u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ |
| 5422 | #define SUPC_SR_WKUPIS10 (0x1u << 26) /**< \brief (SUPC_SR) WKUP Input Status 10 */ |
| 5423 | #define SUPC_SR_WKUPIS10_DIS (0x0u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ |
| 5424 | #define SUPC_SR_WKUPIS10_EN (0x1u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ |
| 5425 | #define SUPC_SR_WKUPIS11 (0x1u << 27) /**< \brief (SUPC_SR) WKUP Input Status 11 */ |
| 5426 | #define SUPC_SR_WKUPIS11_DIS (0x0u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ |
| 5427 | #define SUPC_SR_WKUPIS11_EN (0x1u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ |
| 5428 | #define SUPC_SR_WKUPIS12 (0x1u << 28) /**< \brief (SUPC_SR) WKUP Input Status 12 */ |
| 5429 | #define SUPC_SR_WKUPIS12_DIS (0x0u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ |
| 5430 | #define SUPC_SR_WKUPIS12_EN (0x1u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ |
| 5431 | #define SUPC_SR_WKUPIS13 (0x1u << 29) /**< \brief (SUPC_SR) WKUP Input Status 13 */ |
| 5432 | #define SUPC_SR_WKUPIS13_DIS (0x0u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ |
| 5433 | #define SUPC_SR_WKUPIS13_EN (0x1u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ |
| 5434 | #define SUPC_SR_WKUPIS14 (0x1u << 30) /**< \brief (SUPC_SR) WKUP Input Status 14 */ |
| 5435 | #define SUPC_SR_WKUPIS14_DIS (0x0u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ |
| 5436 | #define SUPC_SR_WKUPIS14_EN (0x1u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ |
| 5437 | #define SUPC_SR_WKUPIS15 (0x1u << 31) /**< \brief (SUPC_SR) WKUP Input Status 15 */ |
| 5438 | #define SUPC_SR_WKUPIS15_DIS (0x0u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ |
| 5439 | #define SUPC_SR_WKUPIS15_EN (0x1u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ |
| 5440 | |
| 5441 | /*@}*/ |
| 5442 | |
| 5443 | /* ============================================================================= */ |
| 5444 | /** SOFTWARE API DEFINITION FOR Timer Counter */ |
| 5445 | /* ============================================================================= */ |
| 5446 | /** \addtogroup SAM3S_TC Timer Counter */ |
| 5447 | /*@{*/ |
| 5448 | |
| 5449 | #ifndef __ASSEMBLY__ |
| 5450 | /** \brief TcChannel hardware registers */ |
| 5451 | typedef struct { |
| 5452 | RwReg TC_CCR; /**< \brief (TcChannel Offset: 0x0) Channel Control Register */ |
| 5453 | RwReg TC_CMR; /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */ |
| 5454 | RwReg TC_SMMR; /**< \brief (TcChannel Offset: 0x8) Stepper Motor Mode Register */ |
| 5455 | RwReg Reserved1[1]; |
| 5456 | RwReg TC_CV; /**< \brief (TcChannel Offset: 0x10) Counter Value */ |
| 5457 | RwReg TC_RA; /**< \brief (TcChannel Offset: 0x14) Register A */ |
| 5458 | RwReg TC_RB; /**< \brief (TcChannel Offset: 0x18) Register B */ |
| 5459 | RwReg TC_RC; /**< \brief (TcChannel Offset: 0x1C) Register C */ |
| 5460 | RwReg TC_SR; /**< \brief (TcChannel Offset: 0x20) Status Register */ |
| 5461 | RwReg TC_IER; /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */ |
| 5462 | RwReg TC_IDR; /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */ |
| 5463 | RwReg TC_IMR; /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */ |
| 5464 | RwReg Reserved2[4]; |
| 5465 | } TcChannel; |
| 5466 | /** \brief Tc hardware registers */ |
| 5467 | typedef struct { |
| 5468 | TcChannel TC_CHANNEL[3]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */ |
| 5469 | WoReg TC_BCR; /**< \brief (Tc Offset: 0xC0) Block Control Register */ |
| 5470 | RwReg TC_BMR; /**< \brief (Tc Offset: 0xC4) Block Mode Register */ |
| 5471 | WoReg TC_QIER; /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */ |
| 5472 | WoReg TC_QIDR; /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */ |
| 5473 | RoReg TC_QIMR; /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */ |
| 5474 | RoReg TC_QISR; /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */ |
| 5475 | RwReg TC_FMR; /**< \brief (Tc Offset: 0xD8) Fault Mode Register */ |
| 5476 | RwReg Reserved1[2]; |
| 5477 | RwReg TC_WPMR; /**< \brief (Tc Offset: 0xE4) Write Protect Mode Register */ |
| 5478 | } Tc; |
| 5479 | #endif /* __ASSEMBLY__ */ |
| 5480 | /* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */ |
| 5481 | #define TC_CCR_CLKEN (0x1u << 0) /**< \brief (TC_CCR) Counter Clock Enable Command */ |
| 5482 | #define TC_CCR_CLKDIS (0x1u << 1) /**< \brief (TC_CCR) Counter Clock Disable Command */ |
| 5483 | #define TC_CCR_SWTRG (0x1u << 2) /**< \brief (TC_CCR) Software Trigger Command */ |
| 5484 | /* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */ |
| 5485 | #define TC_CMR_TCCLKS_Pos 0 |
| 5486 | #define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /**< \brief (TC_CMR) Clock Selection */ |
| 5487 | #define TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CMR) Clock selected: TCLK1 */ |
| 5488 | #define TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CMR) Clock selected: TCLK2 */ |
| 5489 | #define TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CMR) Clock selected: TCLK3 */ |
| 5490 | #define TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CMR) Clock selected: TCLK4 */ |
| 5491 | #define TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CMR) Clock selected: TCLK5 */ |
| 5492 | #define TC_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CMR) Clock selected: XC0 */ |
| 5493 | #define TC_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CMR) Clock selected: XC1 */ |
| 5494 | #define TC_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CMR) Clock selected: XC2 */ |
| 5495 | #define TC_CMR_CLKI (0x1u << 3) /**< \brief (TC_CMR) Clock Invert */ |
| 5496 | #define TC_CMR_BURST_Pos 4 |
| 5497 | #define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /**< \brief (TC_CMR) Burst Signal Selection */ |
| 5498 | #define TC_CMR_BURST_NONE (0x0u << 4) /**< \brief (TC_CMR) The clock is not gated by an external signal. */ |
| 5499 | #define TC_CMR_BURST_XC0 (0x1u << 4) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */ |
| 5500 | #define TC_CMR_BURST_XC1 (0x2u << 4) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */ |
| 5501 | #define TC_CMR_BURST_XC2 (0x3u << 4) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */ |
| 5502 | #define TC_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */ |
| 5503 | #define TC_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */ |
| 5504 | #define TC_CMR_ETRGEDG_Pos 8 |
| 5505 | #define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /**< \brief (TC_CMR) External Trigger Edge Selection */ |
| 5506 | #define TC_CMR_ETRGEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) The clock is not gated by an external signal. */ |
| 5507 | #define TC_CMR_ETRGEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */ |
| 5508 | #define TC_CMR_ETRGEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */ |
| 5509 | #define TC_CMR_ETRGEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */ |
| 5510 | #define TC_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */ |
| 5511 | #define TC_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CMR) RC Compare Trigger Enable */ |
| 5512 | #define TC_CMR_WAVE (0x1u << 15) /**< \brief (TC_CMR) */ |
| 5513 | #define TC_CMR_LDRA_Pos 16 |
| 5514 | #define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /**< \brief (TC_CMR) RA Loading Selection */ |
| 5515 | #define TC_CMR_LDRA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */ |
| 5516 | #define TC_CMR_LDRA_RISING (0x1u << 16) /**< \brief (TC_CMR) Rising edge of TIOA */ |
| 5517 | #define TC_CMR_LDRA_FALLING (0x2u << 16) /**< \brief (TC_CMR) Falling edge of TIOA */ |
| 5518 | #define TC_CMR_LDRA_EDGE (0x3u << 16) /**< \brief (TC_CMR) Each edge of TIOA */ |
| 5519 | #define TC_CMR_LDRB_Pos 18 |
| 5520 | #define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /**< \brief (TC_CMR) RB Loading Selection */ |
| 5521 | #define TC_CMR_LDRB_NONE (0x0u << 18) /**< \brief (TC_CMR) None */ |
| 5522 | #define TC_CMR_LDRB_RISING (0x1u << 18) /**< \brief (TC_CMR) Rising edge of TIOA */ |
| 5523 | #define TC_CMR_LDRB_FALLING (0x2u << 18) /**< \brief (TC_CMR) Falling edge of TIOA */ |
| 5524 | #define TC_CMR_LDRB_EDGE (0x3u << 18) /**< \brief (TC_CMR) Each edge of TIOA */ |
| 5525 | #define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */ |
| 5526 | #define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */ |
| 5527 | #define TC_CMR_EEVTEDG_Pos 8 |
| 5528 | #define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */ |
| 5529 | #define TC_CMR_EEVTEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) None */ |
| 5530 | #define TC_CMR_EEVTEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */ |
| 5531 | #define TC_CMR_EEVTEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */ |
| 5532 | #define TC_CMR_EEVTEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */ |
| 5533 | #define TC_CMR_EEVT_Pos 10 |
| 5534 | #define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /**< \brief (TC_CMR) External Event Selection */ |
| 5535 | #define TC_CMR_EEVT_TIOB (0x0u << 10) /**< \brief (TC_CMR) TIOB */ |
| 5536 | #define TC_CMR_EEVT_XC0 (0x1u << 10) /**< \brief (TC_CMR) XC0 */ |
| 5537 | #define TC_CMR_EEVT_XC1 (0x2u << 10) /**< \brief (TC_CMR) XC1 */ |
| 5538 | #define TC_CMR_EEVT_XC2 (0x3u << 10) /**< \brief (TC_CMR) XC2 */ |
| 5539 | #define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */ |
| 5540 | #define TC_CMR_WAVSEL_Pos 13 |
| 5541 | #define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */ |
| 5542 | #define TC_CMR_WAVSEL_UP (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */ |
| 5543 | #define TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */ |
| 5544 | #define TC_CMR_WAVSEL_UP_RC (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */ |
| 5545 | #define TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */ |
| 5546 | #define TC_CMR_ACPA_Pos 16 |
| 5547 | #define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */ |
| 5548 | #define TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */ |
| 5549 | #define TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) Set */ |
| 5550 | #define TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) Clear */ |
| 5551 | #define TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) Toggle */ |
| 5552 | #define TC_CMR_ACPC_Pos 18 |
| 5553 | #define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */ |
| 5554 | #define TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) None */ |
| 5555 | #define TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) Set */ |
| 5556 | #define TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) Clear */ |
| 5557 | #define TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) Toggle */ |
| 5558 | #define TC_CMR_AEEVT_Pos 20 |
| 5559 | #define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */ |
| 5560 | #define TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) None */ |
| 5561 | #define TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) Set */ |
| 5562 | #define TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) Clear */ |
| 5563 | #define TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) Toggle */ |
| 5564 | #define TC_CMR_ASWTRG_Pos 22 |
| 5565 | #define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */ |
| 5566 | #define TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) None */ |
| 5567 | #define TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) Set */ |
| 5568 | #define TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) Clear */ |
| 5569 | #define TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) Toggle */ |
| 5570 | #define TC_CMR_BCPB_Pos 24 |
| 5571 | #define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */ |
| 5572 | #define TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) None */ |
| 5573 | #define TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) Set */ |
| 5574 | #define TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) Clear */ |
| 5575 | #define TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) Toggle */ |
| 5576 | #define TC_CMR_BCPC_Pos 26 |
| 5577 | #define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */ |
| 5578 | #define TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) None */ |
| 5579 | #define TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) Set */ |
| 5580 | #define TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) Clear */ |
| 5581 | #define TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) Toggle */ |
| 5582 | #define TC_CMR_BEEVT_Pos 28 |
| 5583 | #define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */ |
| 5584 | #define TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) None */ |
| 5585 | #define TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) Set */ |
| 5586 | #define TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) Clear */ |
| 5587 | #define TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) Toggle */ |
| 5588 | #define TC_CMR_BSWTRG_Pos 30 |
| 5589 | #define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */ |
| 5590 | #define TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) None */ |
| 5591 | #define TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) Set */ |
| 5592 | #define TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) Clear */ |
| 5593 | #define TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) Toggle */ |
| 5594 | /* -------- TC_SMMR : (TC Offset: N/A) Stepper Motor Mode Register -------- */ |
| 5595 | #define TC_SMMR_GCEN (0x1u << 0) /**< \brief (TC_SMMR) Gray Count Enable */ |
| 5596 | #define TC_SMMR_DOWN (0x1u << 1) /**< \brief (TC_SMMR) DOWN Count */ |
| 5597 | /* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */ |
| 5598 | #define TC_CV_CV_Pos 0 |
| 5599 | #define TC_CV_CV_Msk (0xffffu << TC_CV_CV_Pos) /**< \brief (TC_CV) Counter Value */ |
| 5600 | /* -------- TC_RA : (TC Offset: N/A) Register A -------- */ |
| 5601 | #define TC_RA_RA_Pos 0 |
| 5602 | #define TC_RA_RA_Msk (0xffffu << TC_RA_RA_Pos) /**< \brief (TC_RA) Register A */ |
| 5603 | #define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos))) |
| 5604 | /* -------- TC_RB : (TC Offset: N/A) Register B -------- */ |
| 5605 | #define TC_RB_RB_Pos 0 |
| 5606 | #define TC_RB_RB_Msk (0xffffu << TC_RB_RB_Pos) /**< \brief (TC_RB) Register B */ |
| 5607 | #define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos))) |
| 5608 | /* -------- TC_RC : (TC Offset: N/A) Register C -------- */ |
| 5609 | #define TC_RC_RC_Pos 0 |
| 5610 | #define TC_RC_RC_Msk (0xffffu << TC_RC_RC_Pos) /**< \brief (TC_RC) Register C */ |
| 5611 | #define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos))) |
| 5612 | /* -------- TC_SR : (TC Offset: N/A) Status Register -------- */ |
| 5613 | #define TC_SR_COVFS (0x1u << 0) /**< \brief (TC_SR) Counter Overflow Status */ |
| 5614 | #define TC_SR_LOVRS (0x1u << 1) /**< \brief (TC_SR) Load Overrun Status */ |
| 5615 | #define TC_SR_CPAS (0x1u << 2) /**< \brief (TC_SR) RA Compare Status */ |
| 5616 | #define TC_SR_CPBS (0x1u << 3) /**< \brief (TC_SR) RB Compare Status */ |
| 5617 | #define TC_SR_CPCS (0x1u << 4) /**< \brief (TC_SR) RC Compare Status */ |
| 5618 | #define TC_SR_LDRAS (0x1u << 5) /**< \brief (TC_SR) RA Loading Status */ |
| 5619 | #define TC_SR_LDRBS (0x1u << 6) /**< \brief (TC_SR) RB Loading Status */ |
| 5620 | #define TC_SR_ETRGS (0x1u << 7) /**< \brief (TC_SR) External Trigger Status */ |
| 5621 | #define TC_SR_CLKSTA (0x1u << 16) /**< \brief (TC_SR) Clock Enabling Status */ |
| 5622 | #define TC_SR_MTIOA (0x1u << 17) /**< \brief (TC_SR) TIOA Mirror */ |
| 5623 | #define TC_SR_MTIOB (0x1u << 18) /**< \brief (TC_SR) TIOB Mirror */ |
| 5624 | /* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */ |
| 5625 | #define TC_IER_COVFS (0x1u << 0) /**< \brief (TC_IER) Counter Overflow */ |
| 5626 | #define TC_IER_LOVRS (0x1u << 1) /**< \brief (TC_IER) Load Overrun */ |
| 5627 | #define TC_IER_CPAS (0x1u << 2) /**< \brief (TC_IER) RA Compare */ |
| 5628 | #define TC_IER_CPBS (0x1u << 3) /**< \brief (TC_IER) RB Compare */ |
| 5629 | #define TC_IER_CPCS (0x1u << 4) /**< \brief (TC_IER) RC Compare */ |
| 5630 | #define TC_IER_LDRAS (0x1u << 5) /**< \brief (TC_IER) RA Loading */ |
| 5631 | #define TC_IER_LDRBS (0x1u << 6) /**< \brief (TC_IER) RB Loading */ |
| 5632 | #define TC_IER_ETRGS (0x1u << 7) /**< \brief (TC_IER) External Trigger */ |
| 5633 | /* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */ |
| 5634 | #define TC_IDR_COVFS (0x1u << 0) /**< \brief (TC_IDR) Counter Overflow */ |
| 5635 | #define TC_IDR_LOVRS (0x1u << 1) /**< \brief (TC_IDR) Load Overrun */ |
| 5636 | #define TC_IDR_CPAS (0x1u << 2) /**< \brief (TC_IDR) RA Compare */ |
| 5637 | #define TC_IDR_CPBS (0x1u << 3) /**< \brief (TC_IDR) RB Compare */ |
| 5638 | #define TC_IDR_CPCS (0x1u << 4) /**< \brief (TC_IDR) RC Compare */ |
| 5639 | #define TC_IDR_LDRAS (0x1u << 5) /**< \brief (TC_IDR) RA Loading */ |
| 5640 | #define TC_IDR_LDRBS (0x1u << 6) /**< \brief (TC_IDR) RB Loading */ |
| 5641 | #define TC_IDR_ETRGS (0x1u << 7) /**< \brief (TC_IDR) External Trigger */ |
| 5642 | /* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */ |
| 5643 | #define TC_IMR_COVFS (0x1u << 0) /**< \brief (TC_IMR) Counter Overflow */ |
| 5644 | #define TC_IMR_LOVRS (0x1u << 1) /**< \brief (TC_IMR) Load Overrun */ |
| 5645 | #define TC_IMR_CPAS (0x1u << 2) /**< \brief (TC_IMR) RA Compare */ |
| 5646 | #define TC_IMR_CPBS (0x1u << 3) /**< \brief (TC_IMR) RB Compare */ |
| 5647 | #define TC_IMR_CPCS (0x1u << 4) /**< \brief (TC_IMR) RC Compare */ |
| 5648 | #define TC_IMR_LDRAS (0x1u << 5) /**< \brief (TC_IMR) RA Loading */ |
| 5649 | #define TC_IMR_LDRBS (0x1u << 6) /**< \brief (TC_IMR) RB Loading */ |
| 5650 | #define TC_IMR_ETRGS (0x1u << 7) /**< \brief (TC_IMR) External Trigger */ |
| 5651 | /* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */ |
| 5652 | #define TC_BCR_SYNC (0x1u << 0) /**< \brief (TC_BCR) Synchro Command */ |
| 5653 | /* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */ |
| 5654 | #define TC_BMR_TC0XC0S_Pos 0 |
| 5655 | #define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /**< \brief (TC_BMR) External Clock Signal 0 Selection */ |
| 5656 | #define TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TCLK0 */ |
| 5657 | #define TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA1 */ |
| 5658 | #define TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA2 */ |
| 5659 | #define TC_BMR_TC1XC1S_Pos 2 |
| 5660 | #define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /**< \brief (TC_BMR) External Clock Signal 1 Selection */ |
| 5661 | #define TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TCLK1 */ |
| 5662 | #define TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA0 */ |
| 5663 | #define TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA2 */ |
| 5664 | #define TC_BMR_TC2XC2S_Pos 4 |
| 5665 | #define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /**< \brief (TC_BMR) External Clock Signal 2 Selection */ |
| 5666 | #define TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TCLK2 */ |
| 5667 | #define TC_BMR_TC2XC2S_TIOA1 (0x2u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA1 */ |
| 5668 | #define TC_BMR_TC2XC2S_TIOA2 (0x3u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA2 */ |
| 5669 | #define TC_BMR_QDEN (0x1u << 8) /**< \brief (TC_BMR) Quadrature Decoder ENabled */ |
| 5670 | #define TC_BMR_POSEN (0x1u << 9) /**< \brief (TC_BMR) POSition ENabled */ |
| 5671 | #define TC_BMR_SPEEDEN (0x1u << 10) /**< \brief (TC_BMR) SPEED ENabled */ |
| 5672 | #define TC_BMR_QDTRANS (0x1u << 11) /**< \brief (TC_BMR) Quadrature Decoding TRANSparent */ |
| 5673 | #define TC_BMR_EDGPHA (0x1u << 12) /**< \brief (TC_BMR) EDGe on PHA count mode */ |
| 5674 | #define TC_BMR_INVA (0x1u << 13) /**< \brief (TC_BMR) INVerted phA */ |
| 5675 | #define TC_BMR_INVB (0x1u << 14) /**< \brief (TC_BMR) INVerted phB */ |
| 5676 | #define TC_BMR_INVIDX (0x1u << 15) /**< \brief (TC_BMR) INVerted InDeX */ |
| 5677 | #define TC_BMR_SWAP (0x1u << 16) /**< \brief (TC_BMR) SWAP PHA and PHB */ |
| 5678 | #define TC_BMR_IDXPHB (0x1u << 17) /**< \brief (TC_BMR) InDeX pin is PHB pin */ |
| 5679 | #define TC_BMR_FILTER (0x1u << 19) /**< \brief (TC_BMR) */ |
| 5680 | #define TC_BMR_MAXFILT_Pos 20 |
| 5681 | #define TC_BMR_MAXFILT_Msk (0x3fu << TC_BMR_MAXFILT_Pos) /**< \brief (TC_BMR) MAXimum FILTer */ |
| 5682 | #define TC_BMR_MAXFILT(value) ((TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos))) |
| 5683 | /* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */ |
| 5684 | #define TC_QIER_IDX (0x1u << 0) /**< \brief (TC_QIER) InDeX */ |
| 5685 | #define TC_QIER_DIRCHG (0x1u << 1) /**< \brief (TC_QIER) DIRection CHanGe */ |
| 5686 | #define TC_QIER_QERR (0x1u << 2) /**< \brief (TC_QIER) Quadrature ERRor */ |
| 5687 | /* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */ |
| 5688 | #define TC_QIDR_IDX (0x1u << 0) /**< \brief (TC_QIDR) InDeX */ |
| 5689 | #define TC_QIDR_DIRCHG (0x1u << 1) /**< \brief (TC_QIDR) DIRection CHanGe */ |
| 5690 | #define TC_QIDR_QERR (0x1u << 2) /**< \brief (TC_QIDR) Quadrature ERRor */ |
| 5691 | /* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */ |
| 5692 | #define TC_QIMR_IDX (0x1u << 0) /**< \brief (TC_QIMR) InDeX */ |
| 5693 | #define TC_QIMR_DIRCHG (0x1u << 1) /**< \brief (TC_QIMR) DIRection CHanGe */ |
| 5694 | #define TC_QIMR_QERR (0x1u << 2) /**< \brief (TC_QIMR) Quadrature ERRor */ |
| 5695 | /* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */ |
| 5696 | #define TC_QISR_IDX (0x1u << 0) /**< \brief (TC_QISR) InDeX */ |
| 5697 | #define TC_QISR_DIRCHG (0x1u << 1) /**< \brief (TC_QISR) DIRection CHanGe */ |
| 5698 | #define TC_QISR_QERR (0x1u << 2) /**< \brief (TC_QISR) Quadrature ERRor */ |
| 5699 | #define TC_QISR_DIR (0x1u << 8) /**< \brief (TC_QISR) Direction */ |
| 5700 | /* -------- TC_FMR : (TC Offset: 0xD8) Fault Mode Register -------- */ |
| 5701 | #define TC_FMR_ENCF0 (0x1u << 0) /**< \brief (TC_FMR) ENable Compare Fault Channel 0 */ |
| 5702 | #define TC_FMR_ENCF1 (0x1u << 1) /**< \brief (TC_FMR) ENable Compare Fault Channel 1 */ |
| 5703 | /* -------- TC_WPMR : (TC Offset: 0xE4) Write Protect Mode Register -------- */ |
| 5704 | #define TC_WPMR_WPEN (0x1u << 0) /**< \brief (TC_WPMR) Write Protect Enable */ |
| 5705 | #define TC_WPMR_WPKEY_Pos 8 |
| 5706 | #define TC_WPMR_WPKEY_Msk (0xffffffu << TC_WPMR_WPKEY_Pos) /**< \brief (TC_WPMR) Write Protect KEY */ |
| 5707 | #define TC_WPMR_WPKEY(value) ((TC_WPMR_WPKEY_Msk & ((value) << TC_WPMR_WPKEY_Pos))) |
| 5708 | |
| 5709 | /*@}*/ |
| 5710 | |
| 5711 | /* ============================================================================= */ |
| 5712 | /** SOFTWARE API DEFINITION FOR Two-wire Interface */ |
| 5713 | /* ============================================================================= */ |
| 5714 | /** \addtogroup SAM3S_TWI Two-wire Interface */ |
| 5715 | /*@{*/ |
| 5716 | |
| 5717 | #ifndef __ASSEMBLY__ |
| 5718 | /** \brief Twi hardware registers */ |
| 5719 | typedef struct { |
| 5720 | WoReg TWI_CR; /**< \brief (Twi Offset: 0x00) Control Register */ |
| 5721 | RwReg TWI_MMR; /**< \brief (Twi Offset: 0x04) Master Mode Register */ |
| 5722 | RwReg TWI_SMR; /**< \brief (Twi Offset: 0x08) Slave Mode Register */ |
| 5723 | RwReg TWI_IADR; /**< \brief (Twi Offset: 0x0C) Internal Address Register */ |
| 5724 | RwReg TWI_CWGR; /**< \brief (Twi Offset: 0x10) Clock Waveform Generator Register */ |
| 5725 | RwReg Reserved1[3]; |
| 5726 | RoReg TWI_SR; /**< \brief (Twi Offset: 0x20) Status Register */ |
| 5727 | WoReg TWI_IER; /**< \brief (Twi Offset: 0x24) Interrupt Enable Register */ |
| 5728 | WoReg TWI_IDR; /**< \brief (Twi Offset: 0x28) Interrupt Disable Register */ |
| 5729 | RoReg TWI_IMR; /**< \brief (Twi Offset: 0x2C) Interrupt Mask Register */ |
| 5730 | RoReg TWI_RHR; /**< \brief (Twi Offset: 0x30) Receive Holding Register */ |
| 5731 | WoReg TWI_THR; /**< \brief (Twi Offset: 0x34) Transmit Holding Register */ |
| 5732 | RwReg Reserved2[50]; |
| 5733 | RwReg TWI_RPR; /**< \brief (Twi Offset: 0x100) Receive Pointer Register */ |
| 5734 | RwReg TWI_RCR; /**< \brief (Twi Offset: 0x104) Receive Counter Register */ |
| 5735 | RwReg TWI_TPR; /**< \brief (Twi Offset: 0x108) Transmit Pointer Register */ |
| 5736 | RwReg TWI_TCR; /**< \brief (Twi Offset: 0x10C) Transmit Counter Register */ |
| 5737 | RwReg TWI_RNPR; /**< \brief (Twi Offset: 0x110) Receive Next Pointer Register */ |
| 5738 | RwReg TWI_RNCR; /**< \brief (Twi Offset: 0x114) Receive Next Counter Register */ |
| 5739 | RwReg TWI_TNPR; /**< \brief (Twi Offset: 0x118) Transmit Next Pointer Register */ |
| 5740 | RwReg TWI_TNCR; /**< \brief (Twi Offset: 0x11C) Transmit Next Counter Register */ |
| 5741 | WoReg TWI_PTCR; /**< \brief (Twi Offset: 0x120) Transfer Control Register */ |
| 5742 | RoReg TWI_PTSR; /**< \brief (Twi Offset: 0x124) Transfer Status Register */ |
| 5743 | } Twi; |
| 5744 | #endif /* __ASSEMBLY__ */ |
| 5745 | /* -------- TWI_CR : (TWI Offset: 0x00) Control Register -------- */ |
| 5746 | #define TWI_CR_START (0x1u << 0) /**< \brief (TWI_CR) Send a START Condition */ |
| 5747 | #define TWI_CR_STOP (0x1u << 1) /**< \brief (TWI_CR) Send a STOP Condition */ |
| 5748 | #define TWI_CR_MSEN (0x1u << 2) /**< \brief (TWI_CR) TWI Master Mode Enabled */ |
| 5749 | #define TWI_CR_MSDIS (0x1u << 3) /**< \brief (TWI_CR) TWI Master Mode Disabled */ |
| 5750 | #define TWI_CR_SVEN (0x1u << 4) /**< \brief (TWI_CR) TWI Slave Mode Enabled */ |
| 5751 | #define TWI_CR_SVDIS (0x1u << 5) /**< \brief (TWI_CR) TWI Slave Mode Disabled */ |
| 5752 | #define TWI_CR_QUICK (0x1u << 6) /**< \brief (TWI_CR) SMBUS Quick Command */ |
| 5753 | #define TWI_CR_SWRST (0x1u << 7) /**< \brief (TWI_CR) Software Reset */ |
| 5754 | /* -------- TWI_MMR : (TWI Offset: 0x04) Master Mode Register -------- */ |
| 5755 | #define TWI_MMR_IADRSZ_Pos 8 |
| 5756 | #define TWI_MMR_IADRSZ_Msk (0x3u << TWI_MMR_IADRSZ_Pos) /**< \brief (TWI_MMR) Internal Device Address Size */ |
| 5757 | #define TWI_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWI_MMR) No internal device address */ |
| 5758 | #define TWI_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWI_MMR) One-byte internal device address */ |
| 5759 | #define TWI_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWI_MMR) Two-byte internal device address */ |
| 5760 | #define TWI_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWI_MMR) Three-byte internal device address */ |
| 5761 | #define TWI_MMR_MREAD (0x1u << 12) /**< \brief (TWI_MMR) Master Read Direction */ |
| 5762 | #define TWI_MMR_DADR_Pos 16 |
| 5763 | #define TWI_MMR_DADR_Msk (0x7fu << TWI_MMR_DADR_Pos) /**< \brief (TWI_MMR) Device Address */ |
| 5764 | #define TWI_MMR_DADR(value) ((TWI_MMR_DADR_Msk & ((value) << TWI_MMR_DADR_Pos))) |
| 5765 | /* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */ |
| 5766 | #define TWI_SMR_SADR_Pos 16 |
| 5767 | #define TWI_SMR_SADR_Msk (0x7fu << TWI_SMR_SADR_Pos) /**< \brief (TWI_SMR) Slave Address */ |
| 5768 | #define TWI_SMR_SADR(value) ((TWI_SMR_SADR_Msk & ((value) << TWI_SMR_SADR_Pos))) |
| 5769 | /* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */ |
| 5770 | #define TWI_IADR_IADR_Pos 0 |
| 5771 | #define TWI_IADR_IADR_Msk (0xffffffu << TWI_IADR_IADR_Pos) /**< \brief (TWI_IADR) Internal Address */ |
| 5772 | #define TWI_IADR_IADR(value) ((TWI_IADR_IADR_Msk & ((value) << TWI_IADR_IADR_Pos))) |
| 5773 | /* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */ |
| 5774 | #define TWI_CWGR_CLDIV_Pos 0 |
| 5775 | #define TWI_CWGR_CLDIV_Msk (0xffu << TWI_CWGR_CLDIV_Pos) /**< \brief (TWI_CWGR) Clock Low Divider */ |
| 5776 | #define TWI_CWGR_CLDIV(value) ((TWI_CWGR_CLDIV_Msk & ((value) << TWI_CWGR_CLDIV_Pos))) |
| 5777 | #define TWI_CWGR_CHDIV_Pos 8 |
| 5778 | #define TWI_CWGR_CHDIV_Msk (0xffu << TWI_CWGR_CHDIV_Pos) /**< \brief (TWI_CWGR) Clock High Divider */ |
| 5779 | #define TWI_CWGR_CHDIV(value) ((TWI_CWGR_CHDIV_Msk & ((value) << TWI_CWGR_CHDIV_Pos))) |
| 5780 | #define TWI_CWGR_CKDIV_Pos 16 |
| 5781 | #define TWI_CWGR_CKDIV_Msk (0x7u << TWI_CWGR_CKDIV_Pos) /**< \brief (TWI_CWGR) Clock Divider */ |
| 5782 | #define TWI_CWGR_CKDIV(value) ((TWI_CWGR_CKDIV_Msk & ((value) << TWI_CWGR_CKDIV_Pos))) |
| 5783 | /* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */ |
| 5784 | #define TWI_SR_TXCOMP (0x1u << 0) /**< \brief (TWI_SR) Transmission Completed (automatically set / reset) */ |
| 5785 | #define TWI_SR_RXRDY (0x1u << 1) /**< \brief (TWI_SR) Receive Holding Register Ready (automatically set / reset) */ |
| 5786 | #define TWI_SR_TXRDY (0x1u << 2) /**< \brief (TWI_SR) Transmit Holding Register Ready (automatically set / reset) */ |
| 5787 | #define TWI_SR_SVREAD (0x1u << 3) /**< \brief (TWI_SR) Slave Read (automatically set / reset) */ |
| 5788 | #define TWI_SR_SVACC (0x1u << 4) /**< \brief (TWI_SR) Slave Access (automatically set / reset) */ |
| 5789 | #define TWI_SR_GACC (0x1u << 5) /**< \brief (TWI_SR) General Call Access (clear on read) */ |
| 5790 | #define TWI_SR_OVRE (0x1u << 6) /**< \brief (TWI_SR) Overrun Error (clear on read) */ |
| 5791 | #define TWI_SR_NACK (0x1u << 8) /**< \brief (TWI_SR) Not Acknowledged (clear on read) */ |
| 5792 | #define TWI_SR_ARBLST (0x1u << 9) /**< \brief (TWI_SR) Arbitration Lost (clear on read) */ |
| 5793 | #define TWI_SR_SCLWS (0x1u << 10) /**< \brief (TWI_SR) Clock Wait State (automatically set / reset) */ |
| 5794 | #define TWI_SR_EOSACC (0x1u << 11) /**< \brief (TWI_SR) End Of Slave Access (clear on read) */ |
| 5795 | #define TWI_SR_ENDRX (0x1u << 12) /**< \brief (TWI_SR) End of RX buffer */ |
| 5796 | #define TWI_SR_ENDTX (0x1u << 13) /**< \brief (TWI_SR) End of TX buffer */ |
| 5797 | #define TWI_SR_RXBUFF (0x1u << 14) /**< \brief (TWI_SR) RX Buffer Full */ |
| 5798 | #define TWI_SR_TXBUFE (0x1u << 15) /**< \brief (TWI_SR) TX Buffer Empty */ |
| 5799 | /* -------- TWI_IER : (TWI Offset: 0x24) Interrupt Enable Register -------- */ |
| 5800 | #define TWI_IER_TXCOMP (0x1u << 0) /**< \brief (TWI_IER) Transmission Completed Interrupt Enable */ |
| 5801 | #define TWI_IER_RXRDY (0x1u << 1) /**< \brief (TWI_IER) Receive Holding Register Ready Interrupt Enable */ |
| 5802 | #define TWI_IER_TXRDY (0x1u << 2) /**< \brief (TWI_IER) Transmit Holding Register Ready Interrupt Enable */ |
| 5803 | #define TWI_IER_SVACC (0x1u << 4) /**< \brief (TWI_IER) Slave Access Interrupt Enable */ |
| 5804 | #define TWI_IER_GACC (0x1u << 5) /**< \brief (TWI_IER) General Call Access Interrupt Enable */ |
| 5805 | #define TWI_IER_OVRE (0x1u << 6) /**< \brief (TWI_IER) Overrun Error Interrupt Enable */ |
| 5806 | #define TWI_IER_NACK (0x1u << 8) /**< \brief (TWI_IER) Not Acknowledge Interrupt Enable */ |
| 5807 | #define TWI_IER_ARBLST (0x1u << 9) /**< \brief (TWI_IER) Arbitration Lost Interrupt Enable */ |
| 5808 | #define TWI_IER_SCL_WS (0x1u << 10) /**< \brief (TWI_IER) Clock Wait State Interrupt Enable */ |
| 5809 | #define TWI_IER_EOSACC (0x1u << 11) /**< \brief (TWI_IER) End Of Slave Access Interrupt Enable */ |
| 5810 | #define TWI_IER_ENDRX (0x1u << 12) /**< \brief (TWI_IER) End of Receive Buffer Interrupt Enable */ |
| 5811 | #define TWI_IER_ENDTX (0x1u << 13) /**< \brief (TWI_IER) End of Transmit Buffer Interrupt Enable */ |
| 5812 | #define TWI_IER_RXBUFF (0x1u << 14) /**< \brief (TWI_IER) Receive Buffer Full Interrupt Enable */ |
| 5813 | #define TWI_IER_TXBUFE (0x1u << 15) /**< \brief (TWI_IER) Transmit Buffer Empty Interrupt Enable */ |
| 5814 | /* -------- TWI_IDR : (TWI Offset: 0x28) Interrupt Disable Register -------- */ |
| 5815 | #define TWI_IDR_TXCOMP (0x1u << 0) /**< \brief (TWI_IDR) Transmission Completed Interrupt Disable */ |
| 5816 | #define TWI_IDR_RXRDY (0x1u << 1) /**< \brief (TWI_IDR) Receive Holding Register Ready Interrupt Disable */ |
| 5817 | #define TWI_IDR_TXRDY (0x1u << 2) /**< \brief (TWI_IDR) Transmit Holding Register Ready Interrupt Disable */ |
| 5818 | #define TWI_IDR_SVACC (0x1u << 4) /**< \brief (TWI_IDR) Slave Access Interrupt Disable */ |
| 5819 | #define TWI_IDR_GACC (0x1u << 5) /**< \brief (TWI_IDR) General Call Access Interrupt Disable */ |
| 5820 | #define TWI_IDR_OVRE (0x1u << 6) /**< \brief (TWI_IDR) Overrun Error Interrupt Disable */ |
| 5821 | #define TWI_IDR_NACK (0x1u << 8) /**< \brief (TWI_IDR) Not Acknowledge Interrupt Disable */ |
| 5822 | #define TWI_IDR_ARBLST (0x1u << 9) /**< \brief (TWI_IDR) Arbitration Lost Interrupt Disable */ |
| 5823 | #define TWI_IDR_SCL_WS (0x1u << 10) /**< \brief (TWI_IDR) Clock Wait State Interrupt Disable */ |
| 5824 | #define TWI_IDR_EOSACC (0x1u << 11) /**< \brief (TWI_IDR) End Of Slave Access Interrupt Disable */ |
| 5825 | #define TWI_IDR_ENDRX (0x1u << 12) /**< \brief (TWI_IDR) End of Receive Buffer Interrupt Disable */ |
| 5826 | #define TWI_IDR_ENDTX (0x1u << 13) /**< \brief (TWI_IDR) End of Transmit Buffer Interrupt Disable */ |
| 5827 | #define TWI_IDR_RXBUFF (0x1u << 14) /**< \brief (TWI_IDR) Receive Buffer Full Interrupt Disable */ |
| 5828 | #define TWI_IDR_TXBUFE (0x1u << 15) /**< \brief (TWI_IDR) Transmit Buffer Empty Interrupt Disable */ |
| 5829 | /* -------- TWI_IMR : (TWI Offset: 0x2C) Interrupt Mask Register -------- */ |
| 5830 | #define TWI_IMR_TXCOMP (0x1u << 0) /**< \brief (TWI_IMR) Transmission Completed Interrupt Mask */ |
| 5831 | #define TWI_IMR_RXRDY (0x1u << 1) /**< \brief (TWI_IMR) Receive Holding Register Ready Interrupt Mask */ |
| 5832 | #define TWI_IMR_TXRDY (0x1u << 2) /**< \brief (TWI_IMR) Transmit Holding Register Ready Interrupt Mask */ |
| 5833 | #define TWI_IMR_SVACC (0x1u << 4) /**< \brief (TWI_IMR) Slave Access Interrupt Mask */ |
| 5834 | #define TWI_IMR_GACC (0x1u << 5) /**< \brief (TWI_IMR) General Call Access Interrupt Mask */ |
| 5835 | #define TWI_IMR_OVRE (0x1u << 6) /**< \brief (TWI_IMR) Overrun Error Interrupt Mask */ |
| 5836 | #define TWI_IMR_NACK (0x1u << 8) /**< \brief (TWI_IMR) Not Acknowledge Interrupt Mask */ |
| 5837 | #define TWI_IMR_ARBLST (0x1u << 9) /**< \brief (TWI_IMR) Arbitration Lost Interrupt Mask */ |
| 5838 | #define TWI_IMR_SCL_WS (0x1u << 10) /**< \brief (TWI_IMR) Clock Wait State Interrupt Mask */ |
| 5839 | #define TWI_IMR_EOSACC (0x1u << 11) /**< \brief (TWI_IMR) End Of Slave Access Interrupt Mask */ |
| 5840 | #define TWI_IMR_ENDRX (0x1u << 12) /**< \brief (TWI_IMR) End of Receive Buffer Interrupt Mask */ |
| 5841 | #define TWI_IMR_ENDTX (0x1u << 13) /**< \brief (TWI_IMR) End of Transmit Buffer Interrupt Mask */ |
| 5842 | #define TWI_IMR_RXBUFF (0x1u << 14) /**< \brief (TWI_IMR) Receive Buffer Full Interrupt Mask */ |
| 5843 | #define TWI_IMR_TXBUFE (0x1u << 15) /**< \brief (TWI_IMR) Transmit Buffer Empty Interrupt Mask */ |
| 5844 | /* -------- TWI_RHR : (TWI Offset: 0x30) Receive Holding Register -------- */ |
| 5845 | #define TWI_RHR_RXDATA_Pos 0 |
| 5846 | #define TWI_RHR_RXDATA_Msk (0xffu << TWI_RHR_RXDATA_Pos) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data */ |
| 5847 | /* -------- TWI_THR : (TWI Offset: 0x34) Transmit Holding Register -------- */ |
| 5848 | #define TWI_THR_TXDATA_Pos 0 |
| 5849 | #define TWI_THR_TXDATA_Msk (0xffu << TWI_THR_TXDATA_Pos) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data */ |
| 5850 | #define TWI_THR_TXDATA(value) ((TWI_THR_TXDATA_Msk & ((value) << TWI_THR_TXDATA_Pos))) |
| 5851 | /* -------- TWI_RPR : (TWI Offset: 0x100) Receive Pointer Register -------- */ |
| 5852 | #define TWI_RPR_RXPTR_Pos 0 |
| 5853 | #define TWI_RPR_RXPTR_Msk (0xffffffffu << TWI_RPR_RXPTR_Pos) /**< \brief (TWI_RPR) Receive Pointer Register */ |
| 5854 | #define TWI_RPR_RXPTR(value) ((TWI_RPR_RXPTR_Msk & ((value) << TWI_RPR_RXPTR_Pos))) |
| 5855 | /* -------- TWI_RCR : (TWI Offset: 0x104) Receive Counter Register -------- */ |
| 5856 | #define TWI_RCR_RXCTR_Pos 0 |
| 5857 | #define TWI_RCR_RXCTR_Msk (0xffffu << TWI_RCR_RXCTR_Pos) /**< \brief (TWI_RCR) Receive Counter Register */ |
| 5858 | #define TWI_RCR_RXCTR(value) ((TWI_RCR_RXCTR_Msk & ((value) << TWI_RCR_RXCTR_Pos))) |
| 5859 | /* -------- TWI_TPR : (TWI Offset: 0x108) Transmit Pointer Register -------- */ |
| 5860 | #define TWI_TPR_TXPTR_Pos 0 |
| 5861 | #define TWI_TPR_TXPTR_Msk (0xffffffffu << TWI_TPR_TXPTR_Pos) /**< \brief (TWI_TPR) Transmit Counter Register */ |
| 5862 | #define TWI_TPR_TXPTR(value) ((TWI_TPR_TXPTR_Msk & ((value) << TWI_TPR_TXPTR_Pos))) |
| 5863 | /* -------- TWI_TCR : (TWI Offset: 0x10C) Transmit Counter Register -------- */ |
| 5864 | #define TWI_TCR_TXCTR_Pos 0 |
| 5865 | #define TWI_TCR_TXCTR_Msk (0xffffu << TWI_TCR_TXCTR_Pos) /**< \brief (TWI_TCR) Transmit Counter Register */ |
| 5866 | #define TWI_TCR_TXCTR(value) ((TWI_TCR_TXCTR_Msk & ((value) << TWI_TCR_TXCTR_Pos))) |
| 5867 | /* -------- TWI_RNPR : (TWI Offset: 0x110) Receive Next Pointer Register -------- */ |
| 5868 | #define TWI_RNPR_RXNPTR_Pos 0 |
| 5869 | #define TWI_RNPR_RXNPTR_Msk (0xffffffffu << TWI_RNPR_RXNPTR_Pos) /**< \brief (TWI_RNPR) Receive Next Pointer */ |
| 5870 | #define TWI_RNPR_RXNPTR(value) ((TWI_RNPR_RXNPTR_Msk & ((value) << TWI_RNPR_RXNPTR_Pos))) |
| 5871 | /* -------- TWI_RNCR : (TWI Offset: 0x114) Receive Next Counter Register -------- */ |
| 5872 | #define TWI_RNCR_RXNCTR_Pos 0 |
| 5873 | #define TWI_RNCR_RXNCTR_Msk (0xffffu << TWI_RNCR_RXNCTR_Pos) /**< \brief (TWI_RNCR) Receive Next Counter */ |
| 5874 | #define TWI_RNCR_RXNCTR(value) ((TWI_RNCR_RXNCTR_Msk & ((value) << TWI_RNCR_RXNCTR_Pos))) |
| 5875 | /* -------- TWI_TNPR : (TWI Offset: 0x118) Transmit Next Pointer Register -------- */ |
| 5876 | #define TWI_TNPR_TXNPTR_Pos 0 |
| 5877 | #define TWI_TNPR_TXNPTR_Msk (0xffffffffu << TWI_TNPR_TXNPTR_Pos) /**< \brief (TWI_TNPR) Transmit Next Pointer */ |
| 5878 | #define TWI_TNPR_TXNPTR(value) ((TWI_TNPR_TXNPTR_Msk & ((value) << TWI_TNPR_TXNPTR_Pos))) |
| 5879 | /* -------- TWI_TNCR : (TWI Offset: 0x11C) Transmit Next Counter Register -------- */ |
| 5880 | #define TWI_TNCR_TXNCTR_Pos 0 |
| 5881 | #define TWI_TNCR_TXNCTR_Msk (0xffffu << TWI_TNCR_TXNCTR_Pos) /**< \brief (TWI_TNCR) Transmit Counter Next */ |
| 5882 | #define TWI_TNCR_TXNCTR(value) ((TWI_TNCR_TXNCTR_Msk & ((value) << TWI_TNCR_TXNCTR_Pos))) |
| 5883 | /* -------- TWI_PTCR : (TWI Offset: 0x120) Transfer Control Register -------- */ |
| 5884 | #define TWI_PTCR_RXTEN (0x1u << 0) /**< \brief (TWI_PTCR) Receiver Transfer Enable */ |
| 5885 | #define TWI_PTCR_RXTDIS (0x1u << 1) /**< \brief (TWI_PTCR) Receiver Transfer Disable */ |
| 5886 | #define TWI_PTCR_TXTEN (0x1u << 8) /**< \brief (TWI_PTCR) Transmitter Transfer Enable */ |
| 5887 | #define TWI_PTCR_TXTDIS (0x1u << 9) /**< \brief (TWI_PTCR) Transmitter Transfer Disable */ |
| 5888 | /* -------- TWI_PTSR : (TWI Offset: 0x124) Transfer Status Register -------- */ |
| 5889 | #define TWI_PTSR_RXTEN (0x1u << 0) /**< \brief (TWI_PTSR) Receiver Transfer Enable */ |
| 5890 | #define TWI_PTSR_TXTEN (0x1u << 8) /**< \brief (TWI_PTSR) Transmitter Transfer Enable */ |
| 5891 | |
| 5892 | /*@}*/ |
| 5893 | |
| 5894 | /* ============================================================================= */ |
| 5895 | /** SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */ |
| 5896 | /* ============================================================================= */ |
| 5897 | /** \addtogroup SAM3S_UART Universal Asynchronous Receiver Transmitter */ |
| 5898 | /*@{*/ |
| 5899 | |
| 5900 | #ifndef __ASSEMBLY__ |
| 5901 | /** \brief Uart hardware registers */ |
| 5902 | typedef struct { |
| 5903 | WoReg UART_CR; /**< \brief (Uart Offset: 0x0000) Control Register */ |
| 5904 | RwReg UART_MR; /**< \brief (Uart Offset: 0x0004) Mode Register */ |
| 5905 | WoReg UART_IER; /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */ |
| 5906 | WoReg UART_IDR; /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */ |
| 5907 | RoReg UART_IMR; /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */ |
| 5908 | RoReg UART_SR; /**< \brief (Uart Offset: 0x0014) Status Register */ |
| 5909 | RoReg UART_RHR; /**< \brief (Uart Offset: 0x0018) Receive Holding Register */ |
| 5910 | WoReg UART_THR; /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */ |
| 5911 | RwReg UART_BRGR; /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */ |
| 5912 | RwReg Reserved1[55]; |
| 5913 | RwReg UART_RPR; /**< \brief (Uart Offset: 0x100) Receive Pointer Register */ |
| 5914 | RwReg UART_RCR; /**< \brief (Uart Offset: 0x104) Receive Counter Register */ |
| 5915 | RwReg UART_TPR; /**< \brief (Uart Offset: 0x108) Transmit Pointer Register */ |
| 5916 | RwReg UART_TCR; /**< \brief (Uart Offset: 0x10C) Transmit Counter Register */ |
| 5917 | RwReg UART_RNPR; /**< \brief (Uart Offset: 0x110) Receive Next Pointer Register */ |
| 5918 | RwReg UART_RNCR; /**< \brief (Uart Offset: 0x114) Receive Next Counter Register */ |
| 5919 | RwReg UART_TNPR; /**< \brief (Uart Offset: 0x118) Transmit Next Pointer Register */ |
| 5920 | RwReg UART_TNCR; /**< \brief (Uart Offset: 0x11C) Transmit Next Counter Register */ |
| 5921 | WoReg UART_PTCR; /**< \brief (Uart Offset: 0x120) Transfer Control Register */ |
| 5922 | RoReg UART_PTSR; /**< \brief (Uart Offset: 0x124) Transfer Status Register */ |
| 5923 | } Uart; |
| 5924 | #endif /* __ASSEMBLY__ */ |
| 5925 | /* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */ |
| 5926 | #define UART_CR_RSTRX (0x1u << 2) /**< \brief (UART_CR) Reset Receiver */ |
| 5927 | #define UART_CR_RSTTX (0x1u << 3) /**< \brief (UART_CR) Reset Transmitter */ |
| 5928 | #define UART_CR_RXEN (0x1u << 4) /**< \brief (UART_CR) Receiver Enable */ |
| 5929 | #define UART_CR_RXDIS (0x1u << 5) /**< \brief (UART_CR) Receiver Disable */ |
| 5930 | #define UART_CR_TXEN (0x1u << 6) /**< \brief (UART_CR) Transmitter Enable */ |
| 5931 | #define UART_CR_TXDIS (0x1u << 7) /**< \brief (UART_CR) Transmitter Disable */ |
| 5932 | #define UART_CR_RSTSTA (0x1u << 8) /**< \brief (UART_CR) Reset Status Bits */ |
| 5933 | /* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */ |
| 5934 | #define UART_MR_PAR_Pos 9 |
| 5935 | #define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos) /**< \brief (UART_MR) Parity Type */ |
| 5936 | #define UART_MR_PAR_EVEN (0x0u << 9) /**< \brief (UART_MR) Even parity */ |
| 5937 | #define UART_MR_PAR_ODD (0x1u << 9) /**< \brief (UART_MR) Odd parity */ |
| 5938 | #define UART_MR_PAR_SPACE (0x2u << 9) /**< \brief (UART_MR) Space: parity forced to 0 */ |
| 5939 | #define UART_MR_PAR_MARK (0x3u << 9) /**< \brief (UART_MR) Mark: parity forced to 1 */ |
| 5940 | #define UART_MR_PAR_NO (0x4u << 9) /**< \brief (UART_MR) No parity */ |
| 5941 | #define UART_MR_CHMODE_Pos 14 |
| 5942 | #define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos) /**< \brief (UART_MR) Channel Mode */ |
| 5943 | #define UART_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (UART_MR) Normal Mode */ |
| 5944 | #define UART_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (UART_MR) Automatic Echo */ |
| 5945 | #define UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (UART_MR) Local Loopback */ |
| 5946 | #define UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (UART_MR) Remote Loopback */ |
| 5947 | /* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */ |
| 5948 | #define UART_IER_RXRDY (0x1u << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */ |
| 5949 | #define UART_IER_TXRDY (0x1u << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */ |
| 5950 | #define UART_IER_ENDRX (0x1u << 3) /**< \brief (UART_IER) Enable End of Receive Transfer Interrupt */ |
| 5951 | #define UART_IER_ENDTX (0x1u << 4) /**< \brief (UART_IER) Enable End of Transmit Interrupt */ |
| 5952 | #define UART_IER_OVRE (0x1u << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */ |
| 5953 | #define UART_IER_FRAME (0x1u << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */ |
| 5954 | #define UART_IER_PARE (0x1u << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */ |
| 5955 | #define UART_IER_TXEMPTY (0x1u << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */ |
| 5956 | #define UART_IER_TXBUFE (0x1u << 11) /**< \brief (UART_IER) Enable Buffer Empty Interrupt */ |
| 5957 | #define UART_IER_RXBUFF (0x1u << 12) /**< \brief (UART_IER) Enable Buffer Full Interrupt */ |
| 5958 | /* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */ |
| 5959 | #define UART_IDR_RXRDY (0x1u << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */ |
| 5960 | #define UART_IDR_TXRDY (0x1u << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */ |
| 5961 | #define UART_IDR_ENDRX (0x1u << 3) /**< \brief (UART_IDR) Disable End of Receive Transfer Interrupt */ |
| 5962 | #define UART_IDR_ENDTX (0x1u << 4) /**< \brief (UART_IDR) Disable End of Transmit Interrupt */ |
| 5963 | #define UART_IDR_OVRE (0x1u << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */ |
| 5964 | #define UART_IDR_FRAME (0x1u << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */ |
| 5965 | #define UART_IDR_PARE (0x1u << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */ |
| 5966 | #define UART_IDR_TXEMPTY (0x1u << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */ |
| 5967 | #define UART_IDR_TXBUFE (0x1u << 11) /**< \brief (UART_IDR) Disable Buffer Empty Interrupt */ |
| 5968 | #define UART_IDR_RXBUFF (0x1u << 12) /**< \brief (UART_IDR) Disable Buffer Full Interrupt */ |
| 5969 | /* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */ |
| 5970 | #define UART_IMR_RXRDY (0x1u << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */ |
| 5971 | #define UART_IMR_TXRDY (0x1u << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */ |
| 5972 | #define UART_IMR_ENDRX (0x1u << 3) /**< \brief (UART_IMR) Mask End of Receive Transfer Interrupt */ |
| 5973 | #define UART_IMR_ENDTX (0x1u << 4) /**< \brief (UART_IMR) Mask End of Transmit Interrupt */ |
| 5974 | #define UART_IMR_OVRE (0x1u << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */ |
| 5975 | #define UART_IMR_FRAME (0x1u << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */ |
| 5976 | #define UART_IMR_PARE (0x1u << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */ |
| 5977 | #define UART_IMR_TXEMPTY (0x1u << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */ |
| 5978 | #define UART_IMR_TXBUFE (0x1u << 11) /**< \brief (UART_IMR) Mask TXBUFE Interrupt */ |
| 5979 | #define UART_IMR_RXBUFF (0x1u << 12) /**< \brief (UART_IMR) Mask RXBUFF Interrupt */ |
| 5980 | /* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */ |
| 5981 | #define UART_SR_RXRDY (0x1u << 0) /**< \brief (UART_SR) Receiver Ready */ |
| 5982 | #define UART_SR_TXRDY (0x1u << 1) /**< \brief (UART_SR) Transmitter Ready */ |
| 5983 | #define UART_SR_ENDRX (0x1u << 3) /**< \brief (UART_SR) End of Receiver Transfer */ |
| 5984 | #define UART_SR_ENDTX (0x1u << 4) /**< \brief (UART_SR) End of Transmitter Transfer */ |
| 5985 | #define UART_SR_OVRE (0x1u << 5) /**< \brief (UART_SR) Overrun Error */ |
| 5986 | #define UART_SR_FRAME (0x1u << 6) /**< \brief (UART_SR) Framing Error */ |
| 5987 | #define UART_SR_PARE (0x1u << 7) /**< \brief (UART_SR) Parity Error */ |
| 5988 | #define UART_SR_TXEMPTY (0x1u << 9) /**< \brief (UART_SR) Transmitter Empty */ |
| 5989 | #define UART_SR_TXBUFE (0x1u << 11) /**< \brief (UART_SR) Transmission Buffer Empty */ |
| 5990 | #define UART_SR_RXBUFF (0x1u << 12) /**< \brief (UART_SR) Receive Buffer Full */ |
| 5991 | /* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */ |
| 5992 | #define UART_RHR_RXCHR_Pos 0 |
| 5993 | #define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos) /**< \brief (UART_RHR) Received Character */ |
| 5994 | /* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */ |
| 5995 | #define UART_THR_TXCHR_Pos 0 |
| 5996 | #define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos) /**< \brief (UART_THR) Character to be Transmitted */ |
| 5997 | #define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos))) |
| 5998 | /* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */ |
| 5999 | #define UART_BRGR_CD_Pos 0 |
| 6000 | #define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos) /**< \brief (UART_BRGR) Clock Divisor */ |
| 6001 | #define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos))) |
| 6002 | /* -------- UART_RPR : (UART Offset: 0x100) Receive Pointer Register -------- */ |
| 6003 | #define UART_RPR_RXPTR_Pos 0 |
| 6004 | #define UART_RPR_RXPTR_Msk (0xffffffffu << UART_RPR_RXPTR_Pos) /**< \brief (UART_RPR) Receive Pointer Register */ |
| 6005 | #define UART_RPR_RXPTR(value) ((UART_RPR_RXPTR_Msk & ((value) << UART_RPR_RXPTR_Pos))) |
| 6006 | /* -------- UART_RCR : (UART Offset: 0x104) Receive Counter Register -------- */ |
| 6007 | #define UART_RCR_RXCTR_Pos 0 |
| 6008 | #define UART_RCR_RXCTR_Msk (0xffffu << UART_RCR_RXCTR_Pos) /**< \brief (UART_RCR) Receive Counter Register */ |
| 6009 | #define UART_RCR_RXCTR(value) ((UART_RCR_RXCTR_Msk & ((value) << UART_RCR_RXCTR_Pos))) |
| 6010 | /* -------- UART_TPR : (UART Offset: 0x108) Transmit Pointer Register -------- */ |
| 6011 | #define UART_TPR_TXPTR_Pos 0 |
| 6012 | #define UART_TPR_TXPTR_Msk (0xffffffffu << UART_TPR_TXPTR_Pos) /**< \brief (UART_TPR) Transmit Counter Register */ |
| 6013 | #define UART_TPR_TXPTR(value) ((UART_TPR_TXPTR_Msk & ((value) << UART_TPR_TXPTR_Pos))) |
| 6014 | /* -------- UART_TCR : (UART Offset: 0x10C) Transmit Counter Register -------- */ |
| 6015 | #define UART_TCR_TXCTR_Pos 0 |
| 6016 | #define UART_TCR_TXCTR_Msk (0xffffu << UART_TCR_TXCTR_Pos) /**< \brief (UART_TCR) Transmit Counter Register */ |
| 6017 | #define UART_TCR_TXCTR(value) ((UART_TCR_TXCTR_Msk & ((value) << UART_TCR_TXCTR_Pos))) |
| 6018 | /* -------- UART_RNPR : (UART Offset: 0x110) Receive Next Pointer Register -------- */ |
| 6019 | #define UART_RNPR_RXNPTR_Pos 0 |
| 6020 | #define UART_RNPR_RXNPTR_Msk (0xffffffffu << UART_RNPR_RXNPTR_Pos) /**< \brief (UART_RNPR) Receive Next Pointer */ |
| 6021 | #define UART_RNPR_RXNPTR(value) ((UART_RNPR_RXNPTR_Msk & ((value) << UART_RNPR_RXNPTR_Pos))) |
| 6022 | /* -------- UART_RNCR : (UART Offset: 0x114) Receive Next Counter Register -------- */ |
| 6023 | #define UART_RNCR_RXNCTR_Pos 0 |
| 6024 | #define UART_RNCR_RXNCTR_Msk (0xffffu << UART_RNCR_RXNCTR_Pos) /**< \brief (UART_RNCR) Receive Next Counter */ |
| 6025 | #define UART_RNCR_RXNCTR(value) ((UART_RNCR_RXNCTR_Msk & ((value) << UART_RNCR_RXNCTR_Pos))) |
| 6026 | /* -------- UART_TNPR : (UART Offset: 0x118) Transmit Next Pointer Register -------- */ |
| 6027 | #define UART_TNPR_TXNPTR_Pos 0 |
| 6028 | #define UART_TNPR_TXNPTR_Msk (0xffffffffu << UART_TNPR_TXNPTR_Pos) /**< \brief (UART_TNPR) Transmit Next Pointer */ |
| 6029 | #define UART_TNPR_TXNPTR(value) ((UART_TNPR_TXNPTR_Msk & ((value) << UART_TNPR_TXNPTR_Pos))) |
| 6030 | /* -------- UART_TNCR : (UART Offset: 0x11C) Transmit Next Counter Register -------- */ |
| 6031 | #define UART_TNCR_TXNCTR_Pos 0 |
| 6032 | #define UART_TNCR_TXNCTR_Msk (0xffffu << UART_TNCR_TXNCTR_Pos) /**< \brief (UART_TNCR) Transmit Counter Next */ |
| 6033 | #define UART_TNCR_TXNCTR(value) ((UART_TNCR_TXNCTR_Msk & ((value) << UART_TNCR_TXNCTR_Pos))) |
| 6034 | /* -------- UART_PTCR : (UART Offset: 0x120) Transfer Control Register -------- */ |
| 6035 | #define UART_PTCR_RXTEN (0x1u << 0) /**< \brief (UART_PTCR) Receiver Transfer Enable */ |
| 6036 | #define UART_PTCR_RXTDIS (0x1u << 1) /**< \brief (UART_PTCR) Receiver Transfer Disable */ |
| 6037 | #define UART_PTCR_TXTEN (0x1u << 8) /**< \brief (UART_PTCR) Transmitter Transfer Enable */ |
| 6038 | #define UART_PTCR_TXTDIS (0x1u << 9) /**< \brief (UART_PTCR) Transmitter Transfer Disable */ |
| 6039 | /* -------- UART_PTSR : (UART Offset: 0x124) Transfer Status Register -------- */ |
| 6040 | #define UART_PTSR_RXTEN (0x1u << 0) /**< \brief (UART_PTSR) Receiver Transfer Enable */ |
| 6041 | #define UART_PTSR_TXTEN (0x1u << 8) /**< \brief (UART_PTSR) Transmitter Transfer Enable */ |
| 6042 | |
| 6043 | /*@}*/ |
| 6044 | |
| 6045 | /* ============================================================================= */ |
| 6046 | /** SOFTWARE API DEFINITION FOR USB Device Port */ |
| 6047 | /* ============================================================================= */ |
| 6048 | /** \addtogroup SAM3S_UDP USB Device Port */ |
| 6049 | /*@{*/ |
| 6050 | |
| 6051 | #ifndef __ASSEMBLY__ |
| 6052 | /** \brief Udp hardware registers */ |
| 6053 | typedef struct { |
| 6054 | RoReg UDP_FRM_NUM; /**< \brief (Udp Offset: 0x000) Frame Number Register */ |
| 6055 | RwReg UDP_GLB_STAT; /**< \brief (Udp Offset: 0x004) Global State Register */ |
| 6056 | RwReg UDP_FADDR; /**< \brief (Udp Offset: 0x008) Function Address Register */ |
| 6057 | RwReg Reserved1[1]; |
| 6058 | WoReg UDP_IER; /**< \brief (Udp Offset: 0x010) Interrupt Enable Register */ |
| 6059 | WoReg UDP_IDR; /**< \brief (Udp Offset: 0x014) Interrupt Disable Register */ |
| 6060 | RoReg UDP_IMR; /**< \brief (Udp Offset: 0x018) Interrupt Mask Register */ |
| 6061 | RoReg UDP_ISR; /**< \brief (Udp Offset: 0x01C) Interrupt Status Register */ |
| 6062 | WoReg UDP_ICR; /**< \brief (Udp Offset: 0x020) Interrupt Clear Register */ |
| 6063 | RwReg Reserved2[1]; |
| 6064 | RwReg UDP_RST_EP; /**< \brief (Udp Offset: 0x028) Reset Endpoint Register */ |
| 6065 | RwReg Reserved3[1]; |
| 6066 | RwReg UDP_CSR[8]; /**< \brief (Udp Offset: 0x030) Endpoint Control and Status Register */ |
| 6067 | RwReg UDP_FDR[8]; /**< \brief (Udp Offset: 0x050) Endpoint FIFO Data Register */ |
| 6068 | RwReg Reserved4[1]; |
| 6069 | RwReg UDP_TXVC; /**< \brief (Udp Offset: 0x074) Transceiver Control Register */ |
| 6070 | } Udp; |
| 6071 | #endif /* __ASSEMBLY__ */ |
| 6072 | /* -------- UDP_FRM_NUM : (UDP Offset: 0x000) Frame Number Register -------- */ |
| 6073 | #define UDP_FRM_NUM_FRM_NUM_Pos 0 |
| 6074 | #define UDP_FRM_NUM_FRM_NUM_Msk (0x7ffu << UDP_FRM_NUM_FRM_NUM_Pos) /**< \brief (UDP_FRM_NUM) Frame Number as Defined in the Packet Field Formats */ |
| 6075 | #define UDP_FRM_NUM_FRM_ERR (0x1u << 16) /**< \brief (UDP_FRM_NUM) Frame Error */ |
| 6076 | #define UDP_FRM_NUM_FRM_OK (0x1u << 17) /**< \brief (UDP_FRM_NUM) Frame OK */ |
| 6077 | /* -------- UDP_GLB_STAT : (UDP Offset: 0x004) Global State Register -------- */ |
| 6078 | #define UDP_GLB_STAT_FADDEN (0x1u << 0) /**< \brief (UDP_GLB_STAT) Function Address Enable */ |
| 6079 | #define UDP_GLB_STAT_CONFG (0x1u << 1) /**< \brief (UDP_GLB_STAT) Configured */ |
| 6080 | #define UDP_GLB_STAT_ESR (0x1u << 2) /**< \brief (UDP_GLB_STAT) Enable Send Resume */ |
| 6081 | #define UDP_GLB_STAT_RSMINPR (0x1u << 3) /**< \brief (UDP_GLB_STAT) */ |
| 6082 | #define UDP_GLB_STAT_RMWUPE (0x1u << 4) /**< \brief (UDP_GLB_STAT) Remote Wake Up Enable */ |
| 6083 | /* -------- UDP_FADDR : (UDP Offset: 0x008) Function Address Register -------- */ |
| 6084 | #define UDP_FADDR_FADD_Pos 0 |
| 6085 | #define UDP_FADDR_FADD_Msk (0x7fu << UDP_FADDR_FADD_Pos) /**< \brief (UDP_FADDR) Function Address Value */ |
| 6086 | #define UDP_FADDR_FADD(value) ((UDP_FADDR_FADD_Msk & ((value) << UDP_FADDR_FADD_Pos))) |
| 6087 | #define UDP_FADDR_FEN (0x1u << 8) /**< \brief (UDP_FADDR) Function Enable */ |
| 6088 | /* -------- UDP_IER : (UDP Offset: 0x010) Interrupt Enable Register -------- */ |
| 6089 | #define UDP_IER_EP0INT (0x1u << 0) /**< \brief (UDP_IER) Enable Endpoint 0 Interrupt */ |
| 6090 | #define UDP_IER_EP1INT (0x1u << 1) /**< \brief (UDP_IER) Enable Endpoint 1 Interrupt */ |
| 6091 | #define UDP_IER_EP2INT (0x1u << 2) /**< \brief (UDP_IER) Enable Endpoint 2Interrupt */ |
| 6092 | #define UDP_IER_EP3INT (0x1u << 3) /**< \brief (UDP_IER) Enable Endpoint 3 Interrupt */ |
| 6093 | #define UDP_IER_EP4INT (0x1u << 4) /**< \brief (UDP_IER) Enable Endpoint 4 Interrupt */ |
| 6094 | #define UDP_IER_EP5INT (0x1u << 5) /**< \brief (UDP_IER) Enable Endpoint 5 Interrupt */ |
| 6095 | #define UDP_IER_EP6INT (0x1u << 6) /**< \brief (UDP_IER) Enable Endpoint 6 Interrupt */ |
| 6096 | #define UDP_IER_EP7INT (0x1u << 7) /**< \brief (UDP_IER) Enable Endpoint 7 Interrupt */ |
| 6097 | #define UDP_IER_RXSUSP (0x1u << 8) /**< \brief (UDP_IER) Enable UDP Suspend Interrupt */ |
| 6098 | #define UDP_IER_RXRSM (0x1u << 9) /**< \brief (UDP_IER) Enable UDP Resume Interrupt */ |
| 6099 | #define UDP_IER_EXTRSM (0x1u << 10) /**< \brief (UDP_IER) */ |
| 6100 | #define UDP_IER_SOFINT (0x1u << 11) /**< \brief (UDP_IER) Enable Start Of Frame Interrupt */ |
| 6101 | #define UDP_IER_WAKEUP (0x1u << 13) /**< \brief (UDP_IER) Enable UDP bus Wakeup Interrupt */ |
| 6102 | /* -------- UDP_IDR : (UDP Offset: 0x014) Interrupt Disable Register -------- */ |
| 6103 | #define UDP_IDR_EP0INT (0x1u << 0) /**< \brief (UDP_IDR) Disable Endpoint 0 Interrupt */ |
| 6104 | #define UDP_IDR_EP1INT (0x1u << 1) /**< \brief (UDP_IDR) Disable Endpoint 1 Interrupt */ |
| 6105 | #define UDP_IDR_EP2INT (0x1u << 2) /**< \brief (UDP_IDR) Disable Endpoint 2 Interrupt */ |
| 6106 | #define UDP_IDR_EP3INT (0x1u << 3) /**< \brief (UDP_IDR) Disable Endpoint 3 Interrupt */ |
| 6107 | #define UDP_IDR_EP4INT (0x1u << 4) /**< \brief (UDP_IDR) Disable Endpoint 4 Interrupt */ |
| 6108 | #define UDP_IDR_EP5INT (0x1u << 5) /**< \brief (UDP_IDR) Disable Endpoint 5 Interrupt */ |
| 6109 | #define UDP_IDR_EP6INT (0x1u << 6) /**< \brief (UDP_IDR) Disable Endpoint 6 Interrupt */ |
| 6110 | #define UDP_IDR_EP7INT (0x1u << 7) /**< \brief (UDP_IDR) Disable Endpoint 7 Interrupt */ |
| 6111 | #define UDP_IDR_RXSUSP (0x1u << 8) /**< \brief (UDP_IDR) Disable UDP Suspend Interrupt */ |
| 6112 | #define UDP_IDR_RXRSM (0x1u << 9) /**< \brief (UDP_IDR) Disable UDP Resume Interrupt */ |
| 6113 | #define UDP_IDR_EXTRSM (0x1u << 10) /**< \brief (UDP_IDR) */ |
| 6114 | #define UDP_IDR_SOFINT (0x1u << 11) /**< \brief (UDP_IDR) Disable Start Of Frame Interrupt */ |
| 6115 | #define UDP_IDR_WAKEUP (0x1u << 13) /**< \brief (UDP_IDR) Disable USB Bus Interrupt */ |
| 6116 | /* -------- UDP_IMR : (UDP Offset: 0x018) Interrupt Mask Register -------- */ |
| 6117 | #define UDP_IMR_EP0INT (0x1u << 0) /**< \brief (UDP_IMR) Mask Endpoint 0 Interrupt */ |
| 6118 | #define UDP_IMR_EP1INT (0x1u << 1) /**< \brief (UDP_IMR) Mask Endpoint 1 Interrupt */ |
| 6119 | #define UDP_IMR_EP2INT (0x1u << 2) /**< \brief (UDP_IMR) Mask Endpoint 2 Interrupt */ |
| 6120 | #define UDP_IMR_EP3INT (0x1u << 3) /**< \brief (UDP_IMR) Mask Endpoint 3 Interrupt */ |
| 6121 | #define UDP_IMR_EP4INT (0x1u << 4) /**< \brief (UDP_IMR) Mask Endpoint 4 Interrupt */ |
| 6122 | #define UDP_IMR_EP5INT (0x1u << 5) /**< \brief (UDP_IMR) Mask Endpoint 5 Interrupt */ |
| 6123 | #define UDP_IMR_EP6INT (0x1u << 6) /**< \brief (UDP_IMR) Mask Endpoint 6 Interrupt */ |
| 6124 | #define UDP_IMR_EP7INT (0x1u << 7) /**< \brief (UDP_IMR) Mask Endpoint 7 Interrupt */ |
| 6125 | #define UDP_IMR_RXSUSP (0x1u << 8) /**< \brief (UDP_IMR) Mask UDP Suspend Interrupt */ |
| 6126 | #define UDP_IMR_RXRSM (0x1u << 9) /**< \brief (UDP_IMR) Mask UDP Resume Interrupt. */ |
| 6127 | #define UDP_IMR_EXTRSM (0x1u << 10) /**< \brief (UDP_IMR) */ |
| 6128 | #define UDP_IMR_SOFINT (0x1u << 11) /**< \brief (UDP_IMR) Mask Start Of Frame Interrupt */ |
| 6129 | #define UDP_IMR_BIT12 (0x1u << 12) /**< \brief (UDP_IMR) UDP_IMR Bit 12 */ |
| 6130 | #define UDP_IMR_WAKEUP (0x1u << 13) /**< \brief (UDP_IMR) USB Bus WAKEUP Interrupt */ |
| 6131 | /* -------- UDP_ISR : (UDP Offset: 0x01C) Interrupt Status Register -------- */ |
| 6132 | #define UDP_ISR_EP0INT (0x1u << 0) /**< \brief (UDP_ISR) Endpoint 0 Interrupt Status */ |
| 6133 | #define UDP_ISR_EP1INT (0x1u << 1) /**< \brief (UDP_ISR) Endpoint 1 Interrupt Status */ |
| 6134 | #define UDP_ISR_EP2INT (0x1u << 2) /**< \brief (UDP_ISR) Endpoint 2 Interrupt Status */ |
| 6135 | #define UDP_ISR_EP3INT (0x1u << 3) /**< \brief (UDP_ISR) Endpoint 3 Interrupt Status */ |
| 6136 | #define UDP_ISR_EP4INT (0x1u << 4) /**< \brief (UDP_ISR) Endpoint 4 Interrupt Status */ |
| 6137 | #define UDP_ISR_EP5INT (0x1u << 5) /**< \brief (UDP_ISR) Endpoint 5 Interrupt Status */ |
| 6138 | #define UDP_ISR_EP6INT (0x1u << 6) /**< \brief (UDP_ISR) Endpoint 6 Interrupt Status */ |
| 6139 | #define UDP_ISR_EP7INT (0x1u << 7) /**< \brief (UDP_ISR) Endpoint 7Interrupt Status */ |
| 6140 | #define UDP_ISR_RXSUSP (0x1u << 8) /**< \brief (UDP_ISR) UDP Suspend Interrupt Status */ |
| 6141 | #define UDP_ISR_RXRSM (0x1u << 9) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */ |
| 6142 | #define UDP_ISR_EXTRSM (0x1u << 10) /**< \brief (UDP_ISR) */ |
| 6143 | #define UDP_ISR_SOFINT (0x1u << 11) /**< \brief (UDP_ISR) Start of Frame Interrupt Status */ |
| 6144 | #define UDP_ISR_ENDBUSRES (0x1u << 12) /**< \brief (UDP_ISR) End of BUS Reset Interrupt Status */ |
| 6145 | #define UDP_ISR_WAKEUP (0x1u << 13) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */ |
| 6146 | /* -------- UDP_ICR : (UDP Offset: 0x020) Interrupt Clear Register -------- */ |
| 6147 | #define UDP_ICR_RXSUSP (0x1u << 8) /**< \brief (UDP_ICR) Clear UDP Suspend Interrupt */ |
| 6148 | #define UDP_ICR_RXRSM (0x1u << 9) /**< \brief (UDP_ICR) Clear UDP Resume Interrupt */ |
| 6149 | #define UDP_ICR_EXTRSM (0x1u << 10) /**< \brief (UDP_ICR) */ |
| 6150 | #define UDP_ICR_SOFINT (0x1u << 11) /**< \brief (UDP_ICR) Clear Start Of Frame Interrupt */ |
| 6151 | #define UDP_ICR_ENDBUSRES (0x1u << 12) /**< \brief (UDP_ICR) Clear End of Bus Reset Interrupt */ |
| 6152 | #define UDP_ICR_WAKEUP (0x1u << 13) /**< \brief (UDP_ICR) Clear Wakeup Interrupt */ |
| 6153 | /* -------- UDP_RST_EP : (UDP Offset: 0x028) Reset Endpoint Register -------- */ |
| 6154 | #define UDP_RST_EP_EP0 (0x1u << 0) /**< \brief (UDP_RST_EP) Reset Endpoint 0 */ |
| 6155 | #define UDP_RST_EP_EP1 (0x1u << 1) /**< \brief (UDP_RST_EP) Reset Endpoint 1 */ |
| 6156 | #define UDP_RST_EP_EP2 (0x1u << 2) /**< \brief (UDP_RST_EP) Reset Endpoint 2 */ |
| 6157 | #define UDP_RST_EP_EP3 (0x1u << 3) /**< \brief (UDP_RST_EP) Reset Endpoint 3 */ |
| 6158 | #define UDP_RST_EP_EP4 (0x1u << 4) /**< \brief (UDP_RST_EP) Reset Endpoint 4 */ |
| 6159 | #define UDP_RST_EP_EP5 (0x1u << 5) /**< \brief (UDP_RST_EP) Reset Endpoint 5 */ |
| 6160 | #define UDP_RST_EP_EP6 (0x1u << 6) /**< \brief (UDP_RST_EP) Reset Endpoint 6 */ |
| 6161 | #define UDP_RST_EP_EP7 (0x1u << 7) /**< \brief (UDP_RST_EP) Reset Endpoint 7 */ |
| 6162 | /* -------- UDP_CSR[8] : (UDP Offset: 0x030) Endpoint Control and Status Register -------- */ |
| 6163 | #define UDP_CSR_TXCOMP (0x1u << 0) /**< \brief (UDP_CSR[8]) Generates an IN Packet with Data Previously Written in the DPR */ |
| 6164 | #define UDP_CSR_RX_DATA_BK0 (0x1u << 1) /**< \brief (UDP_CSR[8]) Receive Data Bank 0 */ |
| 6165 | #define UDP_CSR_RXSETUP (0x1u << 2) /**< \brief (UDP_CSR[8]) Received Setup */ |
| 6166 | #define UDP_CSR_STALLSENTISOERROR (0x1u << 3) /**< \brief (UDP_CSR[8]) */ |
| 6167 | #define UDP_CSR_TXPKTRDY (0x1u << 4) /**< \brief (UDP_CSR[8]) Transmit Packet Ready */ |
| 6168 | #define UDP_CSR_FORCESTALL (0x1u << 5) /**< \brief (UDP_CSR[8]) Force Stall (used by Control, Bulk and Isochronous Endpoints) */ |
| 6169 | #define UDP_CSR_RX_DATA_BK1 (0x1u << 6) /**< \brief (UDP_CSR[8]) Receive Data Bank 1 (only used by endpoints with ping-pong attributes) */ |
| 6170 | #define UDP_CSR_DIR (0x1u << 7) /**< \brief (UDP_CSR[8]) Transfer Direction (only available for control endpoints) */ |
| 6171 | #define UDP_CSR_EPTYPE_Pos 8 |
| 6172 | #define UDP_CSR_EPTYPE_Msk (0x7u << UDP_CSR_EPTYPE_Pos) /**< \brief (UDP_CSR[8]) Endpoint Type */ |
| 6173 | #define UDP_CSR_EPTYPE_CTRL (0x0u << 8) /**< \brief (UDP_CSR[8]) Control */ |
| 6174 | #define UDP_CSR_EPTYPE_ISO_OUT (0x1u << 8) /**< \brief (UDP_CSR[8]) Isochronous OUT */ |
| 6175 | #define UDP_CSR_EPTYPE_BULK_OUT (0x2u << 8) /**< \brief (UDP_CSR[8]) Bulk OUT */ |
| 6176 | #define UDP_CSR_EPTYPE_INT_OUT (0x3u << 8) /**< \brief (UDP_CSR[8]) Interrupt OUT */ |
| 6177 | #define UDP_CSR_EPTYPE_ISO_IN (0x5u << 8) /**< \brief (UDP_CSR[8]) Isochronous IN */ |
| 6178 | #define UDP_CSR_EPTYPE_BULK_IN (0x6u << 8) /**< \brief (UDP_CSR[8]) Bulk IN */ |
| 6179 | #define UDP_CSR_EPTYPE_INT_IN (0x7u << 8) /**< \brief (UDP_CSR[8]) Interrupt IN */ |
| 6180 | #define UDP_CSR_DTGLE (0x1u << 11) /**< \brief (UDP_CSR[8]) Data Toggle */ |
| 6181 | #define UDP_CSR_EPEDS (0x1u << 15) /**< \brief (UDP_CSR[8]) Endpoint Enable Disable */ |
| 6182 | #define UDP_CSR_RXBYTECNT_Pos 16 |
| 6183 | #define UDP_CSR_RXBYTECNT_Msk (0x7ffu << UDP_CSR_RXBYTECNT_Pos) /**< \brief (UDP_CSR[8]) Number of Bytes Available in the FIFO */ |
| 6184 | #define UDP_CSR_RXBYTECNT(value) ((UDP_CSR_RXBYTECNT_Msk & ((value) << UDP_CSR_RXBYTECNT_Pos))) |
| 6185 | /* -------- UDP_FDR[8] : (UDP Offset: 0x050) Endpoint FIFO Data Register -------- */ |
| 6186 | #define UDP_FDR_FIFO_DATA_Pos 0 |
| 6187 | #define UDP_FDR_FIFO_DATA_Msk (0xffu << UDP_FDR_FIFO_DATA_Pos) /**< \brief (UDP_FDR[8]) FIFO Data Value */ |
| 6188 | #define UDP_FDR_FIFO_DATA(value) ((UDP_FDR_FIFO_DATA_Msk & ((value) << UDP_FDR_FIFO_DATA_Pos))) |
| 6189 | /* -------- UDP_TXVC : (UDP Offset: 0x074) Transceiver Control Register -------- */ |
| 6190 | #define UDP_TXVC_TXVDIS (0x1u << 8) /**< \brief (UDP_TXVC) Transceiver Disable */ |
| 6191 | #define UDP_TXVC_PUON (0x1u << 9) /**< \brief (UDP_TXVC) Pullup On */ |
| 6192 | |
| 6193 | /*@}*/ |
| 6194 | |
| 6195 | /* ============================================================================= */ |
| 6196 | /** SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */ |
| 6197 | /* ============================================================================= */ |
| 6198 | /** \addtogroup SAM3S_USART Universal Synchronous Asynchronous Receiver Transmitter */ |
| 6199 | /*@{*/ |
| 6200 | |
| 6201 | #ifndef __ASSEMBLY__ |
| 6202 | /** \brief Usart hardware registers */ |
| 6203 | typedef struct { |
| 6204 | WoReg US_CR; /**< \brief (Usart Offset: 0x0000) Control Register */ |
| 6205 | RwReg US_MR; /**< \brief (Usart Offset: 0x0004) Mode Register */ |
| 6206 | WoReg US_IER; /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */ |
| 6207 | WoReg US_IDR; /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */ |
| 6208 | RoReg US_IMR; /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */ |
| 6209 | RoReg US_CSR; /**< \brief (Usart Offset: 0x0014) Channel Status Register */ |
| 6210 | RoReg US_RHR; /**< \brief (Usart Offset: 0x0018) Receiver Holding Register */ |
| 6211 | WoReg US_THR; /**< \brief (Usart Offset: 0x001C) Transmitter Holding Register */ |
| 6212 | RwReg US_BRGR; /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */ |
| 6213 | RwReg US_RTOR; /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */ |
| 6214 | RwReg US_TTGR; /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */ |
| 6215 | RwReg Reserved1[5]; |
| 6216 | RwReg US_FIDI; /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */ |
| 6217 | RoReg US_NER; /**< \brief (Usart Offset: 0x0044) Number of Errors Register */ |
| 6218 | RwReg Reserved2[1]; |
| 6219 | RwReg US_IF; /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */ |
| 6220 | RwReg US_MAN; /**< \brief (Usart Offset: 0x0050) Manchester Encoder Decoder Register */ |
| 6221 | RwReg Reserved3[36]; |
| 6222 | RwReg US_WPMR; /**< \brief (Usart Offset: 0xE4) Write Protect Mode Register */ |
| 6223 | RoReg US_WPSR; /**< \brief (Usart Offset: 0xE8) Write Protect Status Register */ |
| 6224 | RwReg Reserved4[5]; |
| 6225 | RwReg US_RPR; /**< \brief (Usart Offset: 0x100) Receive Pointer Register */ |
| 6226 | RwReg US_RCR; /**< \brief (Usart Offset: 0x104) Receive Counter Register */ |
| 6227 | RwReg US_TPR; /**< \brief (Usart Offset: 0x108) Transmit Pointer Register */ |
| 6228 | RwReg US_TCR; /**< \brief (Usart Offset: 0x10C) Transmit Counter Register */ |
| 6229 | RwReg US_RNPR; /**< \brief (Usart Offset: 0x110) Receive Next Pointer Register */ |
| 6230 | RwReg US_RNCR; /**< \brief (Usart Offset: 0x114) Receive Next Counter Register */ |
| 6231 | RwReg US_TNPR; /**< \brief (Usart Offset: 0x118) Transmit Next Pointer Register */ |
| 6232 | RwReg US_TNCR; /**< \brief (Usart Offset: 0x11C) Transmit Next Counter Register */ |
| 6233 | WoReg US_PTCR; /**< \brief (Usart Offset: 0x120) Transfer Control Register */ |
| 6234 | RoReg US_PTSR; /**< \brief (Usart Offset: 0x124) Transfer Status Register */ |
| 6235 | } Usart; |
| 6236 | #endif /* __ASSEMBLY__ */ |
| 6237 | /* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */ |
| 6238 | #define US_CR_RSTRX (0x1u << 2) /**< \brief (US_CR) Reset Receiver */ |
| 6239 | #define US_CR_RSTTX (0x1u << 3) /**< \brief (US_CR) Reset Transmitter */ |
| 6240 | #define US_CR_RXEN (0x1u << 4) /**< \brief (US_CR) Receiver Enable */ |
| 6241 | #define US_CR_RXDIS (0x1u << 5) /**< \brief (US_CR) Receiver Disable */ |
| 6242 | #define US_CR_TXEN (0x1u << 6) /**< \brief (US_CR) Transmitter Enable */ |
| 6243 | #define US_CR_TXDIS (0x1u << 7) /**< \brief (US_CR) Transmitter Disable */ |
| 6244 | #define US_CR_RSTSTA (0x1u << 8) /**< \brief (US_CR) Reset Status Bits */ |
| 6245 | #define US_CR_STTBRK (0x1u << 9) /**< \brief (US_CR) Start Break */ |
| 6246 | #define US_CR_STPBRK (0x1u << 10) /**< \brief (US_CR) Stop Break */ |
| 6247 | #define US_CR_STTTO (0x1u << 11) /**< \brief (US_CR) Start Time-out */ |
| 6248 | #define US_CR_SENDA (0x1u << 12) /**< \brief (US_CR) Send Address */ |
| 6249 | #define US_CR_RSTIT (0x1u << 13) /**< \brief (US_CR) Reset Iterations */ |
| 6250 | #define US_CR_RSTNACK (0x1u << 14) /**< \brief (US_CR) Reset Non Acknowledge */ |
| 6251 | #define US_CR_RETTO (0x1u << 15) /**< \brief (US_CR) Rearm Time-out */ |
| 6252 | #define US_CR_DTREN (0x1u << 16) /**< \brief (US_CR) Data Terminal Ready Enable */ |
| 6253 | #define US_CR_DTRDIS (0x1u << 17) /**< \brief (US_CR) Data Terminal Ready Disable */ |
| 6254 | #define US_CR_RTSEN (0x1u << 18) /**< \brief (US_CR) Request to Send Enable */ |
| 6255 | #define US_CR_FCS (0x1u << 18) /**< \brief (US_CR) Force SPI Chip Select */ |
| 6256 | #define US_CR_RTSDIS (0x1u << 19) /**< \brief (US_CR) Request to Send Disable */ |
| 6257 | #define US_CR_RCS (0x1u << 19) /**< \brief (US_CR) Release SPI Chip Select */ |
| 6258 | /* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */ |
| 6259 | #define US_MR_USART_MODE_Pos 0 |
| 6260 | #define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos) /**< \brief (US_MR) */ |
| 6261 | #define US_MR_USART_MODE_NORMAL (0x0u << 0) /**< \brief (US_MR) Normal mode */ |
| 6262 | #define US_MR_USART_MODE_RS485 (0x1u << 0) /**< \brief (US_MR) RS485 */ |
| 6263 | #define US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0) /**< \brief (US_MR) Hardware Handshaking */ |
| 6264 | #define US_MR_USART_MODE_MODEM (0x3u << 0) /**< \brief (US_MR) Modem */ |
| 6265 | #define US_MR_USART_MODE_IS07816_T_0 (0x4u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 0 */ |
| 6266 | #define US_MR_USART_MODE_IS07816_T_1 (0x6u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 1 */ |
| 6267 | #define US_MR_USART_MODE_IRDA (0x8u << 0) /**< \brief (US_MR) IrDA */ |
| 6268 | #define US_MR_USART_MODE_SPI_MASTER (0xEu << 0) /**< \brief (US_MR) SPI Master */ |
| 6269 | #define US_MR_USART_MODE_SPI_SLAVE (0xFu << 0) /**< \brief (US_MR) SPI Slave */ |
| 6270 | #define US_MR_USCLKS_Pos 4 |
| 6271 | #define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos) /**< \brief (US_MR) Clock Selection */ |
| 6272 | #define US_MR_USCLKS_MCK (0x0u << 4) /**< \brief (US_MR) Master Clock MCK is selected */ |
| 6273 | #define US_MR_USCLKS_DIV (0x1u << 4) /**< \brief (US_MR) Internal Clock Divided MCK/DIV (DIV=8) is selected */ |
| 6274 | #define US_MR_USCLKS_SCK (0x3u << 4) /**< \brief (US_MR) Serial Clock SLK is selected */ |
| 6275 | #define US_MR_CHRL_Pos 6 |
| 6276 | #define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos) /**< \brief (US_MR) Character Length. */ |
| 6277 | #define US_MR_CHRL_5_BIT (0x0u << 6) /**< \brief (US_MR) Character length is 5 bits */ |
| 6278 | #define US_MR_CHRL_6_BIT (0x1u << 6) /**< \brief (US_MR) Character length is 6 bits */ |
| 6279 | #define US_MR_CHRL_7_BIT (0x2u << 6) /**< \brief (US_MR) Character length is 7 bits */ |
| 6280 | #define US_MR_CHRL_8_BIT (0x3u << 6) /**< \brief (US_MR) Character length is 8 bits */ |
| 6281 | #define US_MR_SYNC (0x1u << 8) /**< \brief (US_MR) Synchronous Mode Select */ |
| 6282 | #define US_MR_CPHA (0x1u << 8) /**< \brief (US_MR) SPI Clock Phase */ |
| 6283 | #define US_MR_PAR_Pos 9 |
| 6284 | #define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos) /**< \brief (US_MR) Parity Type */ |
| 6285 | #define US_MR_PAR_EVEN (0x0u << 9) /**< \brief (US_MR) Even parity */ |
| 6286 | #define US_MR_PAR_ODD (0x1u << 9) /**< \brief (US_MR) Odd parity */ |
| 6287 | #define US_MR_PAR_SPACE (0x2u << 9) /**< \brief (US_MR) Parity forced to 0 (Space) */ |
| 6288 | #define US_MR_PAR_MARK (0x3u << 9) /**< \brief (US_MR) Parity forced to 1 (Mark) */ |
| 6289 | #define US_MR_PAR_NO (0x4u << 9) /**< \brief (US_MR) No parity */ |
| 6290 | #define US_MR_PAR_MULTIDROP (0x6u << 9) /**< \brief (US_MR) Multidrop mode */ |
| 6291 | #define US_MR_NBSTOP_Pos 12 |
| 6292 | #define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos) /**< \brief (US_MR) Number of Stop Bits */ |
| 6293 | #define US_MR_NBSTOP_1_BIT (0x0u << 12) /**< \brief (US_MR) 1 stop bit */ |
| 6294 | #define US_MR_NBSTOP_1_5_BIT (0x1u << 12) /**< \brief (US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) */ |
| 6295 | #define US_MR_NBSTOP_2_BIT (0x2u << 12) /**< \brief (US_MR) 2 stop bits */ |
| 6296 | #define US_MR_CHMODE_Pos 14 |
| 6297 | #define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos) /**< \brief (US_MR) Channel Mode */ |
| 6298 | #define US_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (US_MR) Normal Mode */ |
| 6299 | #define US_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. */ |
| 6300 | #define US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. */ |
| 6301 | #define US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. */ |
| 6302 | #define US_MR_MSBF (0x1u << 16) /**< \brief (US_MR) Bit Order */ |
| 6303 | #define US_MR_CPOL (0x1u << 16) /**< \brief (US_MR) SPI Clock Polarity */ |
| 6304 | #define US_MR_MODE9 (0x1u << 17) /**< \brief (US_MR) 9-bit Character Length */ |
| 6305 | #define US_MR_CLKO (0x1u << 18) /**< \brief (US_MR) Clock Output Select */ |
| 6306 | #define US_MR_OVER (0x1u << 19) /**< \brief (US_MR) Oversampling Mode */ |
| 6307 | #define US_MR_INACK (0x1u << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */ |
| 6308 | #define US_MR_DSNACK (0x1u << 21) /**< \brief (US_MR) Disable Successive NACK */ |
| 6309 | #define US_MR_VAR_SYNC (0x1u << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */ |
| 6310 | #define US_MR_INVDATA (0x1u << 23) /**< \brief (US_MR) INverted Data */ |
| 6311 | #define US_MR_MAX_ITERATION_Pos 24 |
| 6312 | #define US_MR_MAX_ITERATION_Msk (0x7u << US_MR_MAX_ITERATION_Pos) /**< \brief (US_MR) */ |
| 6313 | #define US_MR_MAX_ITERATION(value) ((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos))) |
| 6314 | #define US_MR_FILTER (0x1u << 28) /**< \brief (US_MR) Infrared Receive Line Filter */ |
| 6315 | #define US_MR_MAN (0x1u << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */ |
| 6316 | #define US_MR_MODSYNC (0x1u << 30) /**< \brief (US_MR) Manchester Synchronization Mode */ |
| 6317 | #define US_MR_ONEBIT (0x1u << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */ |
| 6318 | /* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */ |
| 6319 | #define US_IER_RXRDY (0x1u << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */ |
| 6320 | #define US_IER_TXRDY (0x1u << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */ |
| 6321 | #define US_IER_RXBRK (0x1u << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */ |
| 6322 | #define US_IER_ENDRX (0x1u << 3) /**< \brief (US_IER) End of Receive Transfer Interrupt Enable */ |
| 6323 | #define US_IER_ENDTX (0x1u << 4) /**< \brief (US_IER) End of Transmit Interrupt Enable */ |
| 6324 | #define US_IER_OVRE (0x1u << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */ |
| 6325 | #define US_IER_FRAME (0x1u << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */ |
| 6326 | #define US_IER_PARE (0x1u << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */ |
| 6327 | #define US_IER_TIMEOUT (0x1u << 8) /**< \brief (US_IER) Time-out Interrupt Enable */ |
| 6328 | #define US_IER_TXEMPTY (0x1u << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */ |
| 6329 | #define US_IER_ITER (0x1u << 10) /**< \brief (US_IER) Max number of Repetitions Reached */ |
| 6330 | #define US_IER_UNRE (0x1u << 10) /**< \brief (US_IER) SPI Underrun Error */ |
| 6331 | #define US_IER_TXBUFE (0x1u << 11) /**< \brief (US_IER) Buffer Empty Interrupt Enable */ |
| 6332 | #define US_IER_RXBUFF (0x1u << 12) /**< \brief (US_IER) Buffer Full Interrupt Enable */ |
| 6333 | #define US_IER_NACK (0x1u << 13) /**< \brief (US_IER) Non AcknowledgeInterrupt Enable */ |
| 6334 | #define US_IER_RIIC (0x1u << 16) /**< \brief (US_IER) Ring Indicator Input Change Enable */ |
| 6335 | #define US_IER_DSRIC (0x1u << 17) /**< \brief (US_IER) Data Set Ready Input Change Enable */ |
| 6336 | #define US_IER_DCDIC (0x1u << 18) /**< \brief (US_IER) Data Carrier Detect Input Change Interrupt Enable */ |
| 6337 | #define US_IER_CTSIC (0x1u << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */ |
| 6338 | #define US_IER_MANE (0x1u << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */ |
| 6339 | /* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */ |
| 6340 | #define US_IDR_RXRDY (0x1u << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */ |
| 6341 | #define US_IDR_TXRDY (0x1u << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */ |
| 6342 | #define US_IDR_RXBRK (0x1u << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */ |
| 6343 | #define US_IDR_ENDRX (0x1u << 3) /**< \brief (US_IDR) End of Receive Transfer Interrupt Disable */ |
| 6344 | #define US_IDR_ENDTX (0x1u << 4) /**< \brief (US_IDR) End of Transmit Interrupt Disable */ |
| 6345 | #define US_IDR_OVRE (0x1u << 5) /**< \brief (US_IDR) Overrun Error Interrupt Disable */ |
| 6346 | #define US_IDR_FRAME (0x1u << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */ |
| 6347 | #define US_IDR_PARE (0x1u << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */ |
| 6348 | #define US_IDR_TIMEOUT (0x1u << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */ |
| 6349 | #define US_IDR_TXEMPTY (0x1u << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */ |
| 6350 | #define US_IDR_ITER (0x1u << 10) /**< \brief (US_IDR) Max number of Repetitions Reached Disable */ |
| 6351 | #define US_IDR_UNRE (0x1u << 10) /**< \brief (US_IDR) SPI Underrun Error Disable */ |
| 6352 | #define US_IDR_TXBUFE (0x1u << 11) /**< \brief (US_IDR) Buffer Empty Interrupt Disable */ |
| 6353 | #define US_IDR_RXBUFF (0x1u << 12) /**< \brief (US_IDR) Buffer Full Interrupt Disable */ |
| 6354 | #define US_IDR_NACK (0x1u << 13) /**< \brief (US_IDR) Non AcknowledgeInterrupt Disable */ |
| 6355 | #define US_IDR_RIIC (0x1u << 16) /**< \brief (US_IDR) Ring Indicator Input Change Disable */ |
| 6356 | #define US_IDR_DSRIC (0x1u << 17) /**< \brief (US_IDR) Data Set Ready Input Change Disable */ |
| 6357 | #define US_IDR_DCDIC (0x1u << 18) /**< \brief (US_IDR) Data Carrier Detect Input Change Interrupt Disable */ |
| 6358 | #define US_IDR_CTSIC (0x1u << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */ |
| 6359 | #define US_IDR_MANE (0x1u << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */ |
| 6360 | /* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */ |
| 6361 | #define US_IMR_RXRDY (0x1u << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */ |
| 6362 | #define US_IMR_TXRDY (0x1u << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */ |
| 6363 | #define US_IMR_RXBRK (0x1u << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */ |
| 6364 | #define US_IMR_ENDRX (0x1u << 3) /**< \brief (US_IMR) End of Receive Transfer Interrupt Mask */ |
| 6365 | #define US_IMR_ENDTX (0x1u << 4) /**< \brief (US_IMR) End of Transmit Interrupt Mask */ |
| 6366 | #define US_IMR_OVRE (0x1u << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */ |
| 6367 | #define US_IMR_FRAME (0x1u << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */ |
| 6368 | #define US_IMR_PARE (0x1u << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */ |
| 6369 | #define US_IMR_TIMEOUT (0x1u << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */ |
| 6370 | #define US_IMR_TXEMPTY (0x1u << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */ |
| 6371 | #define US_IMR_ITER (0x1u << 10) /**< \brief (US_IMR) Max number of Repetitions Reached Mask */ |
| 6372 | #define US_IMR_UNRE (0x1u << 10) /**< \brief (US_IMR) SPI Underrun Error Mask */ |
| 6373 | #define US_IMR_TXBUFE (0x1u << 11) /**< \brief (US_IMR) Buffer Empty Interrupt Mask */ |
| 6374 | #define US_IMR_RXBUFF (0x1u << 12) /**< \brief (US_IMR) Buffer Full Interrupt Mask */ |
| 6375 | #define US_IMR_NACK (0x1u << 13) /**< \brief (US_IMR) Non AcknowledgeInterrupt Mask */ |
| 6376 | #define US_IMR_RIIC (0x1u << 16) /**< \brief (US_IMR) Ring Indicator Input Change Mask */ |
| 6377 | #define US_IMR_DSRIC (0x1u << 17) /**< \brief (US_IMR) Data Set Ready Input Change Mask */ |
| 6378 | #define US_IMR_DCDIC (0x1u << 18) /**< \brief (US_IMR) Data Carrier Detect Input Change Interrupt Mask */ |
| 6379 | #define US_IMR_CTSIC (0x1u << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */ |
| 6380 | #define US_IMR_MANE (0x1u << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */ |
| 6381 | /* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */ |
| 6382 | #define US_CSR_RXRDY (0x1u << 0) /**< \brief (US_CSR) Receiver Ready */ |
| 6383 | #define US_CSR_TXRDY (0x1u << 1) /**< \brief (US_CSR) Transmitter Ready */ |
| 6384 | #define US_CSR_RXBRK (0x1u << 2) /**< \brief (US_CSR) Break Received/End of Break */ |
| 6385 | #define US_CSR_ENDRX (0x1u << 3) /**< \brief (US_CSR) End of Receiver Transfer */ |
| 6386 | #define US_CSR_ENDTX (0x1u << 4) /**< \brief (US_CSR) End of Transmitter Transfer */ |
| 6387 | #define US_CSR_OVRE (0x1u << 5) /**< \brief (US_CSR) Overrun Error */ |
| 6388 | #define US_CSR_FRAME (0x1u << 6) /**< \brief (US_CSR) Framing Error */ |
| 6389 | #define US_CSR_PARE (0x1u << 7) /**< \brief (US_CSR) Parity Error */ |
| 6390 | #define US_CSR_TIMEOUT (0x1u << 8) /**< \brief (US_CSR) Receiver Time-out */ |
| 6391 | #define US_CSR_TXEMPTY (0x1u << 9) /**< \brief (US_CSR) Transmitter Empty */ |
| 6392 | #define US_CSR_ITER (0x1u << 10) /**< \brief (US_CSR) Max number of Repetitions Reached */ |
| 6393 | #define US_CSR_UNRE (0x1u << 10) /**< \brief (US_CSR) SPI Underrun Error */ |
| 6394 | #define US_CSR_TXBUFE (0x1u << 11) /**< \brief (US_CSR) Transmission Buffer Empty */ |
| 6395 | #define US_CSR_RXBUFF (0x1u << 12) /**< \brief (US_CSR) Reception Buffer Full */ |
| 6396 | #define US_CSR_NACK (0x1u << 13) /**< \brief (US_CSR) Non AcknowledgeInterrupt */ |
| 6397 | #define US_CSR_RIIC (0x1u << 16) /**< \brief (US_CSR) Ring Indicator Input Change Flag */ |
| 6398 | #define US_CSR_DSRIC (0x1u << 17) /**< \brief (US_CSR) Data Set Ready Input Change Flag */ |
| 6399 | #define US_CSR_DCDIC (0x1u << 18) /**< \brief (US_CSR) Data Carrier Detect Input Change Flag */ |
| 6400 | #define US_CSR_CTSIC (0x1u << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag */ |
| 6401 | #define US_CSR_RI (0x1u << 20) /**< \brief (US_CSR) Image of RI Input */ |
| 6402 | #define US_CSR_DSR (0x1u << 21) /**< \brief (US_CSR) Image of DSR Input */ |
| 6403 | #define US_CSR_DCD (0x1u << 22) /**< \brief (US_CSR) Image of DCD Input */ |
| 6404 | #define US_CSR_CTS (0x1u << 23) /**< \brief (US_CSR) Image of CTS Input */ |
| 6405 | #define US_CSR_MANERR (0x1u << 24) /**< \brief (US_CSR) Manchester Error */ |
| 6406 | /* -------- US_RHR : (USART Offset: 0x0018) Receiver Holding Register -------- */ |
| 6407 | #define US_RHR_RXCHR_Pos 0 |
| 6408 | #define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos) /**< \brief (US_RHR) Received Character */ |
| 6409 | #define US_RHR_RXSYNH (0x1u << 15) /**< \brief (US_RHR) Received Sync */ |
| 6410 | /* -------- US_THR : (USART Offset: 0x001C) Transmitter Holding Register -------- */ |
| 6411 | #define US_THR_TXCHR_Pos 0 |
| 6412 | #define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos) /**< \brief (US_THR) Character to be Transmitted */ |
| 6413 | #define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos))) |
| 6414 | #define US_THR_TXSYNH (0x1u << 15) /**< \brief (US_THR) Sync Field to be transmitted */ |
| 6415 | /* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */ |
| 6416 | #define US_BRGR_CD_Pos 0 |
| 6417 | #define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos) /**< \brief (US_BRGR) Clock Divider */ |
| 6418 | #define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos))) |
| 6419 | #define US_BRGR_FP_Pos 16 |
| 6420 | #define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos) /**< \brief (US_BRGR) Fractional Part */ |
| 6421 | #define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos))) |
| 6422 | /* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */ |
| 6423 | #define US_RTOR_TO_Pos 0 |
| 6424 | #define US_RTOR_TO_Msk (0xffffu << US_RTOR_TO_Pos) /**< \brief (US_RTOR) Time-out Value */ |
| 6425 | #define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos))) |
| 6426 | /* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */ |
| 6427 | #define US_TTGR_TG_Pos 0 |
| 6428 | #define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos) /**< \brief (US_TTGR) Timeguard Value */ |
| 6429 | #define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos))) |
| 6430 | /* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */ |
| 6431 | #define US_FIDI_FI_DI_RATIO_Pos 0 |
| 6432 | #define US_FIDI_FI_DI_RATIO_Msk (0x7ffu << US_FIDI_FI_DI_RATIO_Pos) /**< \brief (US_FIDI) FI Over DI Ratio Value */ |
| 6433 | #define US_FIDI_FI_DI_RATIO(value) ((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos))) |
| 6434 | /* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */ |
| 6435 | #define US_NER_NB_ERRORS_Pos 0 |
| 6436 | #define US_NER_NB_ERRORS_Msk (0xffu << US_NER_NB_ERRORS_Pos) /**< \brief (US_NER) Number of Errors */ |
| 6437 | /* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */ |
| 6438 | #define US_IF_IRDA_FILTER_Pos 0 |
| 6439 | #define US_IF_IRDA_FILTER_Msk (0xffu << US_IF_IRDA_FILTER_Pos) /**< \brief (US_IF) IrDA Filter */ |
| 6440 | #define US_IF_IRDA_FILTER(value) ((US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos))) |
| 6441 | /* -------- US_MAN : (USART Offset: 0x0050) Manchester Encoder Decoder Register -------- */ |
| 6442 | #define US_MAN_TX_PL_Pos 0 |
| 6443 | #define US_MAN_TX_PL_Msk (0xfu << US_MAN_TX_PL_Pos) /**< \brief (US_MAN) Transmitter Preamble Length */ |
| 6444 | #define US_MAN_TX_PL(value) ((US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos))) |
| 6445 | #define US_MAN_TX_PP_Pos 8 |
| 6446 | #define US_MAN_TX_PP_Msk (0x3u << US_MAN_TX_PP_Pos) /**< \brief (US_MAN) Transmitter Preamble Pattern */ |
| 6447 | #define US_MAN_TX_PP_ALL_ONE (0x0u << 8) /**< \brief (US_MAN) The preamble is composed of '1's */ |
| 6448 | #define US_MAN_TX_PP_ALL_ZERO (0x1u << 8) /**< \brief (US_MAN) The preamble is composed of '0's */ |
| 6449 | #define US_MAN_TX_PP_ZERO_ONE (0x2u << 8) /**< \brief (US_MAN) The preamble is composed of '01's */ |
| 6450 | #define US_MAN_TX_PP_ONE_ZERO (0x3u << 8) /**< \brief (US_MAN) The preamble is composed of '10's */ |
| 6451 | #define US_MAN_TX_MPOL (0x1u << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */ |
| 6452 | #define US_MAN_RX_PL_Pos 16 |
| 6453 | #define US_MAN_RX_PL_Msk (0xfu << US_MAN_RX_PL_Pos) /**< \brief (US_MAN) Receiver Preamble Length */ |
| 6454 | #define US_MAN_RX_PL(value) ((US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos))) |
| 6455 | #define US_MAN_RX_PP_Pos 24 |
| 6456 | #define US_MAN_RX_PP_Msk (0x3u << US_MAN_RX_PP_Pos) /**< \brief (US_MAN) Receiver Preamble Pattern detected */ |
| 6457 | #define US_MAN_RX_PP_ALL_ONE (0x0u << 24) /**< \brief (US_MAN) The preamble is composed of '1's */ |
| 6458 | #define US_MAN_RX_PP_ALL_ZERO (0x1u << 24) /**< \brief (US_MAN) The preamble is composed of '0's */ |
| 6459 | #define US_MAN_RX_PP_ZERO_ONE (0x2u << 24) /**< \brief (US_MAN) The preamble is composed of '01's */ |
| 6460 | #define US_MAN_RX_PP_ONE_ZERO (0x3u << 24) /**< \brief (US_MAN) The preamble is composed of '10's */ |
| 6461 | #define US_MAN_RX_MPOL (0x1u << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */ |
| 6462 | #define US_MAN_STUCKTO1 (0x1u << 29) /**< \brief (US_MAN) */ |
| 6463 | #define US_MAN_DRIFT (0x1u << 30) /**< \brief (US_MAN) Drift compensation */ |
| 6464 | /* -------- US_WPMR : (USART Offset: 0xE4) Write Protect Mode Register -------- */ |
| 6465 | #define US_WPMR_WPEN (0x1u << 0) /**< \brief (US_WPMR) Write Protect Enable */ |
| 6466 | #define US_WPMR_WPKEY_Pos 8 |
| 6467 | #define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos) /**< \brief (US_WPMR) Write Protect KEY */ |
| 6468 | #define US_WPMR_WPKEY(value) ((US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos))) |
| 6469 | /* -------- US_WPSR : (USART Offset: 0xE8) Write Protect Status Register -------- */ |
| 6470 | #define US_WPSR_WPVS (0x1u << 0) /**< \brief (US_WPSR) Write Protect Violation Status */ |
| 6471 | #define US_WPSR_WPVSRC_Pos 8 |
| 6472 | #define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos) /**< \brief (US_WPSR) Write Protect Violation Source */ |
| 6473 | /* -------- US_RPR : (USART Offset: 0x100) Receive Pointer Register -------- */ |
| 6474 | #define US_RPR_RXPTR_Pos 0 |
| 6475 | #define US_RPR_RXPTR_Msk (0xffffffffu << US_RPR_RXPTR_Pos) /**< \brief (US_RPR) Receive Pointer Register */ |
| 6476 | #define US_RPR_RXPTR(value) ((US_RPR_RXPTR_Msk & ((value) << US_RPR_RXPTR_Pos))) |
| 6477 | /* -------- US_RCR : (USART Offset: 0x104) Receive Counter Register -------- */ |
| 6478 | #define US_RCR_RXCTR_Pos 0 |
| 6479 | #define US_RCR_RXCTR_Msk (0xffffu << US_RCR_RXCTR_Pos) /**< \brief (US_RCR) Receive Counter Register */ |
| 6480 | #define US_RCR_RXCTR(value) ((US_RCR_RXCTR_Msk & ((value) << US_RCR_RXCTR_Pos))) |
| 6481 | /* -------- US_TPR : (USART Offset: 0x108) Transmit Pointer Register -------- */ |
| 6482 | #define US_TPR_TXPTR_Pos 0 |
| 6483 | #define US_TPR_TXPTR_Msk (0xffffffffu << US_TPR_TXPTR_Pos) /**< \brief (US_TPR) Transmit Counter Register */ |
| 6484 | #define US_TPR_TXPTR(value) ((US_TPR_TXPTR_Msk & ((value) << US_TPR_TXPTR_Pos))) |
| 6485 | /* -------- US_TCR : (USART Offset: 0x10C) Transmit Counter Register -------- */ |
| 6486 | #define US_TCR_TXCTR_Pos 0 |
| 6487 | #define US_TCR_TXCTR_Msk (0xffffu << US_TCR_TXCTR_Pos) /**< \brief (US_TCR) Transmit Counter Register */ |
| 6488 | #define US_TCR_TXCTR(value) ((US_TCR_TXCTR_Msk & ((value) << US_TCR_TXCTR_Pos))) |
| 6489 | /* -------- US_RNPR : (USART Offset: 0x110) Receive Next Pointer Register -------- */ |
| 6490 | #define US_RNPR_RXNPTR_Pos 0 |
| 6491 | #define US_RNPR_RXNPTR_Msk (0xffffffffu << US_RNPR_RXNPTR_Pos) /**< \brief (US_RNPR) Receive Next Pointer */ |
| 6492 | #define US_RNPR_RXNPTR(value) ((US_RNPR_RXNPTR_Msk & ((value) << US_RNPR_RXNPTR_Pos))) |
| 6493 | /* -------- US_RNCR : (USART Offset: 0x114) Receive Next Counter Register -------- */ |
| 6494 | #define US_RNCR_RXNCTR_Pos 0 |
| 6495 | #define US_RNCR_RXNCTR_Msk (0xffffu << US_RNCR_RXNCTR_Pos) /**< \brief (US_RNCR) Receive Next Counter */ |
| 6496 | #define US_RNCR_RXNCTR(value) ((US_RNCR_RXNCTR_Msk & ((value) << US_RNCR_RXNCTR_Pos))) |
| 6497 | /* -------- US_TNPR : (USART Offset: 0x118) Transmit Next Pointer Register -------- */ |
| 6498 | #define US_TNPR_TXNPTR_Pos 0 |
| 6499 | #define US_TNPR_TXNPTR_Msk (0xffffffffu << US_TNPR_TXNPTR_Pos) /**< \brief (US_TNPR) Transmit Next Pointer */ |
| 6500 | #define US_TNPR_TXNPTR(value) ((US_TNPR_TXNPTR_Msk & ((value) << US_TNPR_TXNPTR_Pos))) |
| 6501 | /* -------- US_TNCR : (USART Offset: 0x11C) Transmit Next Counter Register -------- */ |
| 6502 | #define US_TNCR_TXNCTR_Pos 0 |
| 6503 | #define US_TNCR_TXNCTR_Msk (0xffffu << US_TNCR_TXNCTR_Pos) /**< \brief (US_TNCR) Transmit Counter Next */ |
| 6504 | #define US_TNCR_TXNCTR(value) ((US_TNCR_TXNCTR_Msk & ((value) << US_TNCR_TXNCTR_Pos))) |
| 6505 | /* -------- US_PTCR : (USART Offset: 0x120) Transfer Control Register -------- */ |
| 6506 | #define US_PTCR_RXTEN (0x1u << 0) /**< \brief (US_PTCR) Receiver Transfer Enable */ |
| 6507 | #define US_PTCR_RXTDIS (0x1u << 1) /**< \brief (US_PTCR) Receiver Transfer Disable */ |
| 6508 | #define US_PTCR_TXTEN (0x1u << 8) /**< \brief (US_PTCR) Transmitter Transfer Enable */ |
| 6509 | #define US_PTCR_TXTDIS (0x1u << 9) /**< \brief (US_PTCR) Transmitter Transfer Disable */ |
| 6510 | /* -------- US_PTSR : (USART Offset: 0x124) Transfer Status Register -------- */ |
| 6511 | #define US_PTSR_RXTEN (0x1u << 0) /**< \brief (US_PTSR) Receiver Transfer Enable */ |
| 6512 | #define US_PTSR_TXTEN (0x1u << 8) /**< \brief (US_PTSR) Transmitter Transfer Enable */ |
| 6513 | |
| 6514 | /*@}*/ |
| 6515 | |
| 6516 | /* ============================================================================= */ |
| 6517 | /** SOFTWARE API DEFINITION FOR Watchdog Timer */ |
| 6518 | /* ============================================================================= */ |
| 6519 | /** \addtogroup SAM3S_WDT Watchdog Timer */ |
| 6520 | /*@{*/ |
| 6521 | |
| 6522 | #ifndef __ASSEMBLY__ |
| 6523 | /** \brief Wdt hardware registers */ |
| 6524 | typedef struct { |
| 6525 | WoReg WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */ |
| 6526 | RwReg WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */ |
| 6527 | RoReg WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */ |
| 6528 | } Wdt; |
| 6529 | #endif /* __ASSEMBLY__ */ |
| 6530 | /* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */ |
| 6531 | #define WDT_CR_WDRSTT (0x1u << 0) /**< \brief (WDT_CR) Watchdog Restart */ |
| 6532 | #define WDT_CR_KEY_Pos 24 |
| 6533 | #define WDT_CR_KEY_Msk (0xffu << WDT_CR_KEY_Pos) /**< \brief (WDT_CR) Password */ |
| 6534 | #define WDT_CR_KEY(value) ((WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos))) |
| 6535 | /* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */ |
| 6536 | #define WDT_MR_WDV_Pos 0 |
| 6537 | #define WDT_MR_WDV_Msk (0xfffu << WDT_MR_WDV_Pos) /**< \brief (WDT_MR) Watchdog Counter Value */ |
| 6538 | #define WDT_MR_WDV(value) ((WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos))) |
| 6539 | #define WDT_MR_WDFIEN (0x1u << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */ |
| 6540 | #define WDT_MR_WDRSTEN (0x1u << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */ |
| 6541 | #define WDT_MR_WDRPROC (0x1u << 14) /**< \brief (WDT_MR) Watchdog Reset Processor */ |
| 6542 | #define WDT_MR_WDDIS (0x1u << 15) /**< \brief (WDT_MR) Watchdog Disable */ |
| 6543 | #define WDT_MR_WDD_Pos 16 |
| 6544 | #define WDT_MR_WDD_Msk (0xfffu << WDT_MR_WDD_Pos) /**< \brief (WDT_MR) Watchdog Delta Value */ |
| 6545 | #define WDT_MR_WDD(value) ((WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos))) |
| 6546 | #define WDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */ |
| 6547 | #define WDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */ |
| 6548 | /* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */ |
| 6549 | #define WDT_SR_WDUNF (0x1u << 0) /**< \brief (WDT_SR) Watchdog Underflow */ |
| 6550 | #define WDT_SR_WDERR (0x1u << 1) /**< \brief (WDT_SR) Watchdog Error */ |
| 6551 | |
| 6552 | /*@}*/ |
| 6553 | |
| 6554 | /*@}*/ |
| 6555 | |
| 6556 | /* ************************************************************************** */ |
| 6557 | /* REGISTER ACCESS DEFINITIONS FOR SAM3S */ |
| 6558 | /* ************************************************************************** */ |
| 6559 | /** \addtogroup SAM3S_reg Registers Access Definitions */ |
| 6560 | /*@{*/ |
| 6561 | |
| 6562 | /* ========== Register definition for HSMCI peripheral ========== */ |
| 6563 | #define REG_HSMCI_CR REG_ACCESS(WoReg, 0x40000000U) /**< \brief (HSMCI) Control Register */ |
| 6564 | #define REG_HSMCI_MR REG_ACCESS(RwReg, 0x40000004U) /**< \brief (HSMCI) Mode Register */ |
| 6565 | #define REG_HSMCI_DTOR REG_ACCESS(RwReg, 0x40000008U) /**< \brief (HSMCI) Data Timeout Register */ |
| 6566 | #define REG_HSMCI_SDCR REG_ACCESS(RwReg, 0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */ |
| 6567 | #define REG_HSMCI_ARGR REG_ACCESS(RwReg, 0x40000010U) /**< \brief (HSMCI) Argument Register */ |
| 6568 | #define REG_HSMCI_CMDR REG_ACCESS(WoReg, 0x40000014U) /**< \brief (HSMCI) Command Register */ |
| 6569 | #define REG_HSMCI_BLKR REG_ACCESS(RwReg, 0x40000018U) /**< \brief (HSMCI) Block Register */ |
| 6570 | #define REG_HSMCI_CSTOR REG_ACCESS(RwReg, 0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */ |
| 6571 | #define REG_HSMCI_RSPR REG_ACCESS(RoReg, 0x40000020U) /**< \brief (HSMCI) Response Register */ |
| 6572 | #define REG_HSMCI_RDR REG_ACCESS(RoReg, 0x40000030U) /**< \brief (HSMCI) Receive Data Register */ |
| 6573 | #define REG_HSMCI_TDR REG_ACCESS(WoReg, 0x40000034U) /**< \brief (HSMCI) Transmit Data Register */ |
| 6574 | #define REG_HSMCI_SR REG_ACCESS(RoReg, 0x40000040U) /**< \brief (HSMCI) Status Register */ |
| 6575 | #define REG_HSMCI_IER REG_ACCESS(WoReg, 0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */ |
| 6576 | #define REG_HSMCI_IDR REG_ACCESS(WoReg, 0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */ |
| 6577 | #define REG_HSMCI_IMR REG_ACCESS(RoReg, 0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */ |
| 6578 | #define REG_HSMCI_CFG REG_ACCESS(RwReg, 0x40000054U) /**< \brief (HSMCI) Configuration Register */ |
| 6579 | #define REG_HSMCI_WPMR REG_ACCESS(RwReg, 0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */ |
| 6580 | #define REG_HSMCI_WPSR REG_ACCESS(RoReg, 0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */ |
| 6581 | #define REG_HSMCI_RPR REG_ACCESS(RwReg, 0x40000100U) /**< \brief (HSMCI) Receive Pointer Register */ |
| 6582 | #define REG_HSMCI_RCR REG_ACCESS(RwReg, 0x40000104U) /**< \brief (HSMCI) Receive Counter Register */ |
| 6583 | #define REG_HSMCI_TPR REG_ACCESS(RwReg, 0x40000108U) /**< \brief (HSMCI) Transmit Pointer Register */ |
| 6584 | #define REG_HSMCI_TCR REG_ACCESS(RwReg, 0x4000010CU) /**< \brief (HSMCI) Transmit Counter Register */ |
| 6585 | #define REG_HSMCI_RNPR REG_ACCESS(RwReg, 0x40000110U) /**< \brief (HSMCI) Receive Next Pointer Register */ |
| 6586 | #define REG_HSMCI_RNCR REG_ACCESS(RwReg, 0x40000114U) /**< \brief (HSMCI) Receive Next Counter Register */ |
| 6587 | #define REG_HSMCI_TNPR REG_ACCESS(RwReg, 0x40000118U) /**< \brief (HSMCI) Transmit Next Pointer Register */ |
| 6588 | #define REG_HSMCI_TNCR REG_ACCESS(RwReg, 0x4000011CU) /**< \brief (HSMCI) Transmit Next Counter Register */ |
| 6589 | #define REG_HSMCI_PTCR REG_ACCESS(WoReg, 0x40000120U) /**< \brief (HSMCI) Transfer Control Register */ |
| 6590 | #define REG_HSMCI_PTSR REG_ACCESS(RoReg, 0x40000124U) /**< \brief (HSMCI) Transfer Status Register */ |
| 6591 | #define REG_HSMCI_FIFO REG_ACCESS(RwReg, 0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */ |
| 6592 | /* ========== Register definition for SSC peripheral ========== */ |
| 6593 | #define REG_SSC_CR REG_ACCESS(WoReg, 0x40004000U) /**< \brief (SSC) Control Register */ |
| 6594 | #define REG_SSC_CMR REG_ACCESS(RwReg, 0x40004004U) /**< \brief (SSC) Clock Mode Register */ |
| 6595 | #define REG_SSC_RCMR REG_ACCESS(RwReg, 0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */ |
| 6596 | #define REG_SSC_RFMR REG_ACCESS(RwReg, 0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */ |
| 6597 | #define REG_SSC_TCMR REG_ACCESS(RwReg, 0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */ |
| 6598 | #define REG_SSC_TFMR REG_ACCESS(RwReg, 0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */ |
| 6599 | #define REG_SSC_RHR REG_ACCESS(RoReg, 0x40004020U) /**< \brief (SSC) Receive Holding Register */ |
| 6600 | #define REG_SSC_THR REG_ACCESS(WoReg, 0x40004024U) /**< \brief (SSC) Transmit Holding Register */ |
| 6601 | #define REG_SSC_RSHR REG_ACCESS(RoReg, 0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */ |
| 6602 | #define REG_SSC_TSHR REG_ACCESS(RwReg, 0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */ |
| 6603 | #define REG_SSC_RC0R REG_ACCESS(RwReg, 0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */ |
| 6604 | #define REG_SSC_RC1R REG_ACCESS(RwReg, 0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */ |
| 6605 | #define REG_SSC_SR REG_ACCESS(RoReg, 0x40004040U) /**< \brief (SSC) Status Register */ |
| 6606 | #define REG_SSC_IER REG_ACCESS(WoReg, 0x40004044U) /**< \brief (SSC) Interrupt Enable Register */ |
| 6607 | #define REG_SSC_IDR REG_ACCESS(WoReg, 0x40004048U) /**< \brief (SSC) Interrupt Disable Register */ |
| 6608 | #define REG_SSC_IMR REG_ACCESS(RoReg, 0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */ |
| 6609 | #define REG_SSC_WPMR REG_ACCESS(RwReg, 0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */ |
| 6610 | #define REG_SSC_WPSR REG_ACCESS(RoReg, 0x400040E8U) /**< \brief (SSC) Write Protect Status Register */ |
| 6611 | #define REG_SSC_RPR REG_ACCESS(RwReg, 0x40004100U) /**< \brief (SSC) Receive Pointer Register */ |
| 6612 | #define REG_SSC_RCR REG_ACCESS(RwReg, 0x40004104U) /**< \brief (SSC) Receive Counter Register */ |
| 6613 | #define REG_SSC_TPR REG_ACCESS(RwReg, 0x40004108U) /**< \brief (SSC) Transmit Pointer Register */ |
| 6614 | #define REG_SSC_TCR REG_ACCESS(RwReg, 0x4000410CU) /**< \brief (SSC) Transmit Counter Register */ |
| 6615 | #define REG_SSC_RNPR REG_ACCESS(RwReg, 0x40004110U) /**< \brief (SSC) Receive Next Pointer Register */ |
| 6616 | #define REG_SSC_RNCR REG_ACCESS(RwReg, 0x40004114U) /**< \brief (SSC) Receive Next Counter Register */ |
| 6617 | #define REG_SSC_TNPR REG_ACCESS(RwReg, 0x40004118U) /**< \brief (SSC) Transmit Next Pointer Register */ |
| 6618 | #define REG_SSC_TNCR REG_ACCESS(RwReg, 0x4000411CU) /**< \brief (SSC) Transmit Next Counter Register */ |
| 6619 | #define REG_SSC_PTCR REG_ACCESS(WoReg, 0x40004120U) /**< \brief (SSC) Transfer Control Register */ |
| 6620 | #define REG_SSC_PTSR REG_ACCESS(RoReg, 0x40004124U) /**< \brief (SSC) Transfer Status Register */ |
| 6621 | /* ========== Register definition for SPI peripheral ========== */ |
| 6622 | #define REG_SPI_CR REG_ACCESS(WoReg, 0x40008000U) /**< \brief (SPI) Control Register */ |
| 6623 | #define REG_SPI_MR REG_ACCESS(RwReg, 0x40008004U) /**< \brief (SPI) Mode Register */ |
| 6624 | #define REG_SPI_RDR REG_ACCESS(RoReg, 0x40008008U) /**< \brief (SPI) Receive Data Register */ |
| 6625 | #define REG_SPI_TDR REG_ACCESS(WoReg, 0x4000800CU) /**< \brief (SPI) Transmit Data Register */ |
| 6626 | #define REG_SPI_SR REG_ACCESS(RoReg, 0x40008010U) /**< \brief (SPI) Status Register */ |
| 6627 | #define REG_SPI_IER REG_ACCESS(WoReg, 0x40008014U) /**< \brief (SPI) Interrupt Enable Register */ |
| 6628 | #define REG_SPI_IDR REG_ACCESS(WoReg, 0x40008018U) /**< \brief (SPI) Interrupt Disable Register */ |
| 6629 | #define REG_SPI_IMR REG_ACCESS(RoReg, 0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */ |
| 6630 | #define REG_SPI_CSR REG_ACCESS(RwReg, 0x40008030U) /**< \brief (SPI) Chip Select Register */ |
| 6631 | #define REG_SPI_WPMR REG_ACCESS(RwReg, 0x400080E4U) /**< \brief (SPI) Write Protection Control Register */ |
| 6632 | #define REG_SPI_WPSR REG_ACCESS(RoReg, 0x400080E8U) /**< \brief (SPI) Write Protection Status Register */ |
| 6633 | #define REG_SPI_RPR REG_ACCESS(RwReg, 0x40008100U) /**< \brief (SPI) Receive Pointer Register */ |
| 6634 | #define REG_SPI_RCR REG_ACCESS(RwReg, 0x40008104U) /**< \brief (SPI) Receive Counter Register */ |
| 6635 | #define REG_SPI_TPR REG_ACCESS(RwReg, 0x40008108U) /**< \brief (SPI) Transmit Pointer Register */ |
| 6636 | #define REG_SPI_TCR REG_ACCESS(RwReg, 0x4000810CU) /**< \brief (SPI) Transmit Counter Register */ |
| 6637 | #define REG_SPI_RNPR REG_ACCESS(RwReg, 0x40008110U) /**< \brief (SPI) Receive Next Pointer Register */ |
| 6638 | #define REG_SPI_RNCR REG_ACCESS(RwReg, 0x40008114U) /**< \brief (SPI) Receive Next Counter Register */ |
| 6639 | #define REG_SPI_TNPR REG_ACCESS(RwReg, 0x40008118U) /**< \brief (SPI) Transmit Next Pointer Register */ |
| 6640 | #define REG_SPI_TNCR REG_ACCESS(RwReg, 0x4000811CU) /**< \brief (SPI) Transmit Next Counter Register */ |
| 6641 | #define REG_SPI_PTCR REG_ACCESS(WoReg, 0x40008120U) /**< \brief (SPI) Transfer Control Register */ |
| 6642 | #define REG_SPI_PTSR REG_ACCESS(RoReg, 0x40008124U) /**< \brief (SPI) Transfer Status Register */ |
| 6643 | /* ========== Register definition for TC0 peripheral ========== */ |
| 6644 | #define REG_TC0_CCR0 REG_ACCESS(WoReg, 0x40010000U) /**< \brief (TC0) Channel Control Register (channel = 0) */ |
| 6645 | #define REG_TC0_CMR0 REG_ACCESS(RwReg, 0x40010004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */ |
| 6646 | #define REG_TC0_SMMR0 REG_ACCESS(RwReg, 0x40010008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */ |
| 6647 | #define REG_TC0_CV0 REG_ACCESS(RoReg, 0x40010010U) /**< \brief (TC0) Counter Value (channel = 0) */ |
| 6648 | #define REG_TC0_RA0 REG_ACCESS(RwReg, 0x40010014U) /**< \brief (TC0) Register A (channel = 0) */ |
| 6649 | #define REG_TC0_RB0 REG_ACCESS(RwReg, 0x40010018U) /**< \brief (TC0) Register B (channel = 0) */ |
| 6650 | #define REG_TC0_RC0 REG_ACCESS(RwReg, 0x4001001CU) /**< \brief (TC0) Register C (channel = 0) */ |
| 6651 | #define REG_TC0_SR0 REG_ACCESS(RoReg, 0x40010020U) /**< \brief (TC0) Status Register (channel = 0) */ |
| 6652 | #define REG_TC0_IER0 REG_ACCESS(WoReg, 0x40010024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */ |
| 6653 | #define REG_TC0_IDR0 REG_ACCESS(WoReg, 0x40010028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */ |
| 6654 | #define REG_TC0_IMR0 REG_ACCESS(RoReg, 0x4001002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */ |
| 6655 | #define REG_TC0_CCR1 REG_ACCESS(WoReg, 0x40010040U) /**< \brief (TC0) Channel Control Register (channel = 1) */ |
| 6656 | #define REG_TC0_CMR1 REG_ACCESS(RwReg, 0x40010044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */ |
| 6657 | #define REG_TC0_SMMR1 REG_ACCESS(RwReg, 0x40010048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */ |
| 6658 | #define REG_TC0_CV1 REG_ACCESS(RoReg, 0x40010050U) /**< \brief (TC0) Counter Value (channel = 1) */ |
| 6659 | #define REG_TC0_RA1 REG_ACCESS(RwReg, 0x40010054U) /**< \brief (TC0) Register A (channel = 1) */ |
| 6660 | #define REG_TC0_RB1 REG_ACCESS(RwReg, 0x40010058U) /**< \brief (TC0) Register B (channel = 1) */ |
| 6661 | #define REG_TC0_RC1 REG_ACCESS(RwReg, 0x4001005CU) /**< \brief (TC0) Register C (channel = 1) */ |
| 6662 | #define REG_TC0_SR1 REG_ACCESS(RoReg, 0x40010060U) /**< \brief (TC0) Status Register (channel = 1) */ |
| 6663 | #define REG_TC0_IER1 REG_ACCESS(WoReg, 0x40010064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */ |
| 6664 | #define REG_TC0_IDR1 REG_ACCESS(WoReg, 0x40010068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */ |
| 6665 | #define REG_TC0_IMR1 REG_ACCESS(RoReg, 0x4001006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */ |
| 6666 | #define REG_TC0_CCR2 REG_ACCESS(WoReg, 0x40010080U) /**< \brief (TC0) Channel Control Register (channel = 2) */ |
| 6667 | #define REG_TC0_CMR2 REG_ACCESS(RwReg, 0x40010084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */ |
| 6668 | #define REG_TC0_SMMR2 REG_ACCESS(RwReg, 0x40010088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */ |
| 6669 | #define REG_TC0_CV2 REG_ACCESS(RoReg, 0x40010090U) /**< \brief (TC0) Counter Value (channel = 2) */ |
| 6670 | #define REG_TC0_RA2 REG_ACCESS(RwReg, 0x40010094U) /**< \brief (TC0) Register A (channel = 2) */ |
| 6671 | #define REG_TC0_RB2 REG_ACCESS(RwReg, 0x40010098U) /**< \brief (TC0) Register B (channel = 2) */ |
| 6672 | #define REG_TC0_RC2 REG_ACCESS(RwReg, 0x4001009CU) /**< \brief (TC0) Register C (channel = 2) */ |
| 6673 | #define REG_TC0_SR2 REG_ACCESS(RoReg, 0x400100A0U) /**< \brief (TC0) Status Register (channel = 2) */ |
| 6674 | #define REG_TC0_IER2 REG_ACCESS(WoReg, 0x400100A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */ |
| 6675 | #define REG_TC0_IDR2 REG_ACCESS(WoReg, 0x400100A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */ |
| 6676 | #define REG_TC0_IMR2 REG_ACCESS(RoReg, 0x400100ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */ |
| 6677 | #define REG_TC0_BCR REG_ACCESS(WoReg, 0x400100C0U) /**< \brief (TC0) Block Control Register */ |
| 6678 | #define REG_TC0_BMR REG_ACCESS(RwReg, 0x400100C4U) /**< \brief (TC0) Block Mode Register */ |
| 6679 | #define REG_TC0_QIER REG_ACCESS(WoReg, 0x400100C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */ |
| 6680 | #define REG_TC0_QIDR REG_ACCESS(WoReg, 0x400100CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */ |
| 6681 | #define REG_TC0_QIMR REG_ACCESS(RoReg, 0x400100D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */ |
| 6682 | #define REG_TC0_QISR REG_ACCESS(RoReg, 0x400100D4U) /**< \brief (TC0) QDEC Interrupt Status Register */ |
| 6683 | #define REG_TC0_FMR REG_ACCESS(RwReg, 0x400100D8U) /**< \brief (TC0) Fault Mode Register */ |
| 6684 | #define REG_TC0_WPMR REG_ACCESS(RwReg, 0x400100E4U) /**< \brief (TC0) Write Protect Mode Register */ |
| 6685 | /* ========== Register definition for TC1 peripheral ========== */ |
| 6686 | #define REG_TC1_CCR0 REG_ACCESS(WoReg, 0x40014000U) /**< \brief (TC1) Channel Control Register (channel = 0) */ |
| 6687 | #define REG_TC1_CMR0 REG_ACCESS(RwReg, 0x40014004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */ |
| 6688 | #define REG_TC1_SMMR0 REG_ACCESS(RwReg, 0x40014008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */ |
| 6689 | #define REG_TC1_CV0 REG_ACCESS(RoReg, 0x40014010U) /**< \brief (TC1) Counter Value (channel = 0) */ |
| 6690 | #define REG_TC1_RA0 REG_ACCESS(RwReg, 0x40014014U) /**< \brief (TC1) Register A (channel = 0) */ |
| 6691 | #define REG_TC1_RB0 REG_ACCESS(RwReg, 0x40014018U) /**< \brief (TC1) Register B (channel = 0) */ |
| 6692 | #define REG_TC1_RC0 REG_ACCESS(RwReg, 0x4001401CU) /**< \brief (TC1) Register C (channel = 0) */ |
| 6693 | #define REG_TC1_SR0 REG_ACCESS(RoReg, 0x40014020U) /**< \brief (TC1) Status Register (channel = 0) */ |
| 6694 | #define REG_TC1_IER0 REG_ACCESS(WoReg, 0x40014024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */ |
| 6695 | #define REG_TC1_IDR0 REG_ACCESS(WoReg, 0x40014028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */ |
| 6696 | #define REG_TC1_IMR0 REG_ACCESS(RoReg, 0x4001402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */ |
| 6697 | #define REG_TC1_CCR1 REG_ACCESS(WoReg, 0x40014040U) /**< \brief (TC1) Channel Control Register (channel = 1) */ |
| 6698 | #define REG_TC1_CMR1 REG_ACCESS(RwReg, 0x40014044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */ |
| 6699 | #define REG_TC1_SMMR1 REG_ACCESS(RwReg, 0x40014048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */ |
| 6700 | #define REG_TC1_CV1 REG_ACCESS(RoReg, 0x40014050U) /**< \brief (TC1) Counter Value (channel = 1) */ |
| 6701 | #define REG_TC1_RA1 REG_ACCESS(RwReg, 0x40014054U) /**< \brief (TC1) Register A (channel = 1) */ |
| 6702 | #define REG_TC1_RB1 REG_ACCESS(RwReg, 0x40014058U) /**< \brief (TC1) Register B (channel = 1) */ |
| 6703 | #define REG_TC1_RC1 REG_ACCESS(RwReg, 0x4001405CU) /**< \brief (TC1) Register C (channel = 1) */ |
| 6704 | #define REG_TC1_SR1 REG_ACCESS(RoReg, 0x40014060U) /**< \brief (TC1) Status Register (channel = 1) */ |
| 6705 | #define REG_TC1_IER1 REG_ACCESS(WoReg, 0x40014064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */ |
| 6706 | #define REG_TC1_IDR1 REG_ACCESS(WoReg, 0x40014068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */ |
| 6707 | #define REG_TC1_IMR1 REG_ACCESS(RoReg, 0x4001406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */ |
| 6708 | #define REG_TC1_CCR2 REG_ACCESS(WoReg, 0x40014080U) /**< \brief (TC1) Channel Control Register (channel = 2) */ |
| 6709 | #define REG_TC1_CMR2 REG_ACCESS(RwReg, 0x40014084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */ |
| 6710 | #define REG_TC1_SMMR2 REG_ACCESS(RwReg, 0x40014088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */ |
| 6711 | #define REG_TC1_CV2 REG_ACCESS(RoReg, 0x40014090U) /**< \brief (TC1) Counter Value (channel = 2) */ |
| 6712 | #define REG_TC1_RA2 REG_ACCESS(RwReg, 0x40014094U) /**< \brief (TC1) Register A (channel = 2) */ |
| 6713 | #define REG_TC1_RB2 REG_ACCESS(RwReg, 0x40014098U) /**< \brief (TC1) Register B (channel = 2) */ |
| 6714 | #define REG_TC1_RC2 REG_ACCESS(RwReg, 0x4001409CU) /**< \brief (TC1) Register C (channel = 2) */ |
| 6715 | #define REG_TC1_SR2 REG_ACCESS(RoReg, 0x400140A0U) /**< \brief (TC1) Status Register (channel = 2) */ |
| 6716 | #define REG_TC1_IER2 REG_ACCESS(WoReg, 0x400140A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */ |
| 6717 | #define REG_TC1_IDR2 REG_ACCESS(WoReg, 0x400140A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */ |
| 6718 | #define REG_TC1_IMR2 REG_ACCESS(RoReg, 0x400140ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */ |
| 6719 | #define REG_TC1_BCR REG_ACCESS(WoReg, 0x400140C0U) /**< \brief (TC1) Block Control Register */ |
| 6720 | #define REG_TC1_BMR REG_ACCESS(RwReg, 0x400140C4U) /**< \brief (TC1) Block Mode Register */ |
| 6721 | #define REG_TC1_QIER REG_ACCESS(WoReg, 0x400140C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */ |
| 6722 | #define REG_TC1_QIDR REG_ACCESS(WoReg, 0x400140CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */ |
| 6723 | #define REG_TC1_QIMR REG_ACCESS(RoReg, 0x400140D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */ |
| 6724 | #define REG_TC1_QISR REG_ACCESS(RoReg, 0x400140D4U) /**< \brief (TC1) QDEC Interrupt Status Register */ |
| 6725 | #define REG_TC1_FMR REG_ACCESS(RwReg, 0x400140D8U) /**< \brief (TC1) Fault Mode Register */ |
| 6726 | #define REG_TC1_WPMR REG_ACCESS(RwReg, 0x400140E4U) /**< \brief (TC1) Write Protect Mode Register */ |
| 6727 | /* ========== Register definition for TWI0 peripheral ========== */ |
| 6728 | #define REG_TWI0_CR REG_ACCESS(WoReg, 0x40018000U) /**< \brief (TWI0) Control Register */ |
| 6729 | #define REG_TWI0_MMR REG_ACCESS(RwReg, 0x40018004U) /**< \brief (TWI0) Master Mode Register */ |
| 6730 | #define REG_TWI0_SMR REG_ACCESS(RwReg, 0x40018008U) /**< \brief (TWI0) Slave Mode Register */ |
| 6731 | #define REG_TWI0_IADR REG_ACCESS(RwReg, 0x4001800CU) /**< \brief (TWI0) Internal Address Register */ |
| 6732 | #define REG_TWI0_CWGR REG_ACCESS(RwReg, 0x40018010U) /**< \brief (TWI0) Clock Waveform Generator Register */ |
| 6733 | #define REG_TWI0_SR REG_ACCESS(RoReg, 0x40018020U) /**< \brief (TWI0) Status Register */ |
| 6734 | #define REG_TWI0_IER REG_ACCESS(WoReg, 0x40018024U) /**< \brief (TWI0) Interrupt Enable Register */ |
| 6735 | #define REG_TWI0_IDR REG_ACCESS(WoReg, 0x40018028U) /**< \brief (TWI0) Interrupt Disable Register */ |
| 6736 | #define REG_TWI0_IMR REG_ACCESS(RoReg, 0x4001802CU) /**< \brief (TWI0) Interrupt Mask Register */ |
| 6737 | #define REG_TWI0_RHR REG_ACCESS(RoReg, 0x40018030U) /**< \brief (TWI0) Receive Holding Register */ |
| 6738 | #define REG_TWI0_THR REG_ACCESS(WoReg, 0x40018034U) /**< \brief (TWI0) Transmit Holding Register */ |
| 6739 | #define REG_TWI0_RPR REG_ACCESS(RwReg, 0x40018100U) /**< \brief (TWI0) Receive Pointer Register */ |
| 6740 | #define REG_TWI0_RCR REG_ACCESS(RwReg, 0x40018104U) /**< \brief (TWI0) Receive Counter Register */ |
| 6741 | #define REG_TWI0_TPR REG_ACCESS(RwReg, 0x40018108U) /**< \brief (TWI0) Transmit Pointer Register */ |
| 6742 | #define REG_TWI0_TCR REG_ACCESS(RwReg, 0x4001810CU) /**< \brief (TWI0) Transmit Counter Register */ |
| 6743 | #define REG_TWI0_RNPR REG_ACCESS(RwReg, 0x40018110U) /**< \brief (TWI0) Receive Next Pointer Register */ |
| 6744 | #define REG_TWI0_RNCR REG_ACCESS(RwReg, 0x40018114U) /**< \brief (TWI0) Receive Next Counter Register */ |
| 6745 | #define REG_TWI0_TNPR REG_ACCESS(RwReg, 0x40018118U) /**< \brief (TWI0) Transmit Next Pointer Register */ |
| 6746 | #define REG_TWI0_TNCR REG_ACCESS(RwReg, 0x4001811CU) /**< \brief (TWI0) Transmit Next Counter Register */ |
| 6747 | #define REG_TWI0_PTCR REG_ACCESS(WoReg, 0x40018120U) /**< \brief (TWI0) Transfer Control Register */ |
| 6748 | #define REG_TWI0_PTSR REG_ACCESS(RoReg, 0x40018124U) /**< \brief (TWI0) Transfer Status Register */ |
| 6749 | /* ========== Register definition for TWI1 peripheral ========== */ |
| 6750 | #define REG_TWI1_CR REG_ACCESS(WoReg, 0x4001C000U) /**< \brief (TWI1) Control Register */ |
| 6751 | #define REG_TWI1_MMR REG_ACCESS(RwReg, 0x4001C004U) /**< \brief (TWI1) Master Mode Register */ |
| 6752 | #define REG_TWI1_SMR REG_ACCESS(RwReg, 0x4001C008U) /**< \brief (TWI1) Slave Mode Register */ |
| 6753 | #define REG_TWI1_IADR REG_ACCESS(RwReg, 0x4001C00CU) /**< \brief (TWI1) Internal Address Register */ |
| 6754 | #define REG_TWI1_CWGR REG_ACCESS(RwReg, 0x4001C010U) /**< \brief (TWI1) Clock Waveform Generator Register */ |
| 6755 | #define REG_TWI1_SR REG_ACCESS(RoReg, 0x4001C020U) /**< \brief (TWI1) Status Register */ |
| 6756 | #define REG_TWI1_IER REG_ACCESS(WoReg, 0x4001C024U) /**< \brief (TWI1) Interrupt Enable Register */ |
| 6757 | #define REG_TWI1_IDR REG_ACCESS(WoReg, 0x4001C028U) /**< \brief (TWI1) Interrupt Disable Register */ |
| 6758 | #define REG_TWI1_IMR REG_ACCESS(RoReg, 0x4001C02CU) /**< \brief (TWI1) Interrupt Mask Register */ |
| 6759 | #define REG_TWI1_RHR REG_ACCESS(RoReg, 0x4001C030U) /**< \brief (TWI1) Receive Holding Register */ |
| 6760 | #define REG_TWI1_THR REG_ACCESS(WoReg, 0x4001C034U) /**< \brief (TWI1) Transmit Holding Register */ |
| 6761 | #define REG_TWI1_RPR REG_ACCESS(RwReg, 0x4001C100U) /**< \brief (TWI1) Receive Pointer Register */ |
| 6762 | #define REG_TWI1_RCR REG_ACCESS(RwReg, 0x4001C104U) /**< \brief (TWI1) Receive Counter Register */ |
| 6763 | #define REG_TWI1_TPR REG_ACCESS(RwReg, 0x4001C108U) /**< \brief (TWI1) Transmit Pointer Register */ |
| 6764 | #define REG_TWI1_TCR REG_ACCESS(RwReg, 0x4001C10CU) /**< \brief (TWI1) Transmit Counter Register */ |
| 6765 | #define REG_TWI1_RNPR REG_ACCESS(RwReg, 0x4001C110U) /**< \brief (TWI1) Receive Next Pointer Register */ |
| 6766 | #define REG_TWI1_RNCR REG_ACCESS(RwReg, 0x4001C114U) /**< \brief (TWI1) Receive Next Counter Register */ |
| 6767 | #define REG_TWI1_TNPR REG_ACCESS(RwReg, 0x4001C118U) /**< \brief (TWI1) Transmit Next Pointer Register */ |
| 6768 | #define REG_TWI1_TNCR REG_ACCESS(RwReg, 0x4001C11CU) /**< \brief (TWI1) Transmit Next Counter Register */ |
| 6769 | #define REG_TWI1_PTCR REG_ACCESS(WoReg, 0x4001C120U) /**< \brief (TWI1) Transfer Control Register */ |
| 6770 | #define REG_TWI1_PTSR REG_ACCESS(RoReg, 0x4001C124U) /**< \brief (TWI1) Transfer Status Register */ |
| 6771 | /* ========== Register definition for PWM peripheral ========== */ |
| 6772 | #define REG_PWM_CLK REG_ACCESS(RwReg, 0x40020000U) /**< \brief (PWM) PWM Clock Register */ |
| 6773 | #define REG_PWM_ENA REG_ACCESS(WoReg, 0x40020004U) /**< \brief (PWM) PWM Enable Register */ |
| 6774 | #define REG_PWM_DIS REG_ACCESS(WoReg, 0x40020008U) /**< \brief (PWM) PWM Disable Register */ |
| 6775 | #define REG_PWM_SR REG_ACCESS(RoReg, 0x4002000CU) /**< \brief (PWM) PWM Status Register */ |
| 6776 | #define REG_PWM_IER1 REG_ACCESS(WoReg, 0x40020010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */ |
| 6777 | #define REG_PWM_IDR1 REG_ACCESS(WoReg, 0x40020014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */ |
| 6778 | #define REG_PWM_IMR1 REG_ACCESS(RoReg, 0x40020018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */ |
| 6779 | #define REG_PWM_ISR1 REG_ACCESS(RoReg, 0x4002001CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */ |
| 6780 | #define REG_PWM_SCM REG_ACCESS(RwReg, 0x40020020U) /**< \brief (PWM) PWM Sync Channels Mode Register */ |
| 6781 | #define REG_PWM_SCUC REG_ACCESS(RwReg, 0x40020028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */ |
| 6782 | #define REG_PWM_SCUP REG_ACCESS(RwReg, 0x4002002CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */ |
| 6783 | #define REG_PWM_SCUPUPD REG_ACCESS(WoReg, 0x40020030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */ |
| 6784 | #define REG_PWM_IER2 REG_ACCESS(WoReg, 0x40020034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */ |
| 6785 | #define REG_PWM_IDR2 REG_ACCESS(WoReg, 0x40020038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */ |
| 6786 | #define REG_PWM_IMR2 REG_ACCESS(RoReg, 0x4002003CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */ |
| 6787 | #define REG_PWM_ISR2 REG_ACCESS(RoReg, 0x40020040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */ |
| 6788 | #define REG_PWM_OOV REG_ACCESS(RwReg, 0x40020044U) /**< \brief (PWM) PWM Output Override Value Register */ |
| 6789 | #define REG_PWM_OS REG_ACCESS(RwReg, 0x40020048U) /**< \brief (PWM) PWM Output Selection Register */ |
| 6790 | #define REG_PWM_OSS REG_ACCESS(WoReg, 0x4002004CU) /**< \brief (PWM) PWM Output Selection Set Register */ |
| 6791 | #define REG_PWM_OSC REG_ACCESS(WoReg, 0x40020050U) /**< \brief (PWM) PWM Output Selection Clear Register */ |
| 6792 | #define REG_PWM_OSSUPD REG_ACCESS(WoReg, 0x40020054U) /**< \brief (PWM) PWM Output Selection Set Update Register */ |
| 6793 | #define REG_PWM_OSCUPD REG_ACCESS(WoReg, 0x40020058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */ |
| 6794 | #define REG_PWM_FMR REG_ACCESS(RwReg, 0x4002005CU) /**< \brief (PWM) PWM Fault Mode Register */ |
| 6795 | #define REG_PWM_FSR REG_ACCESS(RoReg, 0x40020060U) /**< \brief (PWM) PWM Fault Status Register */ |
| 6796 | #define REG_PWM_FCR REG_ACCESS(WoReg, 0x40020064U) /**< \brief (PWM) PWM Fault Clear Register */ |
| 6797 | #define REG_PWM_FPV REG_ACCESS(RwReg, 0x40020068U) /**< \brief (PWM) PWM Fault Protection Value Register */ |
| 6798 | #define REG_PWM_FPE REG_ACCESS(RwReg, 0x4002006CU) /**< \brief (PWM) PWM Fault Protection Enable Register */ |
| 6799 | #define REG_PWM_EL0MR REG_ACCESS(RwReg, 0x4002007CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */ |
| 6800 | #define REG_PWM_EL1MR REG_ACCESS(RwReg, 0x40020080U) /**< \brief (PWM) PWM Event Line 1 Mode Register */ |
| 6801 | #define REG_PWM_SMMR REG_ACCESS(RwReg, 0x400200B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */ |
| 6802 | #define REG_PWM_WPCR REG_ACCESS(WoReg, 0x400200E4U) /**< \brief (PWM) PWM Write Protect Control Register */ |
| 6803 | #define REG_PWM_WPSR REG_ACCESS(RoReg, 0x400200E8U) /**< \brief (PWM) PWM Write Protect Status Register */ |
| 6804 | #define REG_PWM_RPR REG_ACCESS(RwReg, 0x40020100U) /**< \brief (PWM) Receive Pointer Register */ |
| 6805 | #define REG_PWM_RCR REG_ACCESS(RwReg, 0x40020104U) /**< \brief (PWM) Receive Counter Register */ |
| 6806 | #define REG_PWM_TPR REG_ACCESS(RwReg, 0x40020108U) /**< \brief (PWM) Transmit Pointer Register */ |
| 6807 | #define REG_PWM_TCR REG_ACCESS(RwReg, 0x4002010CU) /**< \brief (PWM) Transmit Counter Register */ |
| 6808 | #define REG_PWM_RNPR REG_ACCESS(RwReg, 0x40020110U) /**< \brief (PWM) Receive Next Pointer Register */ |
| 6809 | #define REG_PWM_RNCR REG_ACCESS(RwReg, 0x40020114U) /**< \brief (PWM) Receive Next Counter Register */ |
| 6810 | #define REG_PWM_TNPR REG_ACCESS(RwReg, 0x40020118U) /**< \brief (PWM) Transmit Next Pointer Register */ |
| 6811 | #define REG_PWM_TNCR REG_ACCESS(RwReg, 0x4002011CU) /**< \brief (PWM) Transmit Next Counter Register */ |
| 6812 | #define REG_PWM_PTCR REG_ACCESS(WoReg, 0x40020120U) /**< \brief (PWM) Transfer Control Register */ |
| 6813 | #define REG_PWM_PTSR REG_ACCESS(RoReg, 0x40020124U) /**< \brief (PWM) Transfer Status Register */ |
| 6814 | #define REG_PWM_CMP0V REG_ACCESS(RwReg, 0x40020130U) /**< \brief (PWM) PWM Comparison 0 Value Register */ |
| 6815 | #define REG_PWM_CMP0VUPD REG_ACCESS(WoReg, 0x40020134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */ |
| 6816 | #define REG_PWM_CMP0M REG_ACCESS(RwReg, 0x40020138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */ |
| 6817 | #define REG_PWM_CMP0MUPD REG_ACCESS(WoReg, 0x4002013CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */ |
| 6818 | #define REG_PWM_CMP1V REG_ACCESS(RwReg, 0x40020140U) /**< \brief (PWM) PWM Comparison 1 Value Register */ |
| 6819 | #define REG_PWM_CMP1VUPD REG_ACCESS(WoReg, 0x40020144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */ |
| 6820 | #define REG_PWM_CMP1M REG_ACCESS(RwReg, 0x40020148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */ |
| 6821 | #define REG_PWM_CMP1MUPD REG_ACCESS(WoReg, 0x4002014CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */ |
| 6822 | #define REG_PWM_CMP2V REG_ACCESS(RwReg, 0x40020150U) /**< \brief (PWM) PWM Comparison 2 Value Register */ |
| 6823 | #define REG_PWM_CMP2VUPD REG_ACCESS(WoReg, 0x40020154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */ |
| 6824 | #define REG_PWM_CMP2M REG_ACCESS(RwReg, 0x40020158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */ |
| 6825 | #define REG_PWM_CMP2MUPD REG_ACCESS(WoReg, 0x4002015CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */ |
| 6826 | #define REG_PWM_CMP3V REG_ACCESS(RwReg, 0x40020160U) /**< \brief (PWM) PWM Comparison 3 Value Register */ |
| 6827 | #define REG_PWM_CMP3VUPD REG_ACCESS(WoReg, 0x40020164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */ |
| 6828 | #define REG_PWM_CMP3M REG_ACCESS(RwReg, 0x40020168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */ |
| 6829 | #define REG_PWM_CMP3MUPD REG_ACCESS(WoReg, 0x4002016CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */ |
| 6830 | #define REG_PWM_CMP4V REG_ACCESS(RwReg, 0x40020170U) /**< \brief (PWM) PWM Comparison 4 Value Register */ |
| 6831 | #define REG_PWM_CMP4VUPD REG_ACCESS(WoReg, 0x40020174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */ |
| 6832 | #define REG_PWM_CMP4M REG_ACCESS(RwReg, 0x40020178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */ |
| 6833 | #define REG_PWM_CMP4MUPD REG_ACCESS(WoReg, 0x4002017CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */ |
| 6834 | #define REG_PWM_CMP5V REG_ACCESS(RwReg, 0x40020180U) /**< \brief (PWM) PWM Comparison 5 Value Register */ |
| 6835 | #define REG_PWM_CMP5VUPD REG_ACCESS(WoReg, 0x40020184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */ |
| 6836 | #define REG_PWM_CMP5M REG_ACCESS(RwReg, 0x40020188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */ |
| 6837 | #define REG_PWM_CMP5MUPD REG_ACCESS(WoReg, 0x4002018CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */ |
| 6838 | #define REG_PWM_CMP6V REG_ACCESS(RwReg, 0x40020190U) /**< \brief (PWM) PWM Comparison 6 Value Register */ |
| 6839 | #define REG_PWM_CMP6VUPD REG_ACCESS(WoReg, 0x40020194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */ |
| 6840 | #define REG_PWM_CMP6M REG_ACCESS(RwReg, 0x40020198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */ |
| 6841 | #define REG_PWM_CMP6MUPD REG_ACCESS(WoReg, 0x4002019CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */ |
| 6842 | #define REG_PWM_CMP7V REG_ACCESS(RwReg, 0x400201A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */ |
| 6843 | #define REG_PWM_CMP7VUPD REG_ACCESS(WoReg, 0x400201A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */ |
| 6844 | #define REG_PWM_CMP7M REG_ACCESS(RwReg, 0x400201A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */ |
| 6845 | #define REG_PWM_CMP7MUPD REG_ACCESS(WoReg, 0x400201ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */ |
| 6846 | #define REG_PWM_CMR0 REG_ACCESS(RwReg, 0x40020200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */ |
| 6847 | #define REG_PWM_CDTY0 REG_ACCESS(RwReg, 0x40020204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */ |
| 6848 | #define REG_PWM_CDTYUPD0 REG_ACCESS(WoReg, 0x40020208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */ |
| 6849 | #define REG_PWM_CPRD0 REG_ACCESS(RwReg, 0x4002020CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */ |
| 6850 | #define REG_PWM_CPRDUPD0 REG_ACCESS(WoReg, 0x40020210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */ |
| 6851 | #define REG_PWM_CCNT0 REG_ACCESS(RoReg, 0x40020214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */ |
| 6852 | #define REG_PWM_DT0 REG_ACCESS(RwReg, 0x40020218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */ |
| 6853 | #define REG_PWM_DTUPD0 REG_ACCESS(WoReg, 0x4002021CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */ |
| 6854 | #define REG_PWM_CMR1 REG_ACCESS(RwReg, 0x40020220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */ |
| 6855 | #define REG_PWM_CDTY1 REG_ACCESS(RwReg, 0x40020224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */ |
| 6856 | #define REG_PWM_CDTYUPD1 REG_ACCESS(WoReg, 0x40020228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */ |
| 6857 | #define REG_PWM_CPRD1 REG_ACCESS(RwReg, 0x4002022CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */ |
| 6858 | #define REG_PWM_CPRDUPD1 REG_ACCESS(WoReg, 0x40020230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */ |
| 6859 | #define REG_PWM_CCNT1 REG_ACCESS(RoReg, 0x40020234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */ |
| 6860 | #define REG_PWM_DT1 REG_ACCESS(RwReg, 0x40020238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */ |
| 6861 | #define REG_PWM_DTUPD1 REG_ACCESS(WoReg, 0x4002023CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */ |
| 6862 | #define REG_PWM_CMR2 REG_ACCESS(RwReg, 0x40020240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */ |
| 6863 | #define REG_PWM_CDTY2 REG_ACCESS(RwReg, 0x40020244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */ |
| 6864 | #define REG_PWM_CDTYUPD2 REG_ACCESS(WoReg, 0x40020248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */ |
| 6865 | #define REG_PWM_CPRD2 REG_ACCESS(RwReg, 0x4002024CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */ |
| 6866 | #define REG_PWM_CPRDUPD2 REG_ACCESS(WoReg, 0x40020250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */ |
| 6867 | #define REG_PWM_CCNT2 REG_ACCESS(RoReg, 0x40020254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */ |
| 6868 | #define REG_PWM_DT2 REG_ACCESS(RwReg, 0x40020258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */ |
| 6869 | #define REG_PWM_DTUPD2 REG_ACCESS(WoReg, 0x4002025CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */ |
| 6870 | #define REG_PWM_CMR3 REG_ACCESS(RwReg, 0x40020260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */ |
| 6871 | #define REG_PWM_CDTY3 REG_ACCESS(RwReg, 0x40020264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */ |
| 6872 | #define REG_PWM_CDTYUPD3 REG_ACCESS(WoReg, 0x40020268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */ |
| 6873 | #define REG_PWM_CPRD3 REG_ACCESS(RwReg, 0x4002026CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */ |
| 6874 | #define REG_PWM_CPRDUPD3 REG_ACCESS(WoReg, 0x40020270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */ |
| 6875 | #define REG_PWM_CCNT3 REG_ACCESS(RoReg, 0x40020274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */ |
| 6876 | #define REG_PWM_DT3 REG_ACCESS(RwReg, 0x40020278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */ |
| 6877 | #define REG_PWM_DTUPD3 REG_ACCESS(WoReg, 0x4002027CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */ |
| 6878 | /* ========== Register definition for USART0 peripheral ========== */ |
| 6879 | #define REG_USART0_CR REG_ACCESS(WoReg, 0x40024000U) /**< \brief (USART0) Control Register */ |
| 6880 | #define REG_USART0_MR REG_ACCESS(RwReg, 0x40024004U) /**< \brief (USART0) Mode Register */ |
| 6881 | #define REG_USART0_IER REG_ACCESS(WoReg, 0x40024008U) /**< \brief (USART0) Interrupt Enable Register */ |
| 6882 | #define REG_USART0_IDR REG_ACCESS(WoReg, 0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */ |
| 6883 | #define REG_USART0_IMR REG_ACCESS(RoReg, 0x40024010U) /**< \brief (USART0) Interrupt Mask Register */ |
| 6884 | #define REG_USART0_CSR REG_ACCESS(RoReg, 0x40024014U) /**< \brief (USART0) Channel Status Register */ |
| 6885 | #define REG_USART0_RHR REG_ACCESS(RoReg, 0x40024018U) /**< \brief (USART0) Receiver Holding Register */ |
| 6886 | #define REG_USART0_THR REG_ACCESS(WoReg, 0x4002401CU) /**< \brief (USART0) Transmitter Holding Register */ |
| 6887 | #define REG_USART0_BRGR REG_ACCESS(RwReg, 0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */ |
| 6888 | #define REG_USART0_RTOR REG_ACCESS(RwReg, 0x40024024U) /**< \brief (USART0) Receiver Time-out Register */ |
| 6889 | #define REG_USART0_TTGR REG_ACCESS(RwReg, 0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */ |
| 6890 | #define REG_USART0_FIDI REG_ACCESS(RwReg, 0x40024040U) /**< \brief (USART0) FI DI Ratio Register */ |
| 6891 | #define REG_USART0_NER REG_ACCESS(RoReg, 0x40024044U) /**< \brief (USART0) Number of Errors Register */ |
| 6892 | #define REG_USART0_IF REG_ACCESS(RwReg, 0x4002404CU) /**< \brief (USART0) IrDA Filter Register */ |
| 6893 | #define REG_USART0_MAN REG_ACCESS(RwReg, 0x40024050U) /**< \brief (USART0) Manchester Encoder Decoder Register */ |
| 6894 | #define REG_USART0_WPMR REG_ACCESS(RwReg, 0x400240E4U) /**< \brief (USART0) Write Protect Mode Register */ |
| 6895 | #define REG_USART0_WPSR REG_ACCESS(RoReg, 0x400240E8U) /**< \brief (USART0) Write Protect Status Register */ |
| 6896 | #define REG_USART0_RPR REG_ACCESS(RwReg, 0x40024100U) /**< \brief (USART0) Receive Pointer Register */ |
| 6897 | #define REG_USART0_RCR REG_ACCESS(RwReg, 0x40024104U) /**< \brief (USART0) Receive Counter Register */ |
| 6898 | #define REG_USART0_TPR REG_ACCESS(RwReg, 0x40024108U) /**< \brief (USART0) Transmit Pointer Register */ |
| 6899 | #define REG_USART0_TCR REG_ACCESS(RwReg, 0x4002410CU) /**< \brief (USART0) Transmit Counter Register */ |
| 6900 | #define REG_USART0_RNPR REG_ACCESS(RwReg, 0x40024110U) /**< \brief (USART0) Receive Next Pointer Register */ |
| 6901 | #define REG_USART0_RNCR REG_ACCESS(RwReg, 0x40024114U) /**< \brief (USART0) Receive Next Counter Register */ |
| 6902 | #define REG_USART0_TNPR REG_ACCESS(RwReg, 0x40024118U) /**< \brief (USART0) Transmit Next Pointer Register */ |
| 6903 | #define REG_USART0_TNCR REG_ACCESS(RwReg, 0x4002411CU) /**< \brief (USART0) Transmit Next Counter Register */ |
| 6904 | #define REG_USART0_PTCR REG_ACCESS(WoReg, 0x40024120U) /**< \brief (USART0) Transfer Control Register */ |
| 6905 | #define REG_USART0_PTSR REG_ACCESS(RoReg, 0x40024124U) /**< \brief (USART0) Transfer Status Register */ |
| 6906 | /* ========== Register definition for USART1 peripheral ========== */ |
| 6907 | #define REG_USART1_CR REG_ACCESS(WoReg, 0x40028000U) /**< \brief (USART1) Control Register */ |
| 6908 | #define REG_USART1_MR REG_ACCESS(RwReg, 0x40028004U) /**< \brief (USART1) Mode Register */ |
| 6909 | #define REG_USART1_IER REG_ACCESS(WoReg, 0x40028008U) /**< \brief (USART1) Interrupt Enable Register */ |
| 6910 | #define REG_USART1_IDR REG_ACCESS(WoReg, 0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */ |
| 6911 | #define REG_USART1_IMR REG_ACCESS(RoReg, 0x40028010U) /**< \brief (USART1) Interrupt Mask Register */ |
| 6912 | #define REG_USART1_CSR REG_ACCESS(RoReg, 0x40028014U) /**< \brief (USART1) Channel Status Register */ |
| 6913 | #define REG_USART1_RHR REG_ACCESS(RoReg, 0x40028018U) /**< \brief (USART1) Receiver Holding Register */ |
| 6914 | #define REG_USART1_THR REG_ACCESS(WoReg, 0x4002801CU) /**< \brief (USART1) Transmitter Holding Register */ |
| 6915 | #define REG_USART1_BRGR REG_ACCESS(RwReg, 0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */ |
| 6916 | #define REG_USART1_RTOR REG_ACCESS(RwReg, 0x40028024U) /**< \brief (USART1) Receiver Time-out Register */ |
| 6917 | #define REG_USART1_TTGR REG_ACCESS(RwReg, 0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */ |
| 6918 | #define REG_USART1_FIDI REG_ACCESS(RwReg, 0x40028040U) /**< \brief (USART1) FI DI Ratio Register */ |
| 6919 | #define REG_USART1_NER REG_ACCESS(RoReg, 0x40028044U) /**< \brief (USART1) Number of Errors Register */ |
| 6920 | #define REG_USART1_IF REG_ACCESS(RwReg, 0x4002804CU) /**< \brief (USART1) IrDA Filter Register */ |
| 6921 | #define REG_USART1_MAN REG_ACCESS(RwReg, 0x40028050U) /**< \brief (USART1) Manchester Encoder Decoder Register */ |
| 6922 | #define REG_USART1_WPMR REG_ACCESS(RwReg, 0x400280E4U) /**< \brief (USART1) Write Protect Mode Register */ |
| 6923 | #define REG_USART1_WPSR REG_ACCESS(RoReg, 0x400280E8U) /**< \brief (USART1) Write Protect Status Register */ |
| 6924 | #define REG_USART1_RPR REG_ACCESS(RwReg, 0x40028100U) /**< \brief (USART1) Receive Pointer Register */ |
| 6925 | #define REG_USART1_RCR REG_ACCESS(RwReg, 0x40028104U) /**< \brief (USART1) Receive Counter Register */ |
| 6926 | #define REG_USART1_TPR REG_ACCESS(RwReg, 0x40028108U) /**< \brief (USART1) Transmit Pointer Register */ |
| 6927 | #define REG_USART1_TCR REG_ACCESS(RwReg, 0x4002810CU) /**< \brief (USART1) Transmit Counter Register */ |
| 6928 | #define REG_USART1_RNPR REG_ACCESS(RwReg, 0x40028110U) /**< \brief (USART1) Receive Next Pointer Register */ |
| 6929 | #define REG_USART1_RNCR REG_ACCESS(RwReg, 0x40028114U) /**< \brief (USART1) Receive Next Counter Register */ |
| 6930 | #define REG_USART1_TNPR REG_ACCESS(RwReg, 0x40028118U) /**< \brief (USART1) Transmit Next Pointer Register */ |
| 6931 | #define REG_USART1_TNCR REG_ACCESS(RwReg, 0x4002811CU) /**< \brief (USART1) Transmit Next Counter Register */ |
| 6932 | #define REG_USART1_PTCR REG_ACCESS(WoReg, 0x40028120U) /**< \brief (USART1) Transfer Control Register */ |
| 6933 | #define REG_USART1_PTSR REG_ACCESS(RoReg, 0x40028124U) /**< \brief (USART1) Transfer Status Register */ |
| 6934 | /* ========== Register definition for UDP peripheral ========== */ |
| 6935 | #define REG_UDP_FRM_NUM REG_ACCESS(RoReg, 0x40034000U) /**< \brief (UDP) Frame Number Register */ |
| 6936 | #define REG_UDP_GLB_STAT REG_ACCESS(RwReg, 0x40034004U) /**< \brief (UDP) Global State Register */ |
| 6937 | #define REG_UDP_FADDR REG_ACCESS(RwReg, 0x40034008U) /**< \brief (UDP) Function Address Register */ |
| 6938 | #define REG_UDP_IER REG_ACCESS(WoReg, 0x40034010U) /**< \brief (UDP) Interrupt Enable Register */ |
| 6939 | #define REG_UDP_IDR REG_ACCESS(WoReg, 0x40034014U) /**< \brief (UDP) Interrupt Disable Register */ |
| 6940 | #define REG_UDP_IMR REG_ACCESS(RoReg, 0x40034018U) /**< \brief (UDP) Interrupt Mask Register */ |
| 6941 | #define REG_UDP_ISR REG_ACCESS(RoReg, 0x4003401CU) /**< \brief (UDP) Interrupt Status Register */ |
| 6942 | #define REG_UDP_ICR REG_ACCESS(WoReg, 0x40034020U) /**< \brief (UDP) Interrupt Clear Register */ |
| 6943 | #define REG_UDP_RST_EP REG_ACCESS(RwReg, 0x40034028U) /**< \brief (UDP) Reset Endpoint Register */ |
| 6944 | #define REG_UDP_CSR REG_ACCESS(RwReg, 0x40034030U) /**< \brief (UDP) Endpoint Control and Status Register */ |
| 6945 | #define REG_UDP_FDR REG_ACCESS(RwReg, 0x40034050U) /**< \brief (UDP) Endpoint FIFO Data Register */ |
| 6946 | #define REG_UDP_TXVC REG_ACCESS(RwReg, 0x40034074U) /**< \brief (UDP) Transceiver Control Register */ |
| 6947 | /* ========== Register definition for ADC peripheral ========== */ |
| 6948 | #define REG_ADC_CR REG_ACCESS(WoReg, 0x40038000U) /**< \brief (ADC) Control Register */ |
| 6949 | #define REG_ADC_MR REG_ACCESS(RwReg, 0x40038004U) /**< \brief (ADC) Mode Register */ |
| 6950 | #define REG_ADC_SEQR1 REG_ACCESS(RwReg, 0x40038008U) /**< \brief (ADC) Channel Sequence Register 1 */ |
| 6951 | #define REG_ADC_SEQR2 REG_ACCESS(RwReg, 0x4003800CU) /**< \brief (ADC) Channel Sequence Register 2 */ |
| 6952 | #define REG_ADC_CHER REG_ACCESS(WoReg, 0x40038010U) /**< \brief (ADC) Channel Enable Register */ |
| 6953 | #define REG_ADC_CHDR REG_ACCESS(WoReg, 0x40038014U) /**< \brief (ADC) Channel Disable Register */ |
| 6954 | #define REG_ADC_CHSR REG_ACCESS(RoReg, 0x40038018U) /**< \brief (ADC) Channel Status Register */ |
| 6955 | #define REG_ADC_LCDR REG_ACCESS(RoReg, 0x40038020U) /**< \brief (ADC) Last Converted Data Register */ |
| 6956 | #define REG_ADC_IER REG_ACCESS(WoReg, 0x40038024U) /**< \brief (ADC) Interrupt Enable Register */ |
| 6957 | #define REG_ADC_IDR REG_ACCESS(WoReg, 0x40038028U) /**< \brief (ADC) Interrupt Disable Register */ |
| 6958 | #define REG_ADC_IMR REG_ACCESS(RoReg, 0x4003802CU) /**< \brief (ADC) Interrupt Mask Register */ |
| 6959 | #define REG_ADC_ISR REG_ACCESS(RoReg, 0x40038030U) /**< \brief (ADC) Interrupt Status Register */ |
| 6960 | #define REG_ADC_OVER REG_ACCESS(RoReg, 0x4003803CU) /**< \brief (ADC) Overrun Status Register */ |
| 6961 | #define REG_ADC_EMR REG_ACCESS(RwReg, 0x40038040U) /**< \brief (ADC) Extended Mode Register */ |
| 6962 | #define REG_ADC_CWR REG_ACCESS(RwReg, 0x40038044U) /**< \brief (ADC) Compare Window Register */ |
| 6963 | #define REG_ADC_CGR REG_ACCESS(RwReg, 0x40038048U) /**< \brief (ADC) Channel Gain Register */ |
| 6964 | #define REG_ADC_COR REG_ACCESS(RwReg, 0x4003804CU) /**< \brief (ADC) Channel Offset Register */ |
| 6965 | #define REG_ADC_CDR REG_ACCESS(RoReg, 0x40038050U) /**< \brief (ADC) Channel Data Register */ |
| 6966 | #define REG_ADC_ACR REG_ACCESS(RwReg, 0x40038094U) /**< \brief (ADC) Analog Control Register */ |
| 6967 | #define REG_ADC_WPMR REG_ACCESS(RwReg, 0x400380E4U) /**< \brief (ADC) Write Protect Mode Register */ |
| 6968 | #define REG_ADC_WPSR REG_ACCESS(RoReg, 0x400380E8U) /**< \brief (ADC) Write Protect Status Register */ |
| 6969 | #define REG_ADC_RPR REG_ACCESS(RwReg, 0x40038100U) /**< \brief (ADC) Receive Pointer Register */ |
| 6970 | #define REG_ADC_RCR REG_ACCESS(RwReg, 0x40038104U) /**< \brief (ADC) Receive Counter Register */ |
| 6971 | #define REG_ADC_TPR REG_ACCESS(RwReg, 0x40038108U) /**< \brief (ADC) Transmit Pointer Register */ |
| 6972 | #define REG_ADC_TCR REG_ACCESS(RwReg, 0x4003810CU) /**< \brief (ADC) Transmit Counter Register */ |
| 6973 | #define REG_ADC_RNPR REG_ACCESS(RwReg, 0x40038110U) /**< \brief (ADC) Receive Next Pointer Register */ |
| 6974 | #define REG_ADC_RNCR REG_ACCESS(RwReg, 0x40038114U) /**< \brief (ADC) Receive Next Counter Register */ |
| 6975 | #define REG_ADC_TNPR REG_ACCESS(RwReg, 0x40038118U) /**< \brief (ADC) Transmit Next Pointer Register */ |
| 6976 | #define REG_ADC_TNCR REG_ACCESS(RwReg, 0x4003811CU) /**< \brief (ADC) Transmit Next Counter Register */ |
| 6977 | #define REG_ADC_PTCR REG_ACCESS(WoReg, 0x40038120U) /**< \brief (ADC) Transfer Control Register */ |
| 6978 | #define REG_ADC_PTSR REG_ACCESS(RoReg, 0x40038124U) /**< \brief (ADC) Transfer Status Register */ |
| 6979 | /* ========== Register definition for DACC peripheral ========== */ |
| 6980 | #define REG_DACC_CR REG_ACCESS(WoReg, 0x4003C000U) /**< \brief (DACC) Control Register */ |
| 6981 | #define REG_DACC_MR REG_ACCESS(RwReg, 0x4003C004U) /**< \brief (DACC) Mode Register */ |
| 6982 | #define REG_DACC_CHER REG_ACCESS(WoReg, 0x4003C010U) /**< \brief (DACC) Channel Enable Register */ |
| 6983 | #define REG_DACC_CHDR REG_ACCESS(WoReg, 0x4003C014U) /**< \brief (DACC) Channel Disable Register */ |
| 6984 | #define REG_DACC_CHSR REG_ACCESS(RoReg, 0x4003C018U) /**< \brief (DACC) Channel Status Register */ |
| 6985 | #define REG_DACC_CDR REG_ACCESS(WoReg, 0x4003C020U) /**< \brief (DACC) Conversion Data Register */ |
| 6986 | #define REG_DACC_IER REG_ACCESS(WoReg, 0x4003C024U) /**< \brief (DACC) Interrupt Enable Register */ |
| 6987 | #define REG_DACC_IDR REG_ACCESS(WoReg, 0x4003C028U) /**< \brief (DACC) Interrupt Disable Register */ |
| 6988 | #define REG_DACC_IMR REG_ACCESS(RoReg, 0x4003C02CU) /**< \brief (DACC) Interrupt Mask Register */ |
| 6989 | #define REG_DACC_ISR REG_ACCESS(RoReg, 0x4003C030U) /**< \brief (DACC) Interrupt Status Register */ |
| 6990 | #define REG_DACC_ACR REG_ACCESS(RwReg, 0x4003C094U) /**< \brief (DACC) Analog Current Register */ |
| 6991 | #define REG_DACC_WPMR REG_ACCESS(RwReg, 0x4003C0E4U) /**< \brief (DACC) Write Protect Mode register */ |
| 6992 | #define REG_DACC_WPSR REG_ACCESS(RoReg, 0x4003C0E8U) /**< \brief (DACC) Write Protect Status register */ |
| 6993 | #define REG_DACC_RPR REG_ACCESS(RwReg, 0x4003C100U) /**< \brief (DACC) Receive Pointer Register */ |
| 6994 | #define REG_DACC_RCR REG_ACCESS(RwReg, 0x4003C104U) /**< \brief (DACC) Receive Counter Register */ |
| 6995 | #define REG_DACC_TPR REG_ACCESS(RwReg, 0x4003C108U) /**< \brief (DACC) Transmit Pointer Register */ |
| 6996 | #define REG_DACC_TCR REG_ACCESS(RwReg, 0x4003C10CU) /**< \brief (DACC) Transmit Counter Register */ |
| 6997 | #define REG_DACC_RNPR REG_ACCESS(RwReg, 0x4003C110U) /**< \brief (DACC) Receive Next Pointer Register */ |
| 6998 | #define REG_DACC_RNCR REG_ACCESS(RwReg, 0x4003C114U) /**< \brief (DACC) Receive Next Counter Register */ |
| 6999 | #define REG_DACC_TNPR REG_ACCESS(RwReg, 0x4003C118U) /**< \brief (DACC) Transmit Next Pointer Register */ |
| 7000 | #define REG_DACC_TNCR REG_ACCESS(RwReg, 0x4003C11CU) /**< \brief (DACC) Transmit Next Counter Register */ |
| 7001 | #define REG_DACC_PTCR REG_ACCESS(WoReg, 0x4003C120U) /**< \brief (DACC) Transfer Control Register */ |
| 7002 | #define REG_DACC_PTSR REG_ACCESS(RoReg, 0x4003C124U) /**< \brief (DACC) Transfer Status Register */ |
| 7003 | /* ========== Register definition for ACC peripheral ========== */ |
| 7004 | #define REG_ACC_CR REG_ACCESS(WoReg, 0x40040000U) /**< \brief (ACC) Control Register */ |
| 7005 | #define REG_ACC_MR REG_ACCESS(RwReg, 0x40040004U) /**< \brief (ACC) Mode Register */ |
| 7006 | #define REG_ACC_IER REG_ACCESS(WoReg, 0x40040024U) /**< \brief (ACC) Interrupt Enable Register */ |
| 7007 | #define REG_ACC_IDR REG_ACCESS(WoReg, 0x40040028U) /**< \brief (ACC) Interrupt Disable Register */ |
| 7008 | #define REG_ACC_IMR REG_ACCESS(RoReg, 0x4004002CU) /**< \brief (ACC) Interrupt Mask Register */ |
| 7009 | #define REG_ACC_ISR REG_ACCESS(RoReg, 0x40040030U) /**< \brief (ACC) Interrupt Status Register */ |
| 7010 | #define REG_ACC_ACR REG_ACCESS(RwReg, 0x40040094U) /**< \brief (ACC) Analog Control Register */ |
| 7011 | #define REG_ACC_WPMR REG_ACCESS(RwReg, 0x400400E4U) /**< \brief (ACC) Write Protect Mode Register */ |
| 7012 | #define REG_ACC_WPSR REG_ACCESS(RoReg, 0x400400E8U) /**< \brief (ACC) Write Protect Status Register */ |
| 7013 | /* ========== Register definition for CRCCU peripheral ========== */ |
| 7014 | #define REG_CRCCU_DSCR REG_ACCESS(RwReg, 0x40044000U) /**< \brief (CRCCU) CRCCU Descriptor Base Register */ |
| 7015 | #define REG_CRCCU_DMA_EN REG_ACCESS(WoReg, 0x40044008U) /**< \brief (CRCCU) CRCCU DMA Enable Register */ |
| 7016 | #define REG_CRCCU_DMA_DIS REG_ACCESS(WoReg, 0x4004400CU) /**< \brief (CRCCU) CRCCU DMA Disable Register */ |
| 7017 | #define REG_CRCCU_DMA_SR REG_ACCESS(RoReg, 0x40044010U) /**< \brief (CRCCU) CRCCU DMA Status Register */ |
| 7018 | #define REG_CRCCU_DMA_IER REG_ACCESS(WoReg, 0x40044014U) /**< \brief (CRCCU) CRCCU DMA Interrupt Enable Register */ |
| 7019 | #define REG_CRCCU_DMA_IDR REG_ACCESS(WoReg, 0x40044018U) /**< \brief (CRCCU) CRCCU DMA Interrupt Disable Register */ |
| 7020 | #define REG_CRCCU_DMA_IMR REG_ACCESS(RoReg, 0x4004401CU) /**< \brief (CRCCU) CRCCU DMA Interrupt Mask Register */ |
| 7021 | #define REG_CRCCU_DMA_ISR REG_ACCESS(RoReg, 0x40044020U) /**< \brief (CRCCU) CRCCU DMA Interrupt Status Register */ |
| 7022 | #define REG_CRCCU_CR REG_ACCESS(WoReg, 0x40044034U) /**< \brief (CRCCU) CRCCU Control Register */ |
| 7023 | #define REG_CRCCU_MR REG_ACCESS(RwReg, 0x40044038U) /**< \brief (CRCCU) CRCCU Mode Register */ |
| 7024 | #define REG_CRCCU_SR REG_ACCESS(RoReg, 0x4004403CU) /**< \brief (CRCCU) CRCCU Status Register */ |
| 7025 | #define REG_CRCCU_IER REG_ACCESS(WoReg, 0x40044040U) /**< \brief (CRCCU) CRCCU Interrupt Enable Register */ |
| 7026 | #define REG_CRCCU_IDR REG_ACCESS(WoReg, 0x40044044U) /**< \brief (CRCCU) CRCCU Interrupt Disable Register */ |
| 7027 | #define REG_CRCCU_IMR REG_ACCESS(RoReg, 0x40044048U) /**< \brief (CRCCU) CRCCU Interrupt Mask Register */ |
| 7028 | #define REG_CRCCU_ISR REG_ACCESS(RoReg, 0x4004404CU) /**< \brief (CRCCU) CRCCU Interrupt Status Register */ |
| 7029 | /* ========== Register definition for SMC peripheral ========== */ |
| 7030 | #define REG_SMC_SETUP0 REG_ACCESS(RwReg, 0x400E0000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */ |
| 7031 | #define REG_SMC_PULSE0 REG_ACCESS(RwReg, 0x400E0004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */ |
| 7032 | #define REG_SMC_CYCLE0 REG_ACCESS(RwReg, 0x400E0008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */ |
| 7033 | #define REG_SMC_MODE0 REG_ACCESS(RwReg, 0x400E000CU) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */ |
| 7034 | #define REG_SMC_SETUP1 REG_ACCESS(RwReg, 0x400E0010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */ |
| 7035 | #define REG_SMC_PULSE1 REG_ACCESS(RwReg, 0x400E0014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */ |
| 7036 | #define REG_SMC_CYCLE1 REG_ACCESS(RwReg, 0x400E0018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */ |
| 7037 | #define REG_SMC_MODE1 REG_ACCESS(RwReg, 0x400E001CU) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */ |
| 7038 | #define REG_SMC_SETUP2 REG_ACCESS(RwReg, 0x400E0020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */ |
| 7039 | #define REG_SMC_PULSE2 REG_ACCESS(RwReg, 0x400E0024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */ |
| 7040 | #define REG_SMC_CYCLE2 REG_ACCESS(RwReg, 0x400E0028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */ |
| 7041 | #define REG_SMC_MODE2 REG_ACCESS(RwReg, 0x400E002CU) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */ |
| 7042 | #define REG_SMC_SETUP3 REG_ACCESS(RwReg, 0x400E0030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */ |
| 7043 | #define REG_SMC_PULSE3 REG_ACCESS(RwReg, 0x400E0034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */ |
| 7044 | #define REG_SMC_CYCLE3 REG_ACCESS(RwReg, 0x400E0038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */ |
| 7045 | #define REG_SMC_MODE3 REG_ACCESS(RwReg, 0x400E003CU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */ |
| 7046 | #define REG_SMC_SETUP4 REG_ACCESS(RwReg, 0x400E0040U) /**< \brief (SMC) SMC Setup Register (CS_number = 4) */ |
| 7047 | #define REG_SMC_PULSE4 REG_ACCESS(RwReg, 0x400E0044U) /**< \brief (SMC) SMC Pulse Register (CS_number = 4) */ |
| 7048 | #define REG_SMC_CYCLE4 REG_ACCESS(RwReg, 0x400E0048U) /**< \brief (SMC) SMC Cycle Register (CS_number = 4) */ |
| 7049 | #define REG_SMC_MODE4 REG_ACCESS(RwReg, 0x400E004CU) /**< \brief (SMC) SMC Mode Register (CS_number = 4) */ |
| 7050 | #define REG_SMC_OCMS REG_ACCESS(RwReg, 0x400E0080U) /**< \brief (SMC) SMC OCMS MODE Register */ |
| 7051 | #define REG_SMC_KEY1 REG_ACCESS(WoReg, 0x400E0084U) /**< \brief (SMC) SMC OCMS KEY1 Register */ |
| 7052 | #define REG_SMC_KEY2 REG_ACCESS(WoReg, 0x400E0088U) /**< \brief (SMC) SMC OCMS KEY2 Register */ |
| 7053 | #define REG_SMC_WPMR REG_ACCESS(RwReg, 0x400E00E4U) /**< \brief (SMC) SMC Write Protect Mode Register */ |
| 7054 | #define REG_SMC_WPSR REG_ACCESS(RoReg, 0x400E00E8U) /**< \brief (SMC) SMC Write Protect Status Register */ |
| 7055 | /* ========== Register definition for MATRIX peripheral ========== */ |
| 7056 | #define REG_MATRIX_MCFG REG_ACCESS(RwReg, 0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */ |
| 7057 | #define REG_MATRIX_SCFG REG_ACCESS(RwReg, 0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */ |
| 7058 | #define REG_MATRIX_PRAS0 REG_ACCESS(RwReg, 0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */ |
| 7059 | #define REG_MATRIX_PRAS1 REG_ACCESS(RwReg, 0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */ |
| 7060 | #define REG_MATRIX_PRAS2 REG_ACCESS(RwReg, 0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */ |
| 7061 | #define REG_MATRIX_PRAS3 REG_ACCESS(RwReg, 0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */ |
| 7062 | #define REG_MATRIX_PRAS4 REG_ACCESS(RwReg, 0x400E02A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */ |
| 7063 | #define REG_MATRIX_SYSIO REG_ACCESS(RwReg, 0x400E0314U) /**< \brief (MATRIX) System I/O Configuration register */ |
| 7064 | #define REG_MATRIX_SMCNFCS REG_ACCESS(RwReg, 0x400E031CU) /**< \brief (MATRIX) SMC Chip Select NAND Flash Assignment Register */ |
| 7065 | #define REG_MATRIX_WPMR REG_ACCESS(RwReg, 0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */ |
| 7066 | #define REG_MATRIX_WPSR REG_ACCESS(RoReg, 0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */ |
| 7067 | /* ========== Register definition for PMC peripheral ========== */ |
| 7068 | #define REG_PMC_SCER REG_ACCESS(WoReg, 0x400E0400U) /**< \brief (PMC) System Clock Enable Register */ |
| 7069 | #define REG_PMC_SCDR REG_ACCESS(WoReg, 0x400E0404U) /**< \brief (PMC) System Clock Disable Register */ |
| 7070 | #define REG_PMC_SCSR REG_ACCESS(RoReg, 0x400E0408U) /**< \brief (PMC) System Clock Status Register */ |
| 7071 | #define REG_PMC_PCER0 REG_ACCESS(WoReg, 0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */ |
| 7072 | #define REG_PMC_PCDR0 REG_ACCESS(WoReg, 0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */ |
| 7073 | #define REG_PMC_PCSR0 REG_ACCESS(RoReg, 0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */ |
| 7074 | #define REG_PMC_MOR REG_ACCESS(RwReg, 0x400E0420U) /**< \brief (PMC) Main Oscillator Register */ |
| 7075 | #define REG_PMC_MCFR REG_ACCESS(RoReg, 0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */ |
| 7076 | #define REG_PMC_PLLAR REG_ACCESS(RwReg, 0x400E0428U) /**< \brief (PMC) PLLA Register */ |
| 7077 | #define REG_PMC_PLLBR REG_ACCESS(RwReg, 0x400E042CU) /**< \brief (PMC) PLLB Register */ |
| 7078 | #define REG_PMC_MCKR REG_ACCESS(RwReg, 0x400E0430U) /**< \brief (PMC) Master Clock Register */ |
| 7079 | #define REG_PMC_USB REG_ACCESS(RwReg, 0x400E0438U) /**< \brief (PMC) USB Clock Register */ |
| 7080 | #define REG_PMC_PCK REG_ACCESS(RwReg, 0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */ |
| 7081 | #define REG_PMC_IER REG_ACCESS(WoReg, 0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */ |
| 7082 | #define REG_PMC_IDR REG_ACCESS(WoReg, 0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */ |
| 7083 | #define REG_PMC_SR REG_ACCESS(RoReg, 0x400E0468U) /**< \brief (PMC) Status Register */ |
| 7084 | #define REG_PMC_IMR REG_ACCESS(RoReg, 0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */ |
| 7085 | #define REG_PMC_FSMR REG_ACCESS(RwReg, 0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */ |
| 7086 | #define REG_PMC_FSPR REG_ACCESS(RwReg, 0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */ |
| 7087 | #define REG_PMC_FOCR REG_ACCESS(WoReg, 0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */ |
| 7088 | #define REG_PMC_WPMR REG_ACCESS(RwReg, 0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */ |
| 7089 | #define REG_PMC_WPSR REG_ACCESS(RoReg, 0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */ |
| 7090 | #define REG_PMC_PCER1 REG_ACCESS(WoReg, 0x400E0500U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */ |
| 7091 | #define REG_PMC_PCDR1 REG_ACCESS(WoReg, 0x400E0504U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */ |
| 7092 | #define REG_PMC_PCSR1 REG_ACCESS(RoReg, 0x400E0508U) /**< \brief (PMC) Peripheral Clock Status Register 1 */ |
| 7093 | #define REG_PMC_OCR REG_ACCESS(RwReg, 0x400E0510U) /**< \brief (PMC) Oscillator Calibration Register */ |
| 7094 | /* ========== Register definition for UART0 peripheral ========== */ |
| 7095 | #define REG_UART0_CR REG_ACCESS(WoReg, 0x400E0600U) /**< \brief (UART0) Control Register */ |
| 7096 | #define REG_UART0_MR REG_ACCESS(RwReg, 0x400E0604U) /**< \brief (UART0) Mode Register */ |
| 7097 | #define REG_UART0_IER REG_ACCESS(WoReg, 0x400E0608U) /**< \brief (UART0) Interrupt Enable Register */ |
| 7098 | #define REG_UART0_IDR REG_ACCESS(WoReg, 0x400E060CU) /**< \brief (UART0) Interrupt Disable Register */ |
| 7099 | #define REG_UART0_IMR REG_ACCESS(RoReg, 0x400E0610U) /**< \brief (UART0) Interrupt Mask Register */ |
| 7100 | #define REG_UART0_SR REG_ACCESS(RoReg, 0x400E0614U) /**< \brief (UART0) Status Register */ |
| 7101 | #define REG_UART0_RHR REG_ACCESS(RoReg, 0x400E0618U) /**< \brief (UART0) Receive Holding Register */ |
| 7102 | #define REG_UART0_THR REG_ACCESS(WoReg, 0x400E061CU) /**< \brief (UART0) Transmit Holding Register */ |
| 7103 | #define REG_UART0_BRGR REG_ACCESS(RwReg, 0x400E0620U) /**< \brief (UART0) Baud Rate Generator Register */ |
| 7104 | #define REG_UART0_RPR REG_ACCESS(RwReg, 0x400E0700U) /**< \brief (UART0) Receive Pointer Register */ |
| 7105 | #define REG_UART0_RCR REG_ACCESS(RwReg, 0x400E0704U) /**< \brief (UART0) Receive Counter Register */ |
| 7106 | #define REG_UART0_TPR REG_ACCESS(RwReg, 0x400E0708U) /**< \brief (UART0) Transmit Pointer Register */ |
| 7107 | #define REG_UART0_TCR REG_ACCESS(RwReg, 0x400E070CU) /**< \brief (UART0) Transmit Counter Register */ |
| 7108 | #define REG_UART0_RNPR REG_ACCESS(RwReg, 0x400E0710U) /**< \brief (UART0) Receive Next Pointer Register */ |
| 7109 | #define REG_UART0_RNCR REG_ACCESS(RwReg, 0x400E0714U) /**< \brief (UART0) Receive Next Counter Register */ |
| 7110 | #define REG_UART0_TNPR REG_ACCESS(RwReg, 0x400E0718U) /**< \brief (UART0) Transmit Next Pointer Register */ |
| 7111 | #define REG_UART0_TNCR REG_ACCESS(RwReg, 0x400E071CU) /**< \brief (UART0) Transmit Next Counter Register */ |
| 7112 | #define REG_UART0_PTCR REG_ACCESS(WoReg, 0x400E0720U) /**< \brief (UART0) Transfer Control Register */ |
| 7113 | #define REG_UART0_PTSR REG_ACCESS(RoReg, 0x400E0724U) /**< \brief (UART0) Transfer Status Register */ |
| 7114 | /* ========== Register definition for CHIPID peripheral ========== */ |
| 7115 | #define REG_CHIPID_CIDR REG_ACCESS(RoReg, 0x400E0740U) /**< \brief (CHIPID) Chip ID Register */ |
| 7116 | #define REG_CHIPID_EXID REG_ACCESS(RoReg, 0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */ |
| 7117 | /* ========== Register definition for UART1 peripheral ========== */ |
| 7118 | #define REG_UART1_CR REG_ACCESS(WoReg, 0x400E0800U) /**< \brief (UART1) Control Register */ |
| 7119 | #define REG_UART1_MR REG_ACCESS(RwReg, 0x400E0804U) /**< \brief (UART1) Mode Register */ |
| 7120 | #define REG_UART1_IER REG_ACCESS(WoReg, 0x400E0808U) /**< \brief (UART1) Interrupt Enable Register */ |
| 7121 | #define REG_UART1_IDR REG_ACCESS(WoReg, 0x400E080CU) /**< \brief (UART1) Interrupt Disable Register */ |
| 7122 | #define REG_UART1_IMR REG_ACCESS(RoReg, 0x400E0810U) /**< \brief (UART1) Interrupt Mask Register */ |
| 7123 | #define REG_UART1_SR REG_ACCESS(RoReg, 0x400E0814U) /**< \brief (UART1) Status Register */ |
| 7124 | #define REG_UART1_RHR REG_ACCESS(RoReg, 0x400E0818U) /**< \brief (UART1) Receive Holding Register */ |
| 7125 | #define REG_UART1_THR REG_ACCESS(WoReg, 0x400E081CU) /**< \brief (UART1) Transmit Holding Register */ |
| 7126 | #define REG_UART1_BRGR REG_ACCESS(RwReg, 0x400E0820U) /**< \brief (UART1) Baud Rate Generator Register */ |
| 7127 | #define REG_UART1_RPR REG_ACCESS(RwReg, 0x400E0900U) /**< \brief (UART1) Receive Pointer Register */ |
| 7128 | #define REG_UART1_RCR REG_ACCESS(RwReg, 0x400E0904U) /**< \brief (UART1) Receive Counter Register */ |
| 7129 | #define REG_UART1_TPR REG_ACCESS(RwReg, 0x400E0908U) /**< \brief (UART1) Transmit Pointer Register */ |
| 7130 | #define REG_UART1_TCR REG_ACCESS(RwReg, 0x400E090CU) /**< \brief (UART1) Transmit Counter Register */ |
| 7131 | #define REG_UART1_RNPR REG_ACCESS(RwReg, 0x400E0910U) /**< \brief (UART1) Receive Next Pointer Register */ |
| 7132 | #define REG_UART1_RNCR REG_ACCESS(RwReg, 0x400E0914U) /**< \brief (UART1) Receive Next Counter Register */ |
| 7133 | #define REG_UART1_TNPR REG_ACCESS(RwReg, 0x400E0918U) /**< \brief (UART1) Transmit Next Pointer Register */ |
| 7134 | #define REG_UART1_TNCR REG_ACCESS(RwReg, 0x400E091CU) /**< \brief (UART1) Transmit Next Counter Register */ |
| 7135 | #define REG_UART1_PTCR REG_ACCESS(WoReg, 0x400E0920U) /**< \brief (UART1) Transfer Control Register */ |
| 7136 | #define REG_UART1_PTSR REG_ACCESS(RoReg, 0x400E0924U) /**< \brief (UART1) Transfer Status Register */ |
| 7137 | /* ========== Register definition for EFC peripheral ========== */ |
| 7138 | #define REG_EFC_FMR REG_ACCESS(RwReg, 0x400E0A00U) /**< \brief (EFC) EEFC Flash Mode Register */ |
| 7139 | #define REG_EFC_FCR REG_ACCESS(WoReg, 0x400E0A04U) /**< \brief (EFC) EEFC Flash Command Register */ |
| 7140 | #define REG_EFC_FSR REG_ACCESS(RoReg, 0x400E0A08U) /**< \brief (EFC) EEFC Flash Status Register */ |
| 7141 | #define REG_EFC_FRR REG_ACCESS(RoReg, 0x400E0A0CU) /**< \brief (EFC) EEFC Flash Result Register */ |
| 7142 | /* ========== Register definition for PIOA peripheral ========== */ |
| 7143 | #define REG_PIOA_PER REG_ACCESS(WoReg, 0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */ |
| 7144 | #define REG_PIOA_PDR REG_ACCESS(WoReg, 0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */ |
| 7145 | #define REG_PIOA_PSR REG_ACCESS(RoReg, 0x400E0E08U) /**< \brief (PIOA) PIO Status Register */ |
| 7146 | #define REG_PIOA_OER REG_ACCESS(WoReg, 0x400E0E10U) /**< \brief (PIOA) Output Enable Register */ |
| 7147 | #define REG_PIOA_ODR REG_ACCESS(WoReg, 0x400E0E14U) /**< \brief (PIOA) Output Disable Register */ |
| 7148 | #define REG_PIOA_OSR REG_ACCESS(RoReg, 0x400E0E18U) /**< \brief (PIOA) Output Status Register */ |
| 7149 | #define REG_PIOA_IFER REG_ACCESS(WoReg, 0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */ |
| 7150 | #define REG_PIOA_IFDR REG_ACCESS(WoReg, 0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */ |
| 7151 | #define REG_PIOA_IFSR REG_ACCESS(RoReg, 0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */ |
| 7152 | #define REG_PIOA_SODR REG_ACCESS(WoReg, 0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */ |
| 7153 | #define REG_PIOA_CODR REG_ACCESS(WoReg, 0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */ |
| 7154 | #define REG_PIOA_ODSR REG_ACCESS(RwReg, 0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */ |
| 7155 | #define REG_PIOA_PDSR REG_ACCESS(RoReg, 0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */ |
| 7156 | #define REG_PIOA_IER REG_ACCESS(WoReg, 0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */ |
| 7157 | #define REG_PIOA_IDR REG_ACCESS(WoReg, 0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */ |
| 7158 | #define REG_PIOA_IMR REG_ACCESS(RoReg, 0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */ |
| 7159 | #define REG_PIOA_ISR REG_ACCESS(RoReg, 0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */ |
| 7160 | #define REG_PIOA_MDER REG_ACCESS(WoReg, 0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */ |
| 7161 | #define REG_PIOA_MDDR REG_ACCESS(WoReg, 0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */ |
| 7162 | #define REG_PIOA_MDSR REG_ACCESS(RoReg, 0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */ |
| 7163 | #define REG_PIOA_PUDR REG_ACCESS(WoReg, 0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */ |
| 7164 | #define REG_PIOA_PUER REG_ACCESS(WoReg, 0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */ |
| 7165 | #define REG_PIOA_PUSR REG_ACCESS(RoReg, 0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */ |
| 7166 | #define REG_PIOA_ABCDSR REG_ACCESS(RwReg, 0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */ |
| 7167 | #define REG_PIOA_IFSCDR REG_ACCESS(WoReg, 0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */ |
| 7168 | #define REG_PIOA_IFSCER REG_ACCESS(WoReg, 0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */ |
| 7169 | #define REG_PIOA_IFSCSR REG_ACCESS(RoReg, 0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */ |
| 7170 | #define REG_PIOA_SCDR REG_ACCESS(RwReg, 0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */ |
| 7171 | #define REG_PIOA_PPDDR REG_ACCESS(WoReg, 0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */ |
| 7172 | #define REG_PIOA_PPDER REG_ACCESS(WoReg, 0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */ |
| 7173 | #define REG_PIOA_PPDSR REG_ACCESS(RoReg, 0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */ |
| 7174 | #define REG_PIOA_OWER REG_ACCESS(WoReg, 0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */ |
| 7175 | #define REG_PIOA_OWDR REG_ACCESS(WoReg, 0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */ |
| 7176 | #define REG_PIOA_OWSR REG_ACCESS(RoReg, 0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */ |
| 7177 | #define REG_PIOA_AIMER REG_ACCESS(WoReg, 0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */ |
| 7178 | #define REG_PIOA_AIMDR REG_ACCESS(WoReg, 0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */ |
| 7179 | #define REG_PIOA_AIMMR REG_ACCESS(RoReg, 0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */ |
| 7180 | #define REG_PIOA_ESR REG_ACCESS(WoReg, 0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */ |
| 7181 | #define REG_PIOA_LSR REG_ACCESS(WoReg, 0x400E0EC4U) /**< \brief (PIOA) Level Select Register */ |
| 7182 | #define REG_PIOA_ELSR REG_ACCESS(RoReg, 0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */ |
| 7183 | #define REG_PIOA_FELLSR REG_ACCESS(WoReg, 0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */ |
| 7184 | #define REG_PIOA_REHLSR REG_ACCESS(WoReg, 0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */ |
| 7185 | #define REG_PIOA_FRLHSR REG_ACCESS(RoReg, 0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */ |
| 7186 | #define REG_PIOA_LOCKSR REG_ACCESS(RoReg, 0x400E0EE0U) /**< \brief (PIOA) Lock Status */ |
| 7187 | #define REG_PIOA_WPMR REG_ACCESS(RwReg, 0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */ |
| 7188 | #define REG_PIOA_WPSR REG_ACCESS(RoReg, 0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */ |
| 7189 | #define REG_PIOA_SCHMITT REG_ACCESS(RwReg, 0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */ |
| 7190 | #define REG_PIOA_PCMR REG_ACCESS(RwReg, 0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */ |
| 7191 | #define REG_PIOA_PCIER REG_ACCESS(WoReg, 0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */ |
| 7192 | #define REG_PIOA_PCIDR REG_ACCESS(WoReg, 0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */ |
| 7193 | #define REG_PIOA_PCIMR REG_ACCESS(RoReg, 0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */ |
| 7194 | #define REG_PIOA_PCISR REG_ACCESS(RoReg, 0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */ |
| 7195 | #define REG_PIOA_PCRHR REG_ACCESS(RoReg, 0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */ |
| 7196 | #define REG_PIOA_RPR REG_ACCESS(RwReg, 0x400E0F68U) /**< \brief (PIOA) Receive Pointer Register */ |
| 7197 | #define REG_PIOA_RCR REG_ACCESS(RwReg, 0x400E0F6CU) /**< \brief (PIOA) Receive Counter Register */ |
| 7198 | #define REG_PIOA_TPR REG_ACCESS(RwReg, 0x400E0F70U) /**< \brief (PIOA) Transmit Pointer Register */ |
| 7199 | #define REG_PIOA_TCR REG_ACCESS(RwReg, 0x400E0F74U) /**< \brief (PIOA) Transmit Counter Register */ |
| 7200 | #define REG_PIOA_RNPR REG_ACCESS(RwReg, 0x400E0F78U) /**< \brief (PIOA) Receive Next Pointer Register */ |
| 7201 | #define REG_PIOA_RNCR REG_ACCESS(RwReg, 0x400E0F7CU) /**< \brief (PIOA) Receive Next Counter Register */ |
| 7202 | #define REG_PIOA_TNPR REG_ACCESS(RwReg, 0x400E0F80U) /**< \brief (PIOA) Transmit Next Pointer Register */ |
| 7203 | #define REG_PIOA_TNCR REG_ACCESS(RwReg, 0x400E0F84U) /**< \brief (PIOA) Transmit Next Counter Register */ |
| 7204 | #define REG_PIOA_PTCR REG_ACCESS(WoReg, 0x400E0F88U) /**< \brief (PIOA) Transfer Control Register */ |
| 7205 | #define REG_PIOA_PTSR REG_ACCESS(RoReg, 0x400E0F8CU) /**< \brief (PIOA) Transfer Status Register */ |
| 7206 | /* ========== Register definition for PIOB peripheral ========== */ |
| 7207 | #define REG_PIOB_PER REG_ACCESS(WoReg, 0x400E1000U) /**< \brief (PIOB) PIO Enable Register */ |
| 7208 | #define REG_PIOB_PDR REG_ACCESS(WoReg, 0x400E1004U) /**< \brief (PIOB) PIO Disable Register */ |
| 7209 | #define REG_PIOB_PSR REG_ACCESS(RoReg, 0x400E1008U) /**< \brief (PIOB) PIO Status Register */ |
| 7210 | #define REG_PIOB_OER REG_ACCESS(WoReg, 0x400E1010U) /**< \brief (PIOB) Output Enable Register */ |
| 7211 | #define REG_PIOB_ODR REG_ACCESS(WoReg, 0x400E1014U) /**< \brief (PIOB) Output Disable Register */ |
| 7212 | #define REG_PIOB_OSR REG_ACCESS(RoReg, 0x400E1018U) /**< \brief (PIOB) Output Status Register */ |
| 7213 | #define REG_PIOB_IFER REG_ACCESS(WoReg, 0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */ |
| 7214 | #define REG_PIOB_IFDR REG_ACCESS(WoReg, 0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */ |
| 7215 | #define REG_PIOB_IFSR REG_ACCESS(RoReg, 0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */ |
| 7216 | #define REG_PIOB_SODR REG_ACCESS(WoReg, 0x400E1030U) /**< \brief (PIOB) Set Output Data Register */ |
| 7217 | #define REG_PIOB_CODR REG_ACCESS(WoReg, 0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */ |
| 7218 | #define REG_PIOB_ODSR REG_ACCESS(RwReg, 0x400E1038U) /**< \brief (PIOB) Output Data Status Register */ |
| 7219 | #define REG_PIOB_PDSR REG_ACCESS(RoReg, 0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */ |
| 7220 | #define REG_PIOB_IER REG_ACCESS(WoReg, 0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */ |
| 7221 | #define REG_PIOB_IDR REG_ACCESS(WoReg, 0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */ |
| 7222 | #define REG_PIOB_IMR REG_ACCESS(RoReg, 0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */ |
| 7223 | #define REG_PIOB_ISR REG_ACCESS(RoReg, 0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */ |
| 7224 | #define REG_PIOB_MDER REG_ACCESS(WoReg, 0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */ |
| 7225 | #define REG_PIOB_MDDR REG_ACCESS(WoReg, 0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */ |
| 7226 | #define REG_PIOB_MDSR REG_ACCESS(RoReg, 0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */ |
| 7227 | #define REG_PIOB_PUDR REG_ACCESS(WoReg, 0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */ |
| 7228 | #define REG_PIOB_PUER REG_ACCESS(WoReg, 0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */ |
| 7229 | #define REG_PIOB_PUSR REG_ACCESS(RoReg, 0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */ |
| 7230 | #define REG_PIOB_ABCDSR REG_ACCESS(RwReg, 0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */ |
| 7231 | #define REG_PIOB_IFSCDR REG_ACCESS(WoReg, 0x400E1080U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */ |
| 7232 | #define REG_PIOB_IFSCER REG_ACCESS(WoReg, 0x400E1084U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */ |
| 7233 | #define REG_PIOB_IFSCSR REG_ACCESS(RoReg, 0x400E1088U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */ |
| 7234 | #define REG_PIOB_SCDR REG_ACCESS(RwReg, 0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */ |
| 7235 | #define REG_PIOB_PPDDR REG_ACCESS(WoReg, 0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */ |
| 7236 | #define REG_PIOB_PPDER REG_ACCESS(WoReg, 0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */ |
| 7237 | #define REG_PIOB_PPDSR REG_ACCESS(RoReg, 0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */ |
| 7238 | #define REG_PIOB_OWER REG_ACCESS(WoReg, 0x400E10A0U) /**< \brief (PIOB) Output Write Enable */ |
| 7239 | #define REG_PIOB_OWDR REG_ACCESS(WoReg, 0x400E10A4U) /**< \brief (PIOB) Output Write Disable */ |
| 7240 | #define REG_PIOB_OWSR REG_ACCESS(RoReg, 0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */ |
| 7241 | #define REG_PIOB_AIMER REG_ACCESS(WoReg, 0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */ |
| 7242 | #define REG_PIOB_AIMDR REG_ACCESS(WoReg, 0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */ |
| 7243 | #define REG_PIOB_AIMMR REG_ACCESS(RoReg, 0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */ |
| 7244 | #define REG_PIOB_ESR REG_ACCESS(WoReg, 0x400E10C0U) /**< \brief (PIOB) Edge Select Register */ |
| 7245 | #define REG_PIOB_LSR REG_ACCESS(WoReg, 0x400E10C4U) /**< \brief (PIOB) Level Select Register */ |
| 7246 | #define REG_PIOB_ELSR REG_ACCESS(RoReg, 0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */ |
| 7247 | #define REG_PIOB_FELLSR REG_ACCESS(WoReg, 0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */ |
| 7248 | #define REG_PIOB_REHLSR REG_ACCESS(WoReg, 0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */ |
| 7249 | #define REG_PIOB_FRLHSR REG_ACCESS(RoReg, 0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */ |
| 7250 | #define REG_PIOB_LOCKSR REG_ACCESS(RoReg, 0x400E10E0U) /**< \brief (PIOB) Lock Status */ |
| 7251 | #define REG_PIOB_WPMR REG_ACCESS(RwReg, 0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */ |
| 7252 | #define REG_PIOB_WPSR REG_ACCESS(RoReg, 0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */ |
| 7253 | #define REG_PIOB_SCHMITT REG_ACCESS(RwReg, 0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */ |
| 7254 | #define REG_PIOB_PCMR REG_ACCESS(RwReg, 0x400E1150U) /**< \brief (PIOB) Parallel Capture Mode Register */ |
| 7255 | #define REG_PIOB_PCIER REG_ACCESS(WoReg, 0x400E1154U) /**< \brief (PIOB) Parallel Capture Interrupt Enable Register */ |
| 7256 | #define REG_PIOB_PCIDR REG_ACCESS(WoReg, 0x400E1158U) /**< \brief (PIOB) Parallel Capture Interrupt Disable Register */ |
| 7257 | #define REG_PIOB_PCIMR REG_ACCESS(RoReg, 0x400E115CU) /**< \brief (PIOB) Parallel Capture Interrupt Mask Register */ |
| 7258 | #define REG_PIOB_PCISR REG_ACCESS(RoReg, 0x400E1160U) /**< \brief (PIOB) Parallel Capture Interrupt Status Register */ |
| 7259 | #define REG_PIOB_PCRHR REG_ACCESS(RoReg, 0x400E1164U) /**< \brief (PIOB) Parallel Capture Reception Holding Register */ |
| 7260 | /* ========== Register definition for PIOC peripheral ========== */ |
| 7261 | #define REG_PIOC_PER REG_ACCESS(WoReg, 0x400E1200U) /**< \brief (PIOC) PIO Enable Register */ |
| 7262 | #define REG_PIOC_PDR REG_ACCESS(WoReg, 0x400E1204U) /**< \brief (PIOC) PIO Disable Register */ |
| 7263 | #define REG_PIOC_PSR REG_ACCESS(RoReg, 0x400E1208U) /**< \brief (PIOC) PIO Status Register */ |
| 7264 | #define REG_PIOC_OER REG_ACCESS(WoReg, 0x400E1210U) /**< \brief (PIOC) Output Enable Register */ |
| 7265 | #define REG_PIOC_ODR REG_ACCESS(WoReg, 0x400E1214U) /**< \brief (PIOC) Output Disable Register */ |
| 7266 | #define REG_PIOC_OSR REG_ACCESS(RoReg, 0x400E1218U) /**< \brief (PIOC) Output Status Register */ |
| 7267 | #define REG_PIOC_IFER REG_ACCESS(WoReg, 0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */ |
| 7268 | #define REG_PIOC_IFDR REG_ACCESS(WoReg, 0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */ |
| 7269 | #define REG_PIOC_IFSR REG_ACCESS(RoReg, 0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */ |
| 7270 | #define REG_PIOC_SODR REG_ACCESS(WoReg, 0x400E1230U) /**< \brief (PIOC) Set Output Data Register */ |
| 7271 | #define REG_PIOC_CODR REG_ACCESS(WoReg, 0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */ |
| 7272 | #define REG_PIOC_ODSR REG_ACCESS(RwReg, 0x400E1238U) /**< \brief (PIOC) Output Data Status Register */ |
| 7273 | #define REG_PIOC_PDSR REG_ACCESS(RoReg, 0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */ |
| 7274 | #define REG_PIOC_IER REG_ACCESS(WoReg, 0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */ |
| 7275 | #define REG_PIOC_IDR REG_ACCESS(WoReg, 0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */ |
| 7276 | #define REG_PIOC_IMR REG_ACCESS(RoReg, 0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */ |
| 7277 | #define REG_PIOC_ISR REG_ACCESS(RoReg, 0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */ |
| 7278 | #define REG_PIOC_MDER REG_ACCESS(WoReg, 0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */ |
| 7279 | #define REG_PIOC_MDDR REG_ACCESS(WoReg, 0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */ |
| 7280 | #define REG_PIOC_MDSR REG_ACCESS(RoReg, 0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */ |
| 7281 | #define REG_PIOC_PUDR REG_ACCESS(WoReg, 0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */ |
| 7282 | #define REG_PIOC_PUER REG_ACCESS(WoReg, 0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */ |
| 7283 | #define REG_PIOC_PUSR REG_ACCESS(RoReg, 0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */ |
| 7284 | #define REG_PIOC_ABCDSR REG_ACCESS(RwReg, 0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */ |
| 7285 | #define REG_PIOC_IFSCDR REG_ACCESS(WoReg, 0x400E1280U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */ |
| 7286 | #define REG_PIOC_IFSCER REG_ACCESS(WoReg, 0x400E1284U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */ |
| 7287 | #define REG_PIOC_IFSCSR REG_ACCESS(RoReg, 0x400E1288U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */ |
| 7288 | #define REG_PIOC_SCDR REG_ACCESS(RwReg, 0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */ |
| 7289 | #define REG_PIOC_PPDDR REG_ACCESS(WoReg, 0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */ |
| 7290 | #define REG_PIOC_PPDER REG_ACCESS(WoReg, 0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */ |
| 7291 | #define REG_PIOC_PPDSR REG_ACCESS(RoReg, 0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */ |
| 7292 | #define REG_PIOC_OWER REG_ACCESS(WoReg, 0x400E12A0U) /**< \brief (PIOC) Output Write Enable */ |
| 7293 | #define REG_PIOC_OWDR REG_ACCESS(WoReg, 0x400E12A4U) /**< \brief (PIOC) Output Write Disable */ |
| 7294 | #define REG_PIOC_OWSR REG_ACCESS(RoReg, 0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */ |
| 7295 | #define REG_PIOC_AIMER REG_ACCESS(WoReg, 0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */ |
| 7296 | #define REG_PIOC_AIMDR REG_ACCESS(WoReg, 0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */ |
| 7297 | #define REG_PIOC_AIMMR REG_ACCESS(RoReg, 0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */ |
| 7298 | #define REG_PIOC_ESR REG_ACCESS(WoReg, 0x400E12C0U) /**< \brief (PIOC) Edge Select Register */ |
| 7299 | #define REG_PIOC_LSR REG_ACCESS(WoReg, 0x400E12C4U) /**< \brief (PIOC) Level Select Register */ |
| 7300 | #define REG_PIOC_ELSR REG_ACCESS(RoReg, 0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */ |
| 7301 | #define REG_PIOC_FELLSR REG_ACCESS(WoReg, 0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */ |
| 7302 | #define REG_PIOC_REHLSR REG_ACCESS(WoReg, 0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */ |
| 7303 | #define REG_PIOC_FRLHSR REG_ACCESS(RoReg, 0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */ |
| 7304 | #define REG_PIOC_LOCKSR REG_ACCESS(RoReg, 0x400E12E0U) /**< \brief (PIOC) Lock Status */ |
| 7305 | #define REG_PIOC_WPMR REG_ACCESS(RwReg, 0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */ |
| 7306 | #define REG_PIOC_WPSR REG_ACCESS(RoReg, 0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */ |
| 7307 | #define REG_PIOC_SCHMITT REG_ACCESS(RwReg, 0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */ |
| 7308 | #define REG_PIOC_PCMR REG_ACCESS(RwReg, 0x400E1350U) /**< \brief (PIOC) Parallel Capture Mode Register */ |
| 7309 | #define REG_PIOC_PCIER REG_ACCESS(WoReg, 0x400E1354U) /**< \brief (PIOC) Parallel Capture Interrupt Enable Register */ |
| 7310 | #define REG_PIOC_PCIDR REG_ACCESS(WoReg, 0x400E1358U) /**< \brief (PIOC) Parallel Capture Interrupt Disable Register */ |
| 7311 | #define REG_PIOC_PCIMR REG_ACCESS(RoReg, 0x400E135CU) /**< \brief (PIOC) Parallel Capture Interrupt Mask Register */ |
| 7312 | #define REG_PIOC_PCISR REG_ACCESS(RoReg, 0x400E1360U) /**< \brief (PIOC) Parallel Capture Interrupt Status Register */ |
| 7313 | #define REG_PIOC_PCRHR REG_ACCESS(RoReg, 0x400E1364U) /**< \brief (PIOC) Parallel Capture Reception Holding Register */ |
| 7314 | /* ========== Register definition for RSTC peripheral ========== */ |
| 7315 | #define REG_RSTC_CR REG_ACCESS(WoReg, 0x400E1400U) /**< \brief (RSTC) Control Register */ |
| 7316 | #define REG_RSTC_SR REG_ACCESS(RoReg, 0x400E1404U) /**< \brief (RSTC) Status Register */ |
| 7317 | #define REG_RSTC_MR REG_ACCESS(RwReg, 0x400E1408U) /**< \brief (RSTC) Mode Register */ |
| 7318 | /* ========== Register definition for SUPC peripheral ========== */ |
| 7319 | #define REG_SUPC_CR REG_ACCESS(WoReg, 0x400E1410U) /**< \brief (SUPC) Supply Controller Control Register */ |
| 7320 | #define REG_SUPC_SMMR REG_ACCESS(RwReg, 0x400E1414U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */ |
| 7321 | #define REG_SUPC_MR REG_ACCESS(RwReg, 0x400E1418U) /**< \brief (SUPC) Supply Controller Mode Register */ |
| 7322 | #define REG_SUPC_WUMR REG_ACCESS(RwReg, 0x400E141CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */ |
| 7323 | #define REG_SUPC_WUIR REG_ACCESS(RwReg, 0x400E1420U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */ |
| 7324 | #define REG_SUPC_SR REG_ACCESS(RoReg, 0x400E1424U) /**< \brief (SUPC) Supply Controller Status Register */ |
| 7325 | /* ========== Register definition for RTT peripheral ========== */ |
| 7326 | #define REG_RTT_MR REG_ACCESS(RwReg, 0x400E1430U) /**< \brief (RTT) Mode Register */ |
| 7327 | #define REG_RTT_AR REG_ACCESS(RwReg, 0x400E1434U) /**< \brief (RTT) Alarm Register */ |
| 7328 | #define REG_RTT_VR REG_ACCESS(RoReg, 0x400E1438U) /**< \brief (RTT) Value Register */ |
| 7329 | #define REG_RTT_SR REG_ACCESS(RoReg, 0x400E143CU) /**< \brief (RTT) Status Register */ |
| 7330 | /* ========== Register definition for WDT peripheral ========== */ |
| 7331 | #define REG_WDT_CR REG_ACCESS(WoReg, 0x400E1450U) /**< \brief (WDT) Control Register */ |
| 7332 | #define REG_WDT_MR REG_ACCESS(RwReg, 0x400E1454U) /**< \brief (WDT) Mode Register */ |
| 7333 | #define REG_WDT_SR REG_ACCESS(RoReg, 0x400E1458U) /**< \brief (WDT) Status Register */ |
| 7334 | /* ========== Register definition for RTC peripheral ========== */ |
| 7335 | #define REG_RTC_CR REG_ACCESS(RwReg, 0x400E1460U) /**< \brief (RTC) Control Register */ |
| 7336 | #define REG_RTC_MR REG_ACCESS(RwReg, 0x400E1464U) /**< \brief (RTC) Mode Register */ |
| 7337 | #define REG_RTC_TIMR REG_ACCESS(RwReg, 0x400E1468U) /**< \brief (RTC) Time Register */ |
| 7338 | #define REG_RTC_CALR REG_ACCESS(RwReg, 0x400E146CU) /**< \brief (RTC) Calendar Register */ |
| 7339 | #define REG_RTC_TIMALR REG_ACCESS(RwReg, 0x400E1470U) /**< \brief (RTC) Time Alarm Register */ |
| 7340 | #define REG_RTC_CALALR REG_ACCESS(RwReg, 0x400E1474U) /**< \brief (RTC) Calendar Alarm Register */ |
| 7341 | #define REG_RTC_SR REG_ACCESS(RoReg, 0x400E1478U) /**< \brief (RTC) Status Register */ |
| 7342 | #define REG_RTC_SCCR REG_ACCESS(WoReg, 0x400E147CU) /**< \brief (RTC) Status Clear Command Register */ |
| 7343 | #define REG_RTC_IER REG_ACCESS(WoReg, 0x400E1480U) /**< \brief (RTC) Interrupt Enable Register */ |
| 7344 | #define REG_RTC_IDR REG_ACCESS(WoReg, 0x400E1484U) /**< \brief (RTC) Interrupt Disable Register */ |
| 7345 | #define REG_RTC_IMR REG_ACCESS(RoReg, 0x400E1488U) /**< \brief (RTC) Interrupt Mask Register */ |
| 7346 | #define REG_RTC_VER REG_ACCESS(RoReg, 0x400E148CU) /**< \brief (RTC) Valid Entry Register */ |
| 7347 | /* ========== Register definition for GPBR peripheral ========== */ |
| 7348 | #define REG_GPBR_GPBR0 REG_ACCESS(RwReg, 0x400E1490U) /**< \brief (GPBR) General Purpose Backup Register 0 */ |
| 7349 | #define REG_GPBR_GPBR1 REG_ACCESS(RwReg, 0x400E1494U) /**< \brief (GPBR) General Purpose Backup Register 1 */ |
| 7350 | #define REG_GPBR_GPBR2 REG_ACCESS(RwReg, 0x400E1498U) /**< \brief (GPBR) General Purpose Backup Register 2 */ |
| 7351 | #define REG_GPBR_GPBR3 REG_ACCESS(RwReg, 0x400E149CU) /**< \brief (GPBR) General Purpose Backup Register 3 */ |
| 7352 | #define REG_GPBR_GPBR4 REG_ACCESS(RwReg, 0x400E14A0U) /**< \brief (GPBR) General Purpose Backup Register 4 */ |
| 7353 | #define REG_GPBR_GPBR5 REG_ACCESS(RwReg, 0x400E14A4U) /**< \brief (GPBR) General Purpose Backup Register 5 */ |
| 7354 | #define REG_GPBR_GPBR6 REG_ACCESS(RwReg, 0x400E14A8U) /**< \brief (GPBR) General Purpose Backup Register 6 */ |
| 7355 | #define REG_GPBR_GPBR7 REG_ACCESS(RwReg, 0x400E14ACU) /**< \brief (GPBR) General Purpose Backup Register 7 */ |
| 7356 | /*@}*/ |
| 7357 | |
| 7358 | /* ************************************************************************** */ |
| 7359 | /* PERIPHERAL ID DEFINITIONS FOR SAM3S */ |
| 7360 | /* ************************************************************************** */ |
| 7361 | /** \addtogroup SAM3S_id Peripheral Ids Definitions */ |
| 7362 | /*@{*/ |
| 7363 | |
| 7364 | #define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ |
| 7365 | #define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ |
| 7366 | #define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ |
| 7367 | #define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ |
| 7368 | #define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ |
| 7369 | #define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ |
| 7370 | #define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ |
| 7371 | #define ID_UART0 ( 8) /**< \brief UART 0 (UART0) */ |
| 7372 | #define ID_UART1 ( 9) /**< \brief UART 1 (UART1) */ |
| 7373 | #define ID_SMC (10) /**< \brief Static Memory Controller (SMC) */ |
| 7374 | #define ID_PIOA (11) /**< \brief Parallel I/O Controller A (PIOA) */ |
| 7375 | #define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */ |
| 7376 | #define ID_PIOC (13) /**< \brief Parallel I/O Controller C (PIOC) */ |
| 7377 | #define ID_USART0 (14) /**< \brief USART 0 (USART0) */ |
| 7378 | #define ID_USART1 (15) /**< \brief USART 1 (USART1) */ |
| 7379 | #define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ |
| 7380 | #define ID_TWI0 (19) /**< \brief Two Wire Interface 0 (TWI0) */ |
| 7381 | #define ID_TWI1 (20) /**< \brief Two Wire Interface 1 (TWI1) */ |
| 7382 | #define ID_SPI (21) /**< \brief Serial Peripheral Interface (SPI) */ |
| 7383 | #define ID_SSC (22) /**< \brief Synchronous Serial Controler (SSC) */ |
| 7384 | #define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ |
| 7385 | #define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ |
| 7386 | #define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ |
| 7387 | #define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ |
| 7388 | #define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ |
| 7389 | #define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ |
| 7390 | #define ID_ADC (29) /**< \brief Analog To Digital Converter (ADC) */ |
| 7391 | #define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ |
| 7392 | #define ID_PWM (31) /**< \brief Pulse Width Modulation (PWM) */ |
| 7393 | #define ID_CRCCU (32) /**< \brief CRC Calculation Unit (CRCCU) */ |
| 7394 | #define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ |
| 7395 | #define ID_UDP (34) /**< \brief USB Device Port (UDP) */ |
| 7396 | /*@}*/ |
| 7397 | |
| 7398 | /* ************************************************************************** */ |
| 7399 | /* BASE ADDRESS DEFINITIONS FOR SAM3S */ |
| 7400 | /* ************************************************************************** */ |
| 7401 | /** \addtogroup SAM3S_base Peripheral Base Address Definitions */ |
| 7402 | /*@{*/ |
| 7403 | |
| 7404 | #define HSMCI CAST(Hsmci , 0x40000000U) /**< \brief (HSMCI ) Base Address */ |
| 7405 | #define PDC_HSMCI CAST(Pdc , 0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */ |
| 7406 | #define SSC CAST(Ssc , 0x40004000U) /**< \brief (SSC ) Base Address */ |
| 7407 | #define PDC_SSC CAST(Pdc , 0x40004100U) /**< \brief (PDC_SSC ) Base Address */ |
| 7408 | #define SPI CAST(Spi , 0x40008000U) /**< \brief (SPI ) Base Address */ |
| 7409 | #define PDC_SPI CAST(Pdc , 0x40008100U) /**< \brief (PDC_SPI ) Base Address */ |
| 7410 | #define TC0 CAST(Tc , 0x40010000U) /**< \brief (TC0 ) Base Address */ |
| 7411 | #define TC1 CAST(Tc , 0x40014000U) /**< \brief (TC1 ) Base Address */ |
| 7412 | #define TWI0 CAST(Twi , 0x40018000U) /**< \brief (TWI0 ) Base Address */ |
| 7413 | #define PDC_TWI0 CAST(Pdc , 0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */ |
| 7414 | #define TWI1 CAST(Twi , 0x4001C000U) /**< \brief (TWI1 ) Base Address */ |
| 7415 | #define PDC_TWI1 CAST(Pdc , 0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */ |
| 7416 | #define PWM CAST(Pwm , 0x40020000U) /**< \brief (PWM ) Base Address */ |
| 7417 | #define PDC_PWM CAST(Pdc , 0x40020100U) /**< \brief (PDC_PWM ) Base Address */ |
| 7418 | #define USART0 CAST(Usart , 0x40024000U) /**< \brief (USART0 ) Base Address */ |
| 7419 | #define PDC_USART0 CAST(Pdc , 0x40024100U) /**< \brief (PDC_USART0) Base Address */ |
| 7420 | #define USART1 CAST(Usart , 0x40028000U) /**< \brief (USART1 ) Base Address */ |
| 7421 | #define PDC_USART1 CAST(Pdc , 0x40028100U) /**< \brief (PDC_USART1) Base Address */ |
| 7422 | #define UDP CAST(Udp , 0x40034000U) /**< \brief (UDP ) Base Address */ |
| 7423 | #define ADC CAST(Adc , 0x40038000U) /**< \brief (ADC ) Base Address */ |
| 7424 | #define PDC_ADC CAST(Pdc , 0x40038100U) /**< \brief (PDC_ADC ) Base Address */ |
| 7425 | #define DACC CAST(Dacc , 0x4003C000U) /**< \brief (DACC ) Base Address */ |
| 7426 | #define PDC_DACC CAST(Pdc , 0x4003C100U) /**< \brief (PDC_DACC ) Base Address */ |
| 7427 | #define ACC CAST(Acc , 0x40040000U) /**< \brief (ACC ) Base Address */ |
| 7428 | #define CRCCU CAST(Crccu , 0x40044000U) /**< \brief (CRCCU ) Base Address */ |
| 7429 | #define SMC CAST(Smc , 0x400E0000U) /**< \brief (SMC ) Base Address */ |
| 7430 | #define MATRIX CAST(Matrix , 0x400E0200U) /**< \brief (MATRIX ) Base Address */ |
| 7431 | #define PMC CAST(Pmc , 0x400E0400U) /**< \brief (PMC ) Base Address */ |
| 7432 | #define UART0 CAST(Uart , 0x400E0600U) /**< \brief (UART0 ) Base Address */ |
| 7433 | #define PDC_UART0 CAST(Pdc , 0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ |
| 7434 | #define CHIPID CAST(Chipid , 0x400E0740U) /**< \brief (CHIPID ) Base Address */ |
| 7435 | #define UART1 CAST(Uart , 0x400E0800U) /**< \brief (UART1 ) Base Address */ |
| 7436 | #define PDC_UART1 CAST(Pdc , 0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */ |
| 7437 | #define EFC CAST(Efc , 0x400E0A00U) /**< \brief (EFC ) Base Address */ |
| 7438 | #define PIOA CAST(Pio , 0x400E0E00U) /**< \brief (PIOA ) Base Address */ |
| 7439 | #define PDC_PIOA CAST(Pdc , 0x400E0F00U) /**< \brief (PDC_PIOA ) Base Address */ |
| 7440 | #define PIOB CAST(Pio , 0x400E1000U) /**< \brief (PIOB ) Base Address */ |
| 7441 | #define PIOC CAST(Pio , 0x400E1200U) /**< \brief (PIOC ) Base Address */ |
| 7442 | #define RSTC CAST(Rstc , 0x400E1400U) /**< \brief (RSTC ) Base Address */ |
| 7443 | #define SUPC CAST(Supc , 0x400E1410U) /**< \brief (SUPC ) Base Address */ |
| 7444 | #define RTT CAST(Rtt , 0x400E1430U) /**< \brief (RTT ) Base Address */ |
| 7445 | #define WDT CAST(Wdt , 0x400E1450U) /**< \brief (WDT ) Base Address */ |
| 7446 | #define RTC CAST(Rtc , 0x400E1460U) /**< \brief (RTC ) Base Address */ |
| 7447 | #define GPBR CAST(Gpbr , 0x400E1490U) /**< \brief (GPBR ) Base Address */ |
| 7448 | /*@}*/ |
| 7449 | |
| 7450 | /* ************************************************************************** */ |
| 7451 | /* PIO DEFINITIONS FOR SAM3S */ |
| 7452 | /* ************************************************************************** */ |
| 7453 | /** \addtogroup SAM3S_pio Peripheral Pio Definitions */ |
| 7454 | /*@{*/ |
| 7455 | |
| 7456 | #define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ |
| 7457 | #define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ |
| 7458 | #define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ |
| 7459 | #define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ |
| 7460 | #define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ |
| 7461 | #define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ |
| 7462 | #define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ |
| 7463 | #define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ |
| 7464 | #define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ |
| 7465 | #define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ |
| 7466 | #define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ |
| 7467 | #define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ |
| 7468 | #define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ |
| 7469 | #define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ |
| 7470 | #define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ |
| 7471 | #define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ |
| 7472 | #define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ |
| 7473 | #define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ |
| 7474 | #define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ |
| 7475 | #define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ |
| 7476 | #define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ |
| 7477 | #define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ |
| 7478 | #define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ |
| 7479 | #define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ |
| 7480 | #define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ |
| 7481 | #define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ |
| 7482 | #define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ |
| 7483 | #define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ |
| 7484 | #define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ |
| 7485 | #define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ |
| 7486 | #define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ |
| 7487 | #define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ |
| 7488 | #define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ |
| 7489 | #define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ |
| 7490 | #define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ |
| 7491 | #define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ |
| 7492 | #define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ |
| 7493 | #define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ |
| 7494 | #define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ |
| 7495 | #define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ |
| 7496 | #define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ |
| 7497 | #define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ |
| 7498 | #define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */ |
| 7499 | #define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */ |
| 7500 | #define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ |
| 7501 | #define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ |
| 7502 | #define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */ |
| 7503 | #define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ |
| 7504 | #define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ |
| 7505 | #define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ |
| 7506 | #define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ |
| 7507 | #define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ |
| 7508 | #define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ |
| 7509 | #define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ |
| 7510 | #define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ |
| 7511 | #define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ |
| 7512 | #define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ |
| 7513 | #define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ |
| 7514 | #define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ |
| 7515 | #define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ |
| 7516 | #define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ |
| 7517 | #define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ |
| 7518 | #define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ |
| 7519 | #define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ |
| 7520 | #define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ |
| 7521 | #define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ |
| 7522 | #define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ |
| 7523 | #define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ |
| 7524 | #define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ |
| 7525 | #define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ |
| 7526 | #define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ |
| 7527 | #define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ |
| 7528 | #define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ |
| 7529 | #define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ |
| 7530 | #define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ |
| 7531 | #define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ |
| 7532 | #define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ |
| 7533 | #define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ |
| 7534 | #define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */ |
| 7535 | /* ========== Pio definition for HSMCI peripheral ========== */ |
| 7536 | #define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ |
| 7537 | #define PIO_PA29C_MCCK (1u << 29) /**< \brief Hsmci signal: MCCK */ |
| 7538 | #define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ |
| 7539 | #define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ |
| 7540 | #define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ |
| 7541 | #define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ |
| 7542 | /* ========== Pio definition for SSC peripheral ========== */ |
| 7543 | #define PIO_PA18A_RD (1u << 18) /**< \brief Ssc signal: RD */ |
| 7544 | #define PIO_PA20A_RF (1u << 20) /**< \brief Ssc signal: RF */ |
| 7545 | #define PIO_PA19A_RK (1u << 19) /**< \brief Ssc signal: RK */ |
| 7546 | #define PIO_PA17A_TD (1u << 17) /**< \brief Ssc signal: TD */ |
| 7547 | #define PIO_PA15A_TF (1u << 15) /**< \brief Ssc signal: TF */ |
| 7548 | #define PIO_PA16A_TK (1u << 16) /**< \brief Ssc signal: TK */ |
| 7549 | /* ========== Pio definition for SPI peripheral ========== */ |
| 7550 | #define PIO_PA12A_MISO (1u << 12) /**< \brief Spi signal: MISO */ |
| 7551 | #define PIO_PA13A_MOSI (1u << 13) /**< \brief Spi signal: MOSI */ |
| 7552 | #define PIO_PA11A_NPCS0 (1u << 11) /**< \brief Spi signal: NPCS0 */ |
| 7553 | #define PIO_PA9B_NPCS1 (1u << 9) /**< \brief Spi signal: NPCS1 */ |
| 7554 | #define PIO_PA31A_NPCS1 (1u << 31) /**< \brief Spi signal: NPCS1 */ |
| 7555 | #define PIO_PB14A_NPCS1 (1u << 14) /**< \brief Spi signal: NPCS1 */ |
| 7556 | #define PIO_PC4B_NPCS1 (1u << 4) /**< \brief Spi signal: NPCS1 */ |
| 7557 | #define PIO_PA10B_NPCS2 (1u << 10) /**< \brief Spi signal: NPCS2 */ |
| 7558 | #define PIO_PA30B_NPCS2 (1u << 30) /**< \brief Spi signal: NPCS2 */ |
| 7559 | #define PIO_PB2B_NPCS2 (1u << 2) /**< \brief Spi signal: NPCS2 */ |
| 7560 | #define PIO_PA3B_NPCS3 (1u << 3) /**< \brief Spi signal: NPCS3 */ |
| 7561 | #define PIO_PA5B_NPCS3 (1u << 5) /**< \brief Spi signal: NPCS3 */ |
| 7562 | #define PIO_PA22B_NPCS3 (1u << 22) /**< \brief Spi signal: NPCS3 */ |
| 7563 | #define PIO_PA14A_SPCK (1u << 14) /**< \brief Spi signal: SPCK */ |
| 7564 | /* ========== Pio definition for TC0 peripheral ========== */ |
| 7565 | #define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ |
| 7566 | #define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ |
| 7567 | #define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ |
| 7568 | #define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ |
| 7569 | #define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ |
| 7570 | #define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ |
| 7571 | #define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ |
| 7572 | #define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ |
| 7573 | #define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ |
| 7574 | /* ========== Pio definition for TC1 peripheral ========== */ |
| 7575 | #define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */ |
| 7576 | #define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */ |
| 7577 | #define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */ |
| 7578 | #define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */ |
| 7579 | #define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */ |
| 7580 | #define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */ |
| 7581 | #define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */ |
| 7582 | #define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */ |
| 7583 | #define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */ |
| 7584 | /* ========== Pio definition for TWI0 peripheral ========== */ |
| 7585 | #define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twi0 signal: TWCK0 */ |
| 7586 | #define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twi0 signal: TWD0 */ |
| 7587 | /* ========== Pio definition for TWI1 peripheral ========== */ |
| 7588 | #define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twi1 signal: TWCK1 */ |
| 7589 | #define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twi1 signal: TWD1 */ |
| 7590 | /* ========== Pio definition for PWM peripheral ========== */ |
| 7591 | #define PIO_PA9C_PWMFI0 (1u << 9) /**< \brief Pwm signal: PWMFI0 */ |
| 7592 | #define PIO_PA0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */ |
| 7593 | #define PIO_PA11B_PWMH0 (1u << 11) /**< \brief Pwm signal: PWMH0 */ |
| 7594 | #define PIO_PA23B_PWMH0 (1u << 23) /**< \brief Pwm signal: PWMH0 */ |
| 7595 | #define PIO_PB0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */ |
| 7596 | #define PIO_PC18B_PWMH0 (1u << 18) /**< \brief Pwm signal: PWMH0 */ |
| 7597 | #define PIO_PA1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */ |
| 7598 | #define PIO_PA12B_PWMH1 (1u << 12) /**< \brief Pwm signal: PWMH1 */ |
| 7599 | #define PIO_PA24B_PWMH1 (1u << 24) /**< \brief Pwm signal: PWMH1 */ |
| 7600 | #define PIO_PB1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */ |
| 7601 | #define PIO_PC19B_PWMH1 (1u << 19) /**< \brief Pwm signal: PWMH1 */ |
| 7602 | #define PIO_PA2A_PWMH2 (1u << 2) /**< \brief Pwm signal: PWMH2 */ |
| 7603 | #define PIO_PA13B_PWMH2 (1u << 13) /**< \brief Pwm signal: PWMH2 */ |
| 7604 | #define PIO_PA25B_PWMH2 (1u << 25) /**< \brief Pwm signal: PWMH2 */ |
| 7605 | #define PIO_PB4B_PWMH2 (1u << 4) /**< \brief Pwm signal: PWMH2 */ |
| 7606 | #define PIO_PC20B_PWMH2 (1u << 20) /**< \brief Pwm signal: PWMH2 */ |
| 7607 | #define PIO_PA7B_PWMH3 (1u << 7) /**< \brief Pwm signal: PWMH3 */ |
| 7608 | #define PIO_PA14B_PWMH3 (1u << 14) /**< \brief Pwm signal: PWMH3 */ |
| 7609 | #define PIO_PA17C_PWMH3 (1u << 17) /**< \brief Pwm signal: PWMH3 */ |
| 7610 | #define PIO_PB14B_PWMH3 (1u << 14) /**< \brief Pwm signal: PWMH3 */ |
| 7611 | #define PIO_PC21B_PWMH3 (1u << 21) /**< \brief Pwm signal: PWMH3 */ |
| 7612 | #define PIO_PA19B_PWML0 (1u << 19) /**< \brief Pwm signal: PWML0 */ |
| 7613 | #define PIO_PB5B_PWML0 (1u << 5) /**< \brief Pwm signal: PWML0 */ |
| 7614 | #define PIO_PC0B_PWML0 (1u << 0) /**< \brief Pwm signal: PWML0 */ |
| 7615 | #define PIO_PC13B_PWML0 (1u << 13) /**< \brief Pwm signal: PWML0 */ |
| 7616 | #define PIO_PA20B_PWML1 (1u << 20) /**< \brief Pwm signal: PWML1 */ |
| 7617 | #define PIO_PB12A_PWML1 (1u << 12) /**< \brief Pwm signal: PWML1 */ |
| 7618 | #define PIO_PC1B_PWML1 (1u << 1) /**< \brief Pwm signal: PWML1 */ |
| 7619 | #define PIO_PC15B_PWML1 (1u << 15) /**< \brief Pwm signal: PWML1 */ |
| 7620 | #define PIO_PA16C_PWML2 (1u << 16) /**< \brief Pwm signal: PWML2 */ |
| 7621 | #define PIO_PA30A_PWML2 (1u << 30) /**< \brief Pwm signal: PWML2 */ |
| 7622 | #define PIO_PB13A_PWML2 (1u << 13) /**< \brief Pwm signal: PWML2 */ |
| 7623 | #define PIO_PC2B_PWML2 (1u << 2) /**< \brief Pwm signal: PWML2 */ |
| 7624 | #define PIO_PA15C_PWML3 (1u << 15) /**< \brief Pwm signal: PWML3 */ |
| 7625 | #define PIO_PC3B_PWML3 (1u << 3) /**< \brief Pwm signal: PWML3 */ |
| 7626 | #define PIO_PC22B_PWML3 (1u << 22) /**< \brief Pwm signal: PWML3 */ |
| 7627 | /* ========== Pio definition for USART0 peripheral ========== */ |
| 7628 | #define PIO_PA8A_CTS0 (1u << 8) /**< \brief Usart0 signal: CTS0 */ |
| 7629 | #define PIO_PA7A_RTS0 (1u << 7) /**< \brief Usart0 signal: RTS0 */ |
| 7630 | #define PIO_PA5A_RXD0 (1u << 5) /**< \brief Usart0 signal: RXD0 */ |
| 7631 | #define PIO_PA2B_SCK0 (1u << 2) /**< \brief Usart0 signal: SCK0 */ |
| 7632 | #define PIO_PA6A_TXD0 (1u << 6) /**< \brief Usart0 signal: TXD0 */ |
| 7633 | /* ========== Pio definition for USART1 peripheral ========== */ |
| 7634 | #define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ |
| 7635 | #define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ |
| 7636 | #define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ |
| 7637 | #define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ |
| 7638 | #define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ |
| 7639 | #define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ |
| 7640 | #define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ |
| 7641 | #define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ |
| 7642 | #define PIO_PA22A_TXD1 (1u << 22) /**< \brief Usart1 signal: TXD1 */ |
| 7643 | /* ========== Pio definition for ADC peripheral ========== */ |
| 7644 | #define PIO_PA17X1_AD0 (1u << 17) /**< \brief Adc signal: AD0 */ |
| 7645 | #define PIO_PA18X1_AD1 (1u << 18) /**< \brief Adc signal: AD1 */ |
| 7646 | #define PIO_PC13X1_AD10 (1u << 13) /**< \brief Adc signal: AD10 */ |
| 7647 | #define PIO_PC15X1_AD11 (1u << 15) /**< \brief Adc signal: AD11 */ |
| 7648 | #define PIO_PC12X1_AD12 (1u << 12) /**< \brief Adc signal: AD12 */ |
| 7649 | #define PIO_PC29X1_AD13 (1u << 29) /**< \brief Adc signal: AD13 */ |
| 7650 | #define PIO_PC30X1_AD14 (1u << 30) /**< \brief Adc signal: AD14 */ |
| 7651 | #define PIO_PA19X1_AD2_WKUP9 (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */ |
| 7652 | #define PIO_PA20X1_AD3_WKUP10 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */ |
| 7653 | #define PIO_PB0X1_AD4 (1u << 0) /**< \brief Adc signal: AD4 */ |
| 7654 | #define PIO_PB1X1_AD5 (1u << 1) /**< \brief Adc signal: AD5 */ |
| 7655 | #define PIO_PB2X1_AD6_WKUP12 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */ |
| 7656 | #define PIO_PB3X1_AD7 (1u << 3) /**< \brief Adc signal: AD7 */ |
| 7657 | #define PIO_PA21X1_AD8 (1u << 21) /**< \brief Adc signal: AD8 */ |
| 7658 | #define PIO_PA22X1_AD9 (1u << 22) /**< \brief Adc signal: AD9 */ |
| 7659 | #define PIO_PA8B_ADTRG (1u << 8) /**< \brief Adc signal: ADTRG */ |
| 7660 | /* ========== Pio definition for DACC peripheral ========== */ |
| 7661 | #define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ |
| 7662 | #define PIO_PB14X1_DAC1 (1u << 14) /**< \brief Dacc signal: DAC1 */ |
| 7663 | #define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ |
| 7664 | /* ========== Pio definition for PMC peripheral ========== */ |
| 7665 | #define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ |
| 7666 | #define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ |
| 7667 | #define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ |
| 7668 | #define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ |
| 7669 | #define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ |
| 7670 | #define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ |
| 7671 | #define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ |
| 7672 | /* ========== Pio definition for UART0 peripheral ========== */ |
| 7673 | #define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ |
| 7674 | #define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ |
| 7675 | /* ========== Pio definition for UART1 peripheral ========== */ |
| 7676 | #define PIO_PB2A_URXD1 (1u << 2) /**< \brief Uart1 signal: URXD1 */ |
| 7677 | #define PIO_PB3A_UTXD1 (1u << 3) /**< \brief Uart1 signal: UTXD1 */ |
| 7678 | /* ========== Pio definition for PIOA peripheral ========== */ |
| 7679 | #define PIO_PA24D_PIODC0 (1u << 24) /**< \brief Pioa signal: PIODC0 */ |
| 7680 | #define PIO_PA25D_PIODC1 (1u << 25) /**< \brief Pioa signal: PIODC1 */ |
| 7681 | #define PIO_PA26D_PIODC2 (1u << 26) /**< \brief Pioa signal: PIODC2 */ |
| 7682 | #define PIO_PA27D_PIODC3 (1u << 27) /**< \brief Pioa signal: PIODC3 */ |
| 7683 | #define PIO_PA28D_PIODC4 (1u << 28) /**< \brief Pioa signal: PIODC4 */ |
| 7684 | #define PIO_PA29D_PIODC5 (1u << 29) /**< \brief Pioa signal: PIODC5 */ |
| 7685 | #define PIO_PA30D_PIODC6 (1u << 30) /**< \brief Pioa signal: PIODC6 */ |
| 7686 | #define PIO_PA31D_PIODC7 (1u << 31) /**< \brief Pioa signal: PIODC7 */ |
| 7687 | #define PIO_PA23D_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */ |
| 7688 | #define PIO_PA15D_PIODCEN1 (1u << 15) /**< \brief Pioa signal: PIODCEN1 */ |
| 7689 | #define PIO_PA16D_PIODCEN2 (1u << 16) /**< \brief Pioa signal: PIODCEN2 */ |
| 7690 | /*@}*/ |
| 7691 | |
| 7692 | /* ************************************************************************** */ |
| 7693 | /* MEMORY MAPPING DEFINITIONS FOR SAM3S */ |
| 7694 | /* ************************************************************************** */ |
| 7695 | |
| 7696 | #define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ |
| 7697 | #define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ |
| 7698 | #define IRAM_ADDR (0x20000000u) /**< Internal RAM base address */ |
| 7699 | #define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ |
| 7700 | #define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ |
| 7701 | #define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ |
| 7702 | #define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ |
| 7703 | |
| 7704 | #if defined sam3s1 |
| 7705 | #define IFLASH_SIZE 0x10000 |
| 7706 | #define IFLASH_PAGE_SIZE (256) /* Internal FLASH 0 Page Size: 256 bytes */ |
| 7707 | #define IFLASH_LOCK_REGION_SIZE (16384) /* Internal FLASH 0 Lock Region Size: 16 Kbytes */ |
| 7708 | #define IFLASH_NB_OF_PAGES (256) /* Internal FLASH 0 Number of Pages: 256 */ |
| 7709 | #define IFLASH_NB_OF_LOCK_BITS (4) /* Internal FLASH 0 Number of Lock Bits: 4 */ |
| 7710 | #define IRAM_SIZE 0x4000 |
| 7711 | #elif defined sam3s2 |
| 7712 | #define IFLASH_SIZE 0x20000 |
| 7713 | #define IFLASH_PAGE_SIZE (256) /* Internal FLASH 0 Page Size: 256 bytes */ |
| 7714 | #define IFLASH_LOCK_REGION_SIZE (16384) /* Internal FLASH 0 Lock Region Size: 16 Kbytes */ |
| 7715 | #define IFLASH_NB_OF_PAGES (512) /* Internal FLASH 0 Number of Pages: 512 */ |
| 7716 | #define IFLASH_NB_OF_LOCK_BITS (8) /* Internal FLASH 0 Number of Lock Bits: 8 */ |
| 7717 | #define IRAM_SIZE 0x8000 |
| 7718 | #elif defined sam3s4 |
| 7719 | #define IFLASH_SIZE 0x40000 |
| 7720 | #define IFLASH_PAGE_SIZE (256) /* Internal FLASH 0 Page Size: 256 bytes */ |
| 7721 | #define IFLASH_LOCK_REGION_SIZE (16384) /* Internal FLASH 0 Lock Region Size: 16 Kbytes */ |
| 7722 | #define IFLASH_NB_OF_PAGES (1024) /* Internal FLASH 0 Number of Pages: 1024 */ |
| 7723 | #define IFLASH_NB_OF_LOCK_BITS (16) /* Internal FLASH 0 Number of Lock Bits: 16 */ |
| 7724 | #define IRAM_SIZE 0xC000 |
| 7725 | #else |
| 7726 | #error Library does not support the specified device. |
| 7727 | #endif |
| 7728 | |
| 7729 | #ifdef __cplusplus |
| 7730 | } |
| 7731 | #endif |
| 7732 | |
| 7733 | /*@}*/ |
| 7734 | |
| 7735 | #endif /* SAM3S_H */ |