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Kévin Redon93717e42018-07-08 13:26:15 +02001/* ----------------------------------------------------------------------------
2 * ATMEL Microcontroller Software Support
3 * ----------------------------------------------------------------------------
4 * Copyright (c) 2009, Atmel Corporation
5 *
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * - Redistributions of source code must retain the above copyright notice,
12 * this list of conditions and the disclaimer below.
13 *
14 * Atmel's name may not be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
20 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
23 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 * ----------------------------------------------------------------------------
28 */
29
30/**
31 * \file
32 *
33 * Provides the low-level initialization function that called on chip startup.
34 */
35
36/*----------------------------------------------------------------------------
37 * Headers
38 *----------------------------------------------------------------------------*/
39
40#include "board.h"
41
42/*----------------------------------------------------------------------------
43 * Local definitions
44 *----------------------------------------------------------------------------*/
45
46#define BOARD_OSCOUNT (CKGR_MOR_MOSCXTST(0x8))
47#define BOARD_MCKR (PMC_MCKR_PRES_CLK | PMC_MCKR_CSS_PLLA_CLK)
48
49#if (BOARD_MCK == 48000000)
50#if (BOARD_MAINOSC == 18432000)
51/* Clock settings at 48MHz for 18 MHz crystal */
52#define BOARD_PLLAR (CKGR_PLLAR_STUCKTO1 \
Kévin Redon33d1eb72018-07-08 13:58:12 +020053 | CKGR_PLLAR_MULA(13-1) \
54 | CKGR_PLLAR_PLLACOUNT(0x1) \
55 | CKGR_PLLAR_DIVA(5))
Kévin Redon93717e42018-07-08 13:26:15 +020056#elif (BOARD_MAINOSC == 12000000)
57/* QMod has 12 MHz clock, so multply by 8 (96 MHz) and divide by 2 */
58#define BOARD_PLLAR (CKGR_PLLAR_STUCKTO1 \
Kévin Redon33d1eb72018-07-08 13:58:12 +020059 | CKGR_PLLAR_MULA(8-1) \
60 | CKGR_PLLAR_PLLACOUNT(0x1) \
61 | CKGR_PLLAR_DIVA(2))
Kévin Redon93717e42018-07-08 13:26:15 +020062#else
63#error "Please define PLLA config for your MAINOSC frequency"
64#endif /* MAINOSC */
65#elif (BOARD_MCK == 64000000)
66#if (BOARD_MAINOSC == 18432000)
67/* Clock settings at 64MHz for 18 MHz crystal: 64.512 MHz */
68#define BOARD_PLLAR (CKGR_PLLAR_STUCKTO1 \
Kévin Redon33d1eb72018-07-08 13:58:12 +020069 | CKGR_PLLAR_MULA(7-1) \
70 | CKGR_PLLAR_PLLACOUNT(0x1) \
71 | CKGR_PLLAR_DIVA(2))
Kévin Redon93717e42018-07-08 13:26:15 +020072#elif (BOARD_MAINOSC == 12000000)
73/* QMod has 12 MHz clock, so multply by 10 / div by 2: 60 MHz */
74#define BOARD_PLLAR (CKGR_PLLAR_STUCKTO1 \
Kévin Redon33d1eb72018-07-08 13:58:12 +020075 | CKGR_PLLAR_MULA(10-1) \
76 | CKGR_PLLAR_PLLACOUNT(0x1) \
77 | CKGR_PLLAR_DIVA(2))
Kévin Redon93717e42018-07-08 13:26:15 +020078#error "Please define PLLA config for your MAINOSC frequency"
79#endif /* MAINOSC */
80#else
Kévin Redon33d1eb72018-07-08 13:58:12 +020081 #error "No PLL settings for current BOARD_MCK."
Kévin Redon93717e42018-07-08 13:26:15 +020082#endif
83
84#if (BOARD_MAINOSC == 12000000)
85#define PLLB_CFG (CKGR_PLLBR_DIVB(2)|CKGR_PLLBR_MULB(8-1)|CKGR_PLLBR_PLLBCOUNT_Msk)
86#elif (BOARD_MAINOSC == 18432000)
87#define PLLB_CFG (CKGR_PLLBR_DIVB(5)|CKGR_PLLBR_MULB(13-1)|CKGR_PLLBR_PLLBCOUNT_Msk)
88#else
89#error "Please configure PLLB for your MAINOSC freq"
90#endif
91
92/* Define clock timeout */
93#define CLOCK_TIMEOUT 0xFFFFFFFF
94
95/**
96 * \brief Configure 48MHz Clock for USB
97 */
98static void _ConfigureUsbClock(void)
99{
100 /* Enable PLLB for USB */
101 PMC->CKGR_PLLBR = PLLB_CFG;
102 while ((PMC->PMC_SR & PMC_SR_LOCKB) == 0) ;
103
104 /* USB Clock uses PLLB */
105 PMC->PMC_USB = PMC_USB_USBDIV(0) /* /1 (no divider) */
106 | PMC_USB_USBS; /* PLLB */
107}
108
109/*----------------------------------------------------------------------------
110 * Exported functions
111 *----------------------------------------------------------------------------*/
112
113/**
114 * \brief Performs the low-level initialization of the chip.
115 * This includes EFC and master clock configuration.
116 * It also enable a low level on the pin NRST triggers a user reset.
117 */
118extern WEAK void LowLevelInit( void )
119{
Kévin Redon33d1eb72018-07-08 13:58:12 +0200120 uint32_t timeout = 0;
Kévin Redon93717e42018-07-08 13:26:15 +0200121
Kévin Redon33d1eb72018-07-08 13:58:12 +0200122 /* Configure the Supply Monitor to reset the CPU in case VDDIO is
123 * lower than 3.0V. As we run the board on 3.3V, any lower voltage
124 * might be some kind of leakage that creeps in some way, but is not
125 * the "official" power supply */
126 SUPC->SUPC_SMMR = SUPC_SMMR_SMTH_3_0V | SUPC_SMMR_SMSMPL_CSM |
Kévin Redon93717e42018-07-08 13:26:15 +0200127 SUPC_SMMR_SMRSTEN_ENABLE;
128
Kévin Redon33d1eb72018-07-08 13:58:12 +0200129 /* enable both LED and green LED */
130 PIOA->PIO_PER |= PIO_LED_RED | PIO_LED_GREEN;
131 PIOA->PIO_OER |= PIO_LED_RED | PIO_LED_GREEN;
132 PIOA->PIO_CODR |= PIO_LED_RED | PIO_LED_GREEN;
Kévin Redon93717e42018-07-08 13:26:15 +0200133
Kévin Redon33d1eb72018-07-08 13:58:12 +0200134 /* Set 3 FWS for Embedded Flash Access */
135 EFC->EEFC_FMR = EEFC_FMR_FWS(3);
Kévin Redon93717e42018-07-08 13:26:15 +0200136
Kévin Redon33d1eb72018-07-08 13:58:12 +0200137 /* Select external slow clock */
Kévin Redon93717e42018-07-08 13:26:15 +0200138/* if ((SUPC->SUPC_SR & SUPC_SR_OSCSEL) != SUPC_SR_OSCSEL_CRYST)
Kévin Redon33d1eb72018-07-08 13:58:12 +0200139 {
140 SUPC->SUPC_CR = (uint32_t)(SUPC_CR_XTALSEL_CRYSTAL_SEL | SUPC_CR_KEY(0xA5));
141 timeout = 0;
142 while (!(SUPC->SUPC_SR & SUPC_SR_OSCSEL_CRYST) );
143 }
Kévin Redon93717e42018-07-08 13:26:15 +0200144*/
145
146#ifndef qmod
Kévin Redon33d1eb72018-07-08 13:58:12 +0200147 /* Initialize main oscillator */
148 if ( !(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) )
149 {
150 PMC->CKGR_MOR = CKGR_MOR_KEY(0x37) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;
151 timeout = 0;
152 while (!(PMC->PMC_SR & PMC_SR_MOSCXTS) && (timeout++ < CLOCK_TIMEOUT));
153 }
Kévin Redon93717e42018-07-08 13:26:15 +0200154
Kévin Redon33d1eb72018-07-08 13:58:12 +0200155 /* Switch to 3-20MHz Xtal oscillator */
156 PIOB->PIO_PDR = (1 << 8) | (1 << 9);
157 PIOB->PIO_PUDR = (1 << 8) | (1 << 9);
158 PIOB->PIO_PPDDR = (1 << 8) | (1 << 9);
159 PMC->CKGR_MOR = CKGR_MOR_KEY(0x37) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;
160 /* wait for Main XTAL oscillator stabilization */
161 timeout = 0;
162 while (!(PMC->PMC_SR & PMC_SR_MOSCSELS) && (timeout++ < CLOCK_TIMEOUT));
Kévin Redon93717e42018-07-08 13:26:15 +0200163#else
Kévin Redon33d1eb72018-07-08 13:58:12 +0200164 /* QMOD has external 12MHz clock source */
165 PIOB->PIO_PDR = (1 << 9);
166 PIOB->PIO_PUDR = (1 << 9);
167 PIOB->PIO_PPDDR = (1 << 9);
168 PMC->CKGR_MOR = CKGR_MOR_KEY(0x37) | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTBY| CKGR_MOR_MOSCSEL;
Kévin Redon93717e42018-07-08 13:26:15 +0200169#endif
170
Kévin Redon33d1eb72018-07-08 13:58:12 +0200171 /* disable the red LED after main clock initialization */
172 PIOA->PIO_SODR = PIO_LED_RED;
Kévin Redon93717e42018-07-08 13:26:15 +0200173
Kévin Redon33d1eb72018-07-08 13:58:12 +0200174 /* "switch" to main clock as master clock source (should already be the case */
175 PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
176 /* wait for master clock to be ready */
177 for ( timeout = 0; !(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT) ; );
Kévin Redon93717e42018-07-08 13:26:15 +0200178
Kévin Redon33d1eb72018-07-08 13:58:12 +0200179 /* Initialize PLLA */
180 PMC->CKGR_PLLAR = BOARD_PLLAR;
181 /* Wait for PLLA to lock */
182 timeout = 0;
183 while (!(PMC->PMC_SR & PMC_SR_LOCKA) && (timeout++ < CLOCK_TIMEOUT));
Kévin Redon93717e42018-07-08 13:26:15 +0200184
Kévin Redon33d1eb72018-07-08 13:58:12 +0200185 /* Switch to main clock (again ?!?) */
186 PMC->PMC_MCKR = (BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
187 /* wait for master clock to be ready */
188 for ( timeout = 0; !(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT) ; );
Kévin Redon93717e42018-07-08 13:26:15 +0200189
Kévin Redon33d1eb72018-07-08 13:58:12 +0200190 /* switch to PLLA as master clock source */
191 PMC->PMC_MCKR = BOARD_MCKR ;
192 /* wait for master clock to be ready */
193 for ( timeout = 0; !(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT) ; );
Kévin Redon93717e42018-07-08 13:26:15 +0200194
Kévin Redon33d1eb72018-07-08 13:58:12 +0200195 /* Configure SysTick for 1ms */
196 SysTick_Config(BOARD_MCK/1000);
Kévin Redon93717e42018-07-08 13:26:15 +0200197
Kévin Redon33d1eb72018-07-08 13:58:12 +0200198 _ConfigureUsbClock();
Kévin Redon93717e42018-07-08 13:26:15 +0200199}
200
201/* SysTick based delay function */
202
203volatile uint32_t jiffies;
204
205/* Interrupt handler for SysTick interrupt */
206void SysTick_Handler(void)
207{
208 jiffies++;
209}
210
211void mdelay(unsigned int msecs)
212{
213 uint32_t jiffies_start = jiffies;
214 do {
215 } while ((jiffies - jiffies_start) < msecs);
216}