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gerrit.osmocom.org / osmo-sgsn / ce49258a12019d2c7cb53d07e3c9b4ffbc20f561 / . / openbsc / src / libbsc / abis_om2000.c
blob: 9bf0fe2b9baaca1d8643f51a0141d5e6cb41f9a1 [file] [log] [blame]
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]1/* Ericsson RBS 2xxx GSM O&M (OM2000) messages on the A-bis interface
2 * implemented based on protocol trace analysis, no formal documentation */
3
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]4/* (C) 2010-2011,2016 by Harald Welte <laforge@gnumonks.org>
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]5 *
6 * All Rights Reserved
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU Affero General Public License as published by
10 * the Free Software Foundation; either version 3 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU Affero General Public License for more details.
17 *
18 * You should have received a copy of the GNU Affero General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 *
21 */
22
23
24#include <errno.h>
25#include <unistd.h>
26#include <stdio.h>
27#include <stdlib.h>
28#include <time.h>
29#include <stdint.h>
30
31#include <arpa/inet.h>
32
Pablo Neira Ayuso136f4532011-03-22 16:47:59 +0100[diff] [blame]33#include <osmocom/core/msgb.h>
34#include <osmocom/gsm/tlv.h>
35#include <osmocom/core/talloc.h>
36#include <osmocom/core/utils.h>
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]37#include <osmocom/core/fsm.h>
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]38
39#include <openbsc/gsm_data.h>
40#include <openbsc/debug.h>
41#include <openbsc/abis_nm.h>
Harald Welte80ccb952016-11-15 23:23:42 +0100[diff] [blame]42#include <openbsc/abis_rsl.h>
Harald Welte73541072011-02-12 13:44:14 +0100[diff] [blame]43#include <openbsc/abis_om2000.h>
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]44#include <openbsc/signal.h>
Pablo Neira Ayusoed5cacb2011-08-17 22:44:07 +0200[diff] [blame]45#include <osmocom/abis/e1_input.h>
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]46
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]47/* FIXME: move to libosmocore */
48struct osmo_fsm_inst *osmo_fsm_inst_alloc_child_id(struct osmo_fsm *fsm,
49 struct osmo_fsm_inst *parent,
50 uint32_t parent_term_event,
51 const char *id)
52{
53 struct osmo_fsm_inst *fi;
54
55 fi = osmo_fsm_inst_alloc(fsm, parent, NULL, parent->log_level,
56 id ? id : parent->id);
57 if (!fi) {
58 /* indicate immediate termination to caller */
59 osmo_fsm_inst_dispatch(parent, parent_term_event, NULL);
60 return NULL;
61 }
62
63 LOGPFSM(fi, "is child of %s\n", osmo_fsm_inst_name(parent));
64
65 fi->proc.parent = parent;
66 fi->proc.parent_term_event = parent_term_event;
67 llist_add(&fi->proc.child, &parent->proc.children);
68
69 return fi;
70}
71
72
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]73#define OM_ALLOC_SIZE 1024
74#define OM_HEADROOM_SIZE 128
75
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]76#define OM2K_TIMEOUT 10
77#define TRX_FSM_TIMEOUT 60
78#define BTS_FSM_TIMEOUT 60
79
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]80/* use following functions from abis_nm.c:
81 * om2k_msgb_alloc()
Harald Weltebc867d92011-02-12 13:09:38 +0100[diff] [blame]82 * abis_om2k_sendmsg()
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]83 */
84
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]85struct abis_om2k_hdr {
86 struct abis_om_hdr om;
87 uint16_t msg_type;
88 struct abis_om2k_mo mo;
89 uint8_t data[0];
90} __attribute__ ((packed));
91
92enum abis_om2k_msgtype {
93 OM2K_MSGT_ABORT_SP_CMD = 0x0000,
94 OM2K_MSGT_ABORT_SP_COMPL = 0x0002,
95 OM2K_MSGT_ALARM_REP_ACK = 0x0004,
96 OM2K_MSGT_ALARM_REP_NACK = 0x0005,
97 OM2K_MSGT_ALARM_REP = 0x0006,
98 OM2K_MSGT_ALARM_STATUS_REQ = 0x0008,
99 OM2K_MSGT_ALARM_STATUS_REQ_ACK = 0x000a,
100 OM2K_MSGT_ALARM_STATUS_REQ_REJ = 0x000b,
101 OM2K_MSGT_ALARM_STATUS_RES_ACK = 0x000c,
102 OM2K_MSGT_ALARM_STATUS_RES_NACK = 0x000d,
103 OM2K_MSGT_ALARM_STATUS_RES = 0x000e,
104 OM2K_MSGT_CAL_TIME_RESP = 0x0010,
105 OM2K_MSGT_CAL_TIME_REJ = 0x0011,
106 OM2K_MSGT_CAL_TIME_REQ = 0x0012,
107
Harald Weltefdb71942011-02-14 15:31:43 +0100[diff] [blame]108 OM2K_MSGT_CON_CONF_REQ = 0x0014,
109 OM2K_MSGT_CON_CONF_REQ_ACK = 0x0016,
110 OM2K_MSGT_CON_CONF_REQ_REJ = 0x0017,
111 OM2K_MSGT_CON_CONF_RES_ACK = 0x0018,
112 OM2K_MSGT_CON_CONF_RES_NACK = 0x0019,
113 OM2K_MSGT_CON_CONF_RES = 0x001a,
114
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]115 OM2K_MSGT_CONNECT_CMD = 0x001c,
116 OM2K_MSGT_CONNECT_COMPL = 0x001e,
117 OM2K_MSGT_CONNECT_REJ = 0x001f,
118
Harald Welte0741ffe2011-02-12 18:48:53 +0100[diff] [blame]119 OM2K_MSGT_DISABLE_REQ = 0x0028,
120 OM2K_MSGT_DISABLE_REQ_ACK = 0x002a,
121 OM2K_MSGT_DISABLE_REQ_REJ = 0x002b,
122 OM2K_MSGT_DISABLE_RES_ACK = 0x002c,
123 OM2K_MSGT_DISABLE_RES_NACK = 0x002d,
124 OM2K_MSGT_DISABLE_RES = 0x002e,
Harald Welte6fec79d2011-02-12 14:57:17 +0100[diff] [blame]125 OM2K_MSGT_DISCONNECT_CMD = 0x0030,
126 OM2K_MSGT_DISCONNECT_COMPL = 0x0032,
127 OM2K_MSGT_DISCONNECT_REJ = 0x0033,
Harald Welte0741ffe2011-02-12 18:48:53 +0100[diff] [blame]128 OM2K_MSGT_ENABLE_REQ = 0x0034,
129 OM2K_MSGT_ENABLE_REQ_ACK = 0x0036,
130 OM2K_MSGT_ENABLE_REQ_REJ = 0x0037,
131 OM2K_MSGT_ENABLE_RES_ACK = 0x0038,
132 OM2K_MSGT_ENABLE_RES_NACK = 0x0039,
133 OM2K_MSGT_ENABLE_RES = 0x003a,
Harald Welte6fec79d2011-02-12 14:57:17 +0100[diff] [blame]134
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]135 OM2K_MSGT_FAULT_REP_ACK = 0x0040,
136 OM2K_MSGT_FAULT_REP_NACK = 0x0041,
137 OM2K_MSGT_FAULT_REP = 0x0042,
138
139 OM2K_MSGT_IS_CONF_REQ = 0x0060,
140 OM2K_MSGT_IS_CONF_REQ_ACK = 0x0062,
141 OM2K_MSGT_IS_CONF_REQ_REJ = 0x0063,
142 OM2K_MSGT_IS_CONF_RES_ACK = 0x0064,
143 OM2K_MSGT_IS_CONF_RES_NACK = 0x0065,
144 OM2K_MSGT_IS_CONF_RES = 0x0066,
145
146 OM2K_MSGT_OP_INFO = 0x0074,
147 OM2K_MSGT_OP_INFO_ACK = 0x0076,
148 OM2K_MSGT_OP_INFO_REJ = 0x0077,
149 OM2K_MSGT_RESET_CMD = 0x0078,
150 OM2K_MSGT_RESET_COMPL = 0x007a,
151 OM2K_MSGT_RESET_REJ = 0x007b,
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]152 OM2K_MSGT_RX_CONF_REQ = 0x007c,
153 OM2K_MSGT_RX_CONF_REQ_ACK = 0x007e,
154 OM2K_MSGT_RX_CONF_REQ_REJ = 0x007f,
155 OM2K_MSGT_RX_CONF_RES_ACK = 0x0080,
156 OM2K_MSGT_RX_CONF_RES_NACK = 0x0081,
157 OM2K_MSGT_RX_CONF_RES = 0x0082,
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]158 OM2K_MSGT_START_REQ = 0x0084,
159 OM2K_MSGT_START_REQ_ACK = 0x0086,
160 OM2K_MSGT_START_REQ_REJ = 0x0087,
161 OM2K_MSGT_START_RES_ACK = 0x0088,
162 OM2K_MSGT_START_RES_NACK = 0x0089,
163 OM2K_MSGT_START_RES = 0x008a,
Harald Weltee1d5eca2011-02-12 14:42:59 +0100[diff] [blame]164 OM2K_MSGT_STATUS_REQ = 0x008c,
165 OM2K_MSGT_STATUS_RESP = 0x008e,
166 OM2K_MSGT_STATUS_REJ = 0x008f,
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]167
Harald Welte8024d8f2011-02-12 15:07:30 +0100[diff] [blame]168 OM2K_MSGT_TEST_REQ = 0x0094,
169 OM2K_MSGT_TEST_REQ_ACK = 0x0096,
170 OM2K_MSGT_TEST_REQ_REJ = 0x0097,
171 OM2K_MSGT_TEST_RES_ACK = 0x0098,
172 OM2K_MSGT_TEST_RES_NACK = 0x0099,
173 OM2K_MSGT_TEST_RES = 0x009a,
174
Harald Weltef9cf9612011-03-05 14:36:47 +0100[diff] [blame]175 OM2K_MSGT_TF_CONF_REQ = 0x00a0,
176 OM2K_MSGT_TF_CONF_REQ_ACK = 0x00a2,
177 OM2K_MSGT_TF_CONF_REQ_REJ = 0x00a3,
178 OM2K_MSGT_TF_CONF_RES_ACK = 0x00a4,
179 OM2K_MSGT_TF_CONF_RES_NACK = 0x00a5,
180 OM2K_MSGT_TF_CONF_RES = 0x00a6,
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]181 OM2K_MSGT_TS_CONF_REQ = 0x00a8,
182 OM2K_MSGT_TS_CONF_REQ_ACK = 0x00aa,
183 OM2K_MSGT_TS_CONF_REQ_REJ = 0x00ab,
184 OM2K_MSGT_TS_CONF_RES_ACK = 0x00ac,
185 OM2K_MSGT_TS_CONF_RES_NACK = 0x00ad,
186 OM2K_MSGT_TS_CONF_RES = 0x00ae,
187 OM2K_MSGT_TX_CONF_REQ = 0x00b0,
188 OM2K_MSGT_TX_CONF_REQ_ACK = 0x00b2,
189 OM2K_MSGT_TX_CONF_REQ_REJ = 0x00b3,
190 OM2K_MSGT_TX_CONF_RES_ACK = 0x00b4,
191 OM2K_MSGT_TX_CONF_RES_NACK = 0x00b5,
192 OM2K_MSGT_TX_CONF_RES = 0x00b6,
193
root45799782016-10-15 21:24:57 +0200[diff] [blame]194 OM2K_MSGT_CAPA_REQ = 0x00e8,
195 OM2K_MSGT_CAPA_REQ_ACK = 0x00ea,
196 OM2K_MSGT_CAPA_REQ_REJ = 0x00eb,
197 OM2K_MSGT_CAPA_RES = 0x00ee,
198 OM2K_MSGT_CAPA_RES_ACK = 0x00ec,
199 OM2K_MSGT_CAPA_RES_NACK = 0x00ed,
200
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]201 OM2K_MSGT_NEGOT_REQ_ACK = 0x0104,
202 OM2K_MSGT_NEGOT_REQ_NACK = 0x0105,
203 OM2K_MSGT_NEGOT_REQ = 0x0106,
204};
205
206enum abis_om2k_dei {
Harald Weltee898ecc2011-03-06 19:26:11 +0100[diff] [blame]207 OM2K_DEI_ACCORDANCE_IND = 0x00,
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]208 OM2K_DEI_BCC = 0x06,
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]209 OM2K_DEI_BS_AG_BKS_RES = 0x07,
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]210 OM2K_DEI_BSIC = 0x09,
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]211 OM2K_DEI_BA_PA_MFRMS = 0x0a,
212 OM2K_DEI_CBCH_INDICATOR = 0x0b,
213 OM2K_DEI_CCCH_OPTIONS = 0x0c,
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]214 OM2K_DEI_CAL_TIME = 0x0d,
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]215 OM2K_DEI_COMBINATION = 0x0f,
Harald Weltefdb71942011-02-14 15:31:43 +0100[diff] [blame]216 OM2K_DEI_CON_CONN_LIST = 0x10,
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]217 OM2K_DEI_DRX_DEV_MAX = 0x12,
Harald Welte8bcb1a02011-02-12 20:23:40 +0100[diff] [blame]218 OM2K_DEI_END_LIST_NR = 0x13,
Harald Weltef6d6b212011-03-05 20:13:52 +0100[diff] [blame]219 OM2K_DEI_EXT_COND_MAP_1 = 0x14,
220 OM2K_DEI_EXT_COND_MAP_2 = 0x15,
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]221 OM2K_DEI_FILLING_MARKER = 0x1c,
222 OM2K_DEI_FN_OFFSET = 0x1d,
223 OM2K_DEI_FREQ_LIST = 0x1e,
224 OM2K_DEI_FREQ_SPEC_RX = 0x1f,
225 OM2K_DEI_FREQ_SPEC_TX = 0x20,
226 OM2K_DEI_HSN = 0x21,
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]227 OM2K_DEI_ICM_INDICATOR = 0x22,
Harald Weltef6d6b212011-03-05 20:13:52 +0100[diff] [blame]228 OM2K_DEI_INT_FAULT_MAP_1A = 0x23,
229 OM2K_DEI_INT_FAULT_MAP_1B = 0x24,
230 OM2K_DEI_INT_FAULT_MAP_2A = 0x25,
231 OM2K_DEI_INT_FAULT_MAP_2A_EXT = 0x26,
Harald Welte8bcb1a02011-02-12 20:23:40 +0100[diff] [blame]232 OM2K_DEI_IS_CONN_LIST = 0x27,
233 OM2K_DEI_LIST_NR = 0x28,
Harald Weltef6d6b212011-03-05 20:13:52 +0100[diff] [blame]234 OM2K_DEI_LOCAL_ACCESS = 0x2a,
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]235 OM2K_DEI_MAIO = 0x2b,
Harald Weltef6d6b212011-03-05 20:13:52 +0100[diff] [blame]236 OM2K_DEI_MO_STATE = 0x2c,
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]237 OM2K_DEI_NY1 = 0x2d,
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]238 OM2K_DEI_OP_INFO = 0x2e,
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]239 OM2K_DEI_POWER = 0x2f,
Harald Weltee6e83832011-03-05 17:52:09 +0100[diff] [blame]240 OM2K_DEI_REASON_CODE = 0x32,
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]241 OM2K_DEI_RX_DIVERSITY = 0x33,
Philipp8136e4b2016-10-19 10:14:35 +0200[diff] [blame]242 OM2K_DEI_REPL_UNIT_MAP = 0x34,
Harald Weltee6e83832011-03-05 17:52:09 +0100[diff] [blame]243 OM2K_DEI_RESULT_CODE = 0x35,
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]244 OM2K_DEI_T3105 = 0x38,
Harald Weltef9cf9612011-03-05 14:36:47 +0100[diff] [blame]245 OM2K_DEI_TF_MODE = 0x3a,
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]246 OM2K_DEI_TS_NR = 0x3c,
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]247 OM2K_DEI_TSC = 0x3d,
Harald Weltef6d6b212011-03-05 20:13:52 +0100[diff] [blame]248 OM2K_DEI_BTS_VERSION = 0x40,
249 OM2K_DEI_OML_IWD_VERSION = 0x41,
250 OM2K_DEI_RSL_IWD_VERSION = 0x42,
251 OM2K_DEI_OML_FUNC_MAP_1 = 0x43,
252 OM2K_DEI_OML_FUNC_MAP_2 = 0x44,
253 OM2K_DEI_RSL_FUNC_MAP_1 = 0x45,
254 OM2K_DEI_RSL_FUNC_MAP_2 = 0x46,
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]255 OM2K_DEI_EXT_RANGE = 0x47,
Harald Weltef6d6b212011-03-05 20:13:52 +0100[diff] [blame]256 OM2K_DEI_REQ_IND = 0x48,
Philipp8136e4b2016-10-19 10:14:35 +0200[diff] [blame]257 OM2K_DEI_REPL_UNIT_MAP_EXT = 0x50,
Harald Welte75755c52011-03-05 20:38:35 +0100[diff] [blame]258 OM2K_DEI_ICM_BOUND_PARAMS = 0x74,
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]259 OM2K_DEI_LSC = 0x79,
260 OM2K_DEI_LSC_FILT_TIME = 0x7a,
261 OM2K_DEI_CALL_SUPV_TIME = 0x7b,
Harald Welte75755c52011-03-05 20:38:35 +0100[diff] [blame]262 OM2K_DEI_ICM_CHAN_RATE = 0x7e,
Harald Weltef6d6b212011-03-05 20:13:52 +0100[diff] [blame]263 OM2K_DEI_HW_INFO_SIG = 0x84,
Harald Welteba9adbb2011-03-06 19:01:16 +0100[diff] [blame]264 OM2K_DEI_TF_SYNC_SRC = 0x86,
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]265 OM2K_DEI_TTA = 0x87,
Harald Weltef6d6b212011-03-05 20:13:52 +0100[diff] [blame]266 OM2K_DEI_CAPA_SIG = 0x8a,
Harald Welte73541072011-02-12 13:44:14 +0100[diff] [blame]267 OM2K_DEI_NEGOT_REC1 = 0x90,
268 OM2K_DEI_NEGOT_REC2 = 0x91,
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]269 OM2K_DEI_ENCR_ALG = 0x92,
270 OM2K_DEI_INTERF_REJ_COMB = 0x94,
Harald Weltef9cf9612011-03-05 14:36:47 +0100[diff] [blame]271 OM2K_DEI_FS_OFFSET = 0x98,
Harald Weltef6d6b212011-03-05 20:13:52 +0100[diff] [blame]272 OM2K_DEI_EXT_COND_MAP_2_EXT = 0x9c,
Philipp8136e4b2016-10-19 10:14:35 +0200[diff] [blame]273 OM2K_DEI_TSS_MO_STATE = 0x9d,
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]274};
275
Harald Weltee6e83832011-03-05 17:52:09 +0100[diff] [blame]276const struct tlv_definition om2k_att_tlvdef = {
277 .def = {
Harald Weltee898ecc2011-03-06 19:26:11 +0100[diff] [blame]278 [OM2K_DEI_ACCORDANCE_IND] = { TLV_TYPE_TV },
Harald Weltee6e83832011-03-05 17:52:09 +0100[diff] [blame]279 [OM2K_DEI_BCC] = { TLV_TYPE_TV },
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]280 [OM2K_DEI_BS_AG_BKS_RES] = { TLV_TYPE_TV },
Harald Weltee6e83832011-03-05 17:52:09 +0100[diff] [blame]281 [OM2K_DEI_BSIC] = { TLV_TYPE_TV },
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]282 [OM2K_DEI_BA_PA_MFRMS] = { TLV_TYPE_TV },
283 [OM2K_DEI_CBCH_INDICATOR] = { TLV_TYPE_TV },
Harald Weltef6d6b212011-03-05 20:13:52 +0100[diff] [blame]284 [OM2K_DEI_INT_FAULT_MAP_1A] = { TLV_TYPE_FIXED, 6 },
285 [OM2K_DEI_INT_FAULT_MAP_1B] = { TLV_TYPE_FIXED, 6 },
286 [OM2K_DEI_INT_FAULT_MAP_2A] = { TLV_TYPE_FIXED, 6 },
287 [OM2K_DEI_INT_FAULT_MAP_2A_EXT]={ TLV_TYPE_FIXED, 6 },
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]288 [OM2K_DEI_CCCH_OPTIONS] = { TLV_TYPE_TV },
Harald Weltee6e83832011-03-05 17:52:09 +0100[diff] [blame]289 [OM2K_DEI_CAL_TIME] = { TLV_TYPE_FIXED, 6 },
290 [OM2K_DEI_COMBINATION] = { TLV_TYPE_TV },
291 [OM2K_DEI_CON_CONN_LIST] = { TLV_TYPE_TLV },
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]292 [OM2K_DEI_DRX_DEV_MAX] = { TLV_TYPE_TV },
Harald Weltee6e83832011-03-05 17:52:09 +0100[diff] [blame]293 [OM2K_DEI_END_LIST_NR] = { TLV_TYPE_TV },
Harald Weltef6d6b212011-03-05 20:13:52 +0100[diff] [blame]294 [OM2K_DEI_EXT_COND_MAP_1] = { TLV_TYPE_FIXED, 2 },
295 [OM2K_DEI_EXT_COND_MAP_2] = { TLV_TYPE_FIXED, 2 },
Harald Weltee6e83832011-03-05 17:52:09 +0100[diff] [blame]296 [OM2K_DEI_FILLING_MARKER] = { TLV_TYPE_TV },
297 [OM2K_DEI_FN_OFFSET] = { TLV_TYPE_FIXED, 2 },
298 [OM2K_DEI_FREQ_LIST] = { TLV_TYPE_TLV },
299 [OM2K_DEI_FREQ_SPEC_RX] = { TLV_TYPE_FIXED, 2 },
300 [OM2K_DEI_FREQ_SPEC_TX] = { TLV_TYPE_FIXED, 2 },
301 [OM2K_DEI_HSN] = { TLV_TYPE_TV },
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]302 [OM2K_DEI_ICM_INDICATOR] = { TLV_TYPE_TV },
Harald Weltee6e83832011-03-05 17:52:09 +0100[diff] [blame]303 [OM2K_DEI_IS_CONN_LIST] = { TLV_TYPE_TLV },
304 [OM2K_DEI_LIST_NR] = { TLV_TYPE_TV },
Harald Weltef6d6b212011-03-05 20:13:52 +0100[diff] [blame]305 [OM2K_DEI_LOCAL_ACCESS] = { TLV_TYPE_TV },
Harald Weltee6e83832011-03-05 17:52:09 +0100[diff] [blame]306 [OM2K_DEI_MAIO] = { TLV_TYPE_TV },
Harald Weltef6d6b212011-03-05 20:13:52 +0100[diff] [blame]307 [OM2K_DEI_MO_STATE] = { TLV_TYPE_TV },
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]308 [OM2K_DEI_NY1] = { TLV_TYPE_TV },
Harald Weltee6e83832011-03-05 17:52:09 +0100[diff] [blame]309 [OM2K_DEI_OP_INFO] = { TLV_TYPE_TV },
310 [OM2K_DEI_POWER] = { TLV_TYPE_TV },
311 [OM2K_DEI_REASON_CODE] = { TLV_TYPE_TV },
312 [OM2K_DEI_RX_DIVERSITY] = { TLV_TYPE_TV },
313 [OM2K_DEI_RESULT_CODE] = { TLV_TYPE_TV },
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]314 [OM2K_DEI_T3105] = { TLV_TYPE_TV },
Harald Weltee6e83832011-03-05 17:52:09 +0100[diff] [blame]315 [OM2K_DEI_TF_MODE] = { TLV_TYPE_TV },
316 [OM2K_DEI_TS_NR] = { TLV_TYPE_TV },
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]317 [OM2K_DEI_TSC] = { TLV_TYPE_TV },
Harald Weltef6d6b212011-03-05 20:13:52 +0100[diff] [blame]318 [OM2K_DEI_BTS_VERSION] = { TLV_TYPE_FIXED, 12 },
319 [OM2K_DEI_OML_IWD_VERSION] = { TLV_TYPE_FIXED, 6 },
320 [OM2K_DEI_RSL_IWD_VERSION] = { TLV_TYPE_FIXED, 6 },
321 [OM2K_DEI_OML_FUNC_MAP_1] = { TLV_TYPE_TLV },
322 [OM2K_DEI_OML_FUNC_MAP_2] = { TLV_TYPE_TLV },
323 [OM2K_DEI_RSL_FUNC_MAP_1] = { TLV_TYPE_TLV },
324 [OM2K_DEI_RSL_FUNC_MAP_2] = { TLV_TYPE_TLV },
Harald Weltee6e83832011-03-05 17:52:09 +0100[diff] [blame]325 [OM2K_DEI_EXT_RANGE] = { TLV_TYPE_TV },
Harald Weltef6d6b212011-03-05 20:13:52 +0100[diff] [blame]326 [OM2K_DEI_REQ_IND] = { TLV_TYPE_TV },
327 [OM2K_DEI_REPL_UNIT_MAP] = { TLV_TYPE_FIXED, 6 },
Philipp8136e4b2016-10-19 10:14:35 +0200[diff] [blame]328 [OM2K_DEI_REPL_UNIT_MAP_EXT] = {TLV_TYPE_FIXED, 6},
Harald Welte75755c52011-03-05 20:38:35 +0100[diff] [blame]329 [OM2K_DEI_ICM_BOUND_PARAMS] = { TLV_TYPE_FIXED, 5 },
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]330 [OM2K_DEI_LSC] = { TLV_TYPE_TV },
331 [OM2K_DEI_LSC_FILT_TIME] = { TLV_TYPE_TV },
332 [OM2K_DEI_CALL_SUPV_TIME] = { TLV_TYPE_TV },
Harald Welte75755c52011-03-05 20:38:35 +0100[diff] [blame]333 [OM2K_DEI_ICM_CHAN_RATE] = { TLV_TYPE_TV },
Harald Weltef6d6b212011-03-05 20:13:52 +0100[diff] [blame]334 [OM2K_DEI_HW_INFO_SIG] = { TLV_TYPE_FIXED, 2 },
Harald Welteba9adbb2011-03-06 19:01:16 +0100[diff] [blame]335 [OM2K_DEI_TF_SYNC_SRC] = { TLV_TYPE_TV },
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]336 [OM2K_DEI_TTA] = { TLV_TYPE_TV },
Harald Weltef6d6b212011-03-05 20:13:52 +0100[diff] [blame]337 [OM2K_DEI_CAPA_SIG] = { TLV_TYPE_FIXED, 2 },
Harald Weltee6e83832011-03-05 17:52:09 +0100[diff] [blame]338 [OM2K_DEI_NEGOT_REC1] = { TLV_TYPE_TLV },
339 [OM2K_DEI_NEGOT_REC2] = { TLV_TYPE_TLV },
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]340 [OM2K_DEI_ENCR_ALG] = { TLV_TYPE_TV },
341 [OM2K_DEI_INTERF_REJ_COMB] = { TLV_TYPE_TV },
Harald Weltee6e83832011-03-05 17:52:09 +0100[diff] [blame]342 [OM2K_DEI_FS_OFFSET] = { TLV_TYPE_FIXED, 5 },
Harald Weltef6d6b212011-03-05 20:13:52 +0100[diff] [blame]343 [OM2K_DEI_EXT_COND_MAP_2_EXT] = { TLV_TYPE_FIXED, 4 },
Philipp8136e4b2016-10-19 10:14:35 +0200[diff] [blame]344 [OM2K_DEI_TSS_MO_STATE] = { TLV_TYPE_FIXED, 4 },
Harald Weltee6e83832011-03-05 17:52:09 +0100[diff] [blame]345 },
346};
347
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]348static const struct value_string om2k_msgcode_vals[] = {
349 { 0x0000, "Abort SP Command" },
350 { 0x0002, "Abort SP Complete" },
351 { 0x0004, "Alarm Report ACK" },
352 { 0x0005, "Alarm Report NACK" },
353 { 0x0006, "Alarm Report" },
354 { 0x0008, "Alarm Status Request" },
355 { 0x000a, "Alarm Status Request Accept" },
356 { 0x000b, "Alarm Status Request Reject" },
357 { 0x000c, "Alarm Status Result ACK" },
358 { 0x000d, "Alarm Status Result NACK" },
359 { 0x000e, "Alarm Status Result" },
360 { 0x0010, "Calendar Time Response" },
361 { 0x0011, "Calendar Time Reject" },
362 { 0x0012, "Calendar Time Request" },
363 { 0x0014, "CON Configuration Request" },
364 { 0x0016, "CON Configuration Request Accept" },
365 { 0x0017, "CON Configuration Request Reject" },
366 { 0x0018, "CON Configuration Result ACK" },
367 { 0x0019, "CON Configuration Result NACK" },
368 { 0x001a, "CON Configuration Result" },
369 { 0x001c, "Connect Command" },
370 { 0x001e, "Connect Complete" },
Harald Welte3ede7232011-03-05 17:58:13 +0100[diff] [blame]371 { 0x001f, "Connect Reject" },
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]372 { 0x0028, "Disable Request" },
373 { 0x002a, "Disable Request Accept" },
374 { 0x002b, "Disable Request Reject" },
375 { 0x002c, "Disable Result ACK" },
376 { 0x002d, "Disable Result NACK" },
377 { 0x002e, "Disable Result" },
378 { 0x0030, "Disconnect Command" },
379 { 0x0032, "Disconnect Complete" },
380 { 0x0033, "Disconnect Reject" },
381 { 0x0034, "Enable Request" },
382 { 0x0036, "Enable Request Accept" },
383 { 0x0037, "Enable Request Reject" },
384 { 0x0038, "Enable Result ACK" },
385 { 0x0039, "Enable Result NACK" },
386 { 0x003a, "Enable Result" },
387 { 0x003c, "Escape Downlink Normal" },
388 { 0x003d, "Escape Downlink NACK" },
389 { 0x003e, "Escape Uplink Normal" },
390 { 0x003f, "Escape Uplink NACK" },
391 { 0x0040, "Fault Report ACK" },
392 { 0x0041, "Fault Report NACK" },
393 { 0x0042, "Fault Report" },
394 { 0x0044, "File Package End Command" },
395 { 0x0046, "File Package End Result" },
396 { 0x0047, "File Package End Reject" },
397 { 0x0048, "File Relation Request" },
398 { 0x004a, "File Relation Response" },
399 { 0x004b, "File Relation Request Reject" },
400 { 0x004c, "File Segment Transfer" },
401 { 0x004e, "File Segment Transfer Complete" },
402 { 0x004f, "File Segment Transfer Reject" },
403 { 0x0050, "HW Information Request" },
404 { 0x0052, "HW Information Request Accept" },
405 { 0x0053, "HW Information Request Reject" },
406 { 0x0054, "HW Information Result ACK" },
407 { 0x0055, "HW Information Result NACK" },
408 { 0x0056, "HW Information Result" },
409 { 0x0060, "IS Configuration Request" },
410 { 0x0062, "IS Configuration Request Accept" },
411 { 0x0063, "IS Configuration Request Reject" },
412 { 0x0064, "IS Configuration Result ACK" },
413 { 0x0065, "IS Configuration Result NACK" },
414 { 0x0066, "IS Configuration Result" },
415 { 0x0068, "Load Data End" },
416 { 0x006a, "Load Data End Result" },
417 { 0x006b, "Load Data End Reject" },
418 { 0x006c, "Load Data Init" },
419 { 0x006e, "Load Data Init Accept" },
420 { 0x006f, "Load Data Init Reject" },
421 { 0x0070, "Loop Control Command" },
422 { 0x0072, "Loop Control Complete" },
423 { 0x0073, "Loop Control Reject" },
424 { 0x0074, "Operational Information" },
425 { 0x0076, "Operational Information Accept" },
426 { 0x0077, "Operational Information Reject" },
427 { 0x0078, "Reset Command" },
428 { 0x007a, "Reset Complete" },
429 { 0x007b, "Reset Reject" },
430 { 0x007c, "RX Configuration Request" },
431 { 0x007e, "RX Configuration Request Accept" },
432 { 0x007f, "RX Configuration Request Reject" },
433 { 0x0080, "RX Configuration Result ACK" },
434 { 0x0081, "RX Configuration Result NACK" },
435 { 0x0082, "RX Configuration Result" },
436 { 0x0084, "Start Request" },
437 { 0x0086, "Start Request Accept" },
438 { 0x0087, "Start Request Reject" },
439 { 0x0088, "Start Result ACK" },
440 { 0x0089, "Start Result NACK" },
441 { 0x008a, "Start Result" },
442 { 0x008c, "Status Request" },
443 { 0x008e, "Status Response" },
444 { 0x008f, "Status Reject" },
445 { 0x0094, "Test Request" },
446 { 0x0096, "Test Request Accept" },
447 { 0x0097, "Test Request Reject" },
448 { 0x0098, "Test Result ACK" },
449 { 0x0099, "Test Result NACK" },
450 { 0x009a, "Test Result" },
451 { 0x00a0, "TF Configuration Request" },
452 { 0x00a2, "TF Configuration Request Accept" },
453 { 0x00a3, "TF Configuration Request Reject" },
454 { 0x00a4, "TF Configuration Result ACK" },
455 { 0x00a5, "TF Configuration Result NACK" },
456 { 0x00a6, "TF Configuration Result" },
457 { 0x00a8, "TS Configuration Request" },
458 { 0x00aa, "TS Configuration Request Accept" },
459 { 0x00ab, "TS Configuration Request Reject" },
460 { 0x00ac, "TS Configuration Result ACK" },
461 { 0x00ad, "TS Configuration Result NACK" },
462 { 0x00ae, "TS Configuration Result" },
463 { 0x00b0, "TX Configuration Request" },
464 { 0x00b2, "TX Configuration Request Accept" },
465 { 0x00b3, "TX Configuration Request Reject" },
466 { 0x00b4, "TX Configuration Result ACK" },
467 { 0x00b5, "TX Configuration Result NACK" },
468 { 0x00b6, "TX Configuration Result" },
469 { 0x00bc, "DIP Alarm Report ACK" },
470 { 0x00bd, "DIP Alarm Report NACK" },
471 { 0x00be, "DIP Alarm Report" },
472 { 0x00c0, "DIP Alarm Status Request" },
473 { 0x00c2, "DIP Alarm Status Response" },
474 { 0x00c3, "DIP Alarm Status Reject" },
475 { 0x00c4, "DIP Quality Report I ACK" },
476 { 0x00c5, "DIP Quality Report I NACK" },
477 { 0x00c6, "DIP Quality Report I" },
478 { 0x00c8, "DIP Quality Report II ACK" },
479 { 0x00c9, "DIP Quality Report II NACK" },
480 { 0x00ca, "DIP Quality Report II" },
481 { 0x00dc, "DP Configuration Request" },
482 { 0x00de, "DP Configuration Request Accept" },
483 { 0x00df, "DP Configuration Request Reject" },
484 { 0x00e0, "DP Configuration Result ACK" },
485 { 0x00e1, "DP Configuration Result NACK" },
486 { 0x00e2, "DP Configuration Result" },
487 { 0x00e4, "Capabilities HW Info Report ACK" },
488 { 0x00e5, "Capabilities HW Info Report NACK" },
489 { 0x00e6, "Capabilities HW Info Report" },
490 { 0x00e8, "Capabilities Request" },
491 { 0x00ea, "Capabilities Request Accept" },
492 { 0x00eb, "Capabilities Request Reject" },
493 { 0x00ec, "Capabilities Result ACK" },
494 { 0x00ed, "Capabilities Result NACK" },
495 { 0x00ee, "Capabilities Result" },
496 { 0x00f0, "FM Configuration Request" },
497 { 0x00f2, "FM Configuration Request Accept" },
498 { 0x00f3, "FM Configuration Request Reject" },
499 { 0x00f4, "FM Configuration Result ACK" },
500 { 0x00f5, "FM Configuration Result NACK" },
501 { 0x00f6, "FM Configuration Result" },
502 { 0x00f8, "FM Report Request" },
503 { 0x00fa, "FM Report Response" },
504 { 0x00fb, "FM Report Reject" },
505 { 0x00fc, "FM Start Command" },
506 { 0x00fe, "FM Start Complete" },
507 { 0x00ff, "FM Start Reject" },
508 { 0x0100, "FM Stop Command" },
509 { 0x0102, "FM Stop Complete" },
510 { 0x0103, "FM Stop Reject" },
511 { 0x0104, "Negotiation Request ACK" },
512 { 0x0105, "Negotiation Request NACK" },
513 { 0x0106, "Negotiation Request" },
514 { 0x0108, "BTS Initiated Request ACK" },
515 { 0x0109, "BTS Initiated Request NACK" },
516 { 0x010a, "BTS Initiated Request" },
517 { 0x010c, "Radio Channels Release Command" },
518 { 0x010e, "Radio Channels Release Complete" },
519 { 0x010f, "Radio Channels Release Reject" },
520 { 0x0118, "Feature Control Command" },
521 { 0x011a, "Feature Control Complete" },
522 { 0x011b, "Feature Control Reject" },
523
524 { 0, NULL }
525};
526
527/* TS 12.21 Section 9.4: Attributes */
528static const struct value_string om2k_attr_vals[] = {
529 { 0x00, "Accordance indication" },
530 { 0x01, "Alarm Id" },
531 { 0x02, "Alarm Data" },
532 { 0x03, "Alarm Severity" },
533 { 0x04, "Alarm Status" },
534 { 0x05, "Alarm Status Type" },
535 { 0x06, "BCC" },
536 { 0x07, "BS_AG_BKS_RES" },
537 { 0x09, "BSIC" },
538 { 0x0a, "BA_PA_MFRMS" },
539 { 0x0b, "CBCH Indicator" },
540 { 0x0c, "CCCH Options" },
541 { 0x0d, "Calendar Time" },
542 { 0x0f, "Channel Combination" },
543 { 0x10, "CON Connection List" },
544 { 0x11, "Data End Indication" },
545 { 0x12, "DRX_DEV_MAX" },
546 { 0x13, "End List Number" },
547 { 0x14, "External Condition Map Class 1" },
548 { 0x15, "External Condition Map Class 2" },
549 { 0x16, "File Relation Indication" },
550 { 0x17, "File Revision" },
551 { 0x18, "File Segment Data" },
552 { 0x19, "File Segment Length" },
553 { 0x1a, "File Segment Sequence Number" },
554 { 0x1b, "File Size" },
555 { 0x1c, "Filling Marker" },
556 { 0x1d, "FN Offset" },
557 { 0x1e, "Frequency List" },
558 { 0x1f, "Frequency Specifier RX" },
559 { 0x20, "Frequency Specifier TX" },
560 { 0x21, "HSN" },
561 { 0x22, "ICM Indicator" },
562 { 0x23, "Internal Fault Map Class 1A" },
563 { 0x24, "Internal Fault Map Class 1B" },
564 { 0x25, "Internal Fault Map Class 2A" },
565 { 0x26, "Internal Fault Map Class 2A Extension" },
566 { 0x27, "IS Connection List" },
567 { 0x28, "List Number" },
568 { 0x29, "File Package State Indication" },
569 { 0x2a, "Local Access State" },
570 { 0x2b, "MAIO" },
571 { 0x2c, "MO State" },
572 { 0x2d, "Ny1" },
573 { 0x2e, "Operational Information" },
574 { 0x2f, "Power" },
575 { 0x30, "RU Position Data" },
576 { 0x31, "Protocol Error" },
577 { 0x32, "Reason Code" },
578 { 0x33, "Receiver Diversity" },
579 { 0x34, "Replacement Unit Map" },
580 { 0x35, "Result Code" },
581 { 0x36, "RU Revision Data" },
582 { 0x38, "T3105" },
583 { 0x39, "Test Loop Setting" },
584 { 0x3a, "TF Mode" },
585 { 0x3b, "TF Compensation Value" },
586 { 0x3c, "Time Slot Number" },
587 { 0x3d, "TSC" },
588 { 0x3e, "RU Logical Id" },
589 { 0x3f, "RU Serial Number Data" },
590 { 0x40, "BTS Version" },
591 { 0x41, "OML IWD Version" },
592 { 0x42, "RWL IWD Version" },
593 { 0x43, "OML Function Map 1" },
594 { 0x44, "OML Function Map 2" },
595 { 0x45, "RSL Function Map 1" },
596 { 0x46, "RSL Function Map 2" },
597 { 0x47, "Extended Range Indicator" },
598 { 0x48, "Request Indicators" },
599 { 0x49, "DIP Alarm Condition Map" },
600 { 0x4a, "ES Incoming" },
601 { 0x4b, "ES Outgoing" },
602 { 0x4e, "SES Incoming" },
603 { 0x4f, "SES Outgoing" },
604 { 0x50, "Replacement Unit Map Extension" },
605 { 0x52, "UAS Incoming" },
606 { 0x53, "UAS Outgoing" },
607 { 0x58, "DF Incoming" },
608 { 0x5a, "DF Outgoing" },
609 { 0x5c, "SF" },
610 { 0x60, "S Bits Setting" },
611 { 0x61, "CRC-4 Use Option" },
612 { 0x62, "T Parameter" },
613 { 0x63, "N Parameter" },
614 { 0x64, "N1 Parameter" },
615 { 0x65, "N3 Parameter" },
616 { 0x66, "N4 Parameter" },
617 { 0x67, "P Parameter" },
618 { 0x68, "Q Parameter" },
619 { 0x69, "BI_Q1" },
620 { 0x6a, "BI_Q2" },
621 { 0x74, "ICM Boundary Parameters" },
622 { 0x77, "AFT" },
623 { 0x78, "AFT RAI" },
624 { 0x79, "Link Supervision Control" },
625 { 0x7a, "Link Supervision Filtering Time" },
626 { 0x7b, "Call Supervision Time" },
627 { 0x7c, "Interval Length UAS Incoming" },
628 { 0x7d, "Interval Length UAS Outgoing" },
629 { 0x7e, "ICM Channel Rate" },
630 { 0x7f, "Attribute Identifier" },
631 { 0x80, "FM Frequency List" },
632 { 0x81, "FM Frequency Report" },
633 { 0x82, "FM Percentile" },
634 { 0x83, "FM Clear Indication" },
635 { 0x84, "HW Info Signature" },
636 { 0x85, "MO Record" },
637 { 0x86, "TF Synchronisation Source" },
638 { 0x87, "TTA" },
639 { 0x88, "End Segment Number" },
640 { 0x89, "Segment Number" },
641 { 0x8a, "Capabilities Signature" },
642 { 0x8c, "File Relation List" },
643 { 0x90, "Negotiation Record I" },
644 { 0x91, "Negotiation Record II" },
645 { 0x92, "Encryption Algorithm" },
646 { 0x94, "Interference Rejection Combining" },
647 { 0x95, "Dedication Information" },
648 { 0x97, "Feature Code" },
649 { 0x98, "FS Offset" },
650 { 0x99, "ESB Timeslot" },
651 { 0x9a, "Master TG Instance" },
652 { 0x9b, "Master TX Chain Delay" },
653 { 0x9c, "External Condition Class 2 Extension" },
654 { 0x9d, "TSs MO State" },
655 { 0, NULL }
656};
657
Harald Weltee1d5eca2011-02-12 14:42:59 +0100[diff] [blame]658const struct value_string om2k_mo_class_short_vals[] = {
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]659 { 0x01, "TRXC" },
660 { 0x03, "TS" },
661 { 0x04, "TF" },
662 { 0x05, "IS" },
663 { 0x06, "CON" },
664 { 0x07, "DP" },
665 { 0x0a, "CF" },
666 { 0x0b, "TX" },
667 { 0x0c, "RX" },
668 { 0, NULL }
669};
670
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]671const struct value_string om2k_result_strings[] = {
672 { 0x02, "Wrong state or out of sequence" },
673 { 0x03, "File error" },
674 { 0x04, "Fault, unspecified" },
675 { 0x05, "Tuning fault" },
676 { 0x06, "Protocol error" },
677 { 0x07, "MO not connected" },
678 { 0x08, "Parameter error" },
679 { 0x09, "Optional function not supported" },
680 { 0x0a, "Local access state LOCALLY DISCONNECTED" },
681 { 0, NULL }
682};
683
684const struct value_string om2k_accordance_strings[] = {
685 { 0x00, "Data according to request" },
686 { 0x01, "Data not according to request" },
687 { 0x02, "Inconsistent MO data" },
688 { 0x03, "Capability constraint violation" },
689 { 0, NULL }
690};
691
692const struct value_string om2k_mostate_vals[] = {
693 { 0x00, "RESET" },
694 { 0x01, "STARTED" },
695 { 0x02, "ENABLED" },
696 { 0x03, "DISABLED" },
697 { 0, NULL }
698};
699
700/* entire decoded OM2K message (header + parsed TLV) */
701struct om2k_decoded_msg {
702 struct abis_om2k_hdr o2h;
703 uint16_t msg_type;
704 struct tlv_parsed tp;
705};
706
707/* resolve the OM2000 Managed Object by BTS + MO Address */
708static struct om2k_mo *
709get_om2k_mo(struct gsm_bts *bts, const struct abis_om2k_mo *abis_mo)
710{
711 struct om2k_mo *mo = NULL;
712 struct gsm_bts_trx *trx;
713
714 switch (abis_mo->class) {
715 case OM2K_MO_CLS_CF:
716 mo = &bts->rbs2000.cf.om2k_mo;
717 break;
718 case OM2K_MO_CLS_CON:
719 mo = &bts->rbs2000.con.om2k_mo;
720 break;
721 case OM2K_MO_CLS_IS:
722 mo = &bts->rbs2000.is.om2k_mo;
723 break;
724 case OM2K_MO_CLS_TF:
725 mo = &bts->rbs2000.tf.om2k_mo;
726 break;
727
728 case OM2K_MO_CLS_TRXC:
729 trx = gsm_bts_trx_num(bts, abis_mo->inst);
730 if (!trx)
731 return NULL;
732 mo = &trx->rbs2000.trxc.om2k_mo;
733 break;
734 case OM2K_MO_CLS_TX:
735 trx = gsm_bts_trx_num(bts, abis_mo->inst);
736 if (!trx)
737 return NULL;
738 mo = &trx->rbs2000.tx.om2k_mo;
739 break;
740 case OM2K_MO_CLS_RX:
741 trx = gsm_bts_trx_num(bts, abis_mo->inst);
742 if (!trx)
743 return NULL;
744 mo = &trx->rbs2000.rx.om2k_mo;
745 break;
746 case OM2K_MO_CLS_TS:
747 trx = gsm_bts_trx_num(bts, abis_mo->assoc_so);
748 if (!trx)
749 return NULL;
750 if (abis_mo->inst >= ARRAY_SIZE(trx->ts))
751 return NULL;
752 mo = &trx->ts[abis_mo->inst].rbs2000.om2k_mo;
753 break;
754 default:
755 return NULL;
756 };
757
758 return mo;
759}
760
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]761static struct msgb *om2k_msgb_alloc(void)
762{
763 return msgb_alloc_headroom(OM_ALLOC_SIZE, OM_HEADROOM_SIZE,
764 "OM2000");
765}
766
Holger Hans Peter Freytherc42ad8b2011-04-18 17:04:00 +0200[diff] [blame]767static int abis_om2k_tlv_parse(struct tlv_parsed *tp, const uint8_t *buf, int len)
Harald Weltee6e83832011-03-05 17:52:09 +0100[diff] [blame]768{
769 return tlv_parse(tp, &om2k_att_tlvdef, buf, len, 0, 0);
770}
771
Harald Weltee898ecc2011-03-06 19:26:11 +0100[diff] [blame]772static int abis_om2k_msg_tlv_parse(struct tlv_parsed *tp, struct abis_om2k_hdr *oh)
773{
774 return abis_om2k_tlv_parse(tp, oh->data, oh->om.length - 6);
775}
776
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]777/* decode/parse the message */
778static int om2k_decode_msg(struct om2k_decoded_msg *odm, struct msgb *msg)
779{
780 struct abis_om2k_hdr *o2h = msgb_l2(msg);
781 odm->msg_type = ntohs(o2h->msg_type);
782 odm->o2h = *o2h;
783 return abis_om2k_msg_tlv_parse(&odm->tp, o2h);
784}
785
Harald Welted88a3872011-02-14 15:26:13 +0100[diff] [blame]786static char *om2k_mo_name(const struct abis_om2k_mo *mo)
787{
788 static char mo_buf[64];
789
790 memset(mo_buf, 0, sizeof(mo_buf));
791 snprintf(mo_buf, sizeof(mo_buf), "%s/%02x/%02x/%02x",
792 get_value_string(om2k_mo_class_short_vals, mo->class),
793 mo->bts, mo->assoc_so, mo->inst);
794 return mo_buf;
795}
796
Harald Welteaf9b8102011-03-06 21:20:38 +0100[diff] [blame]797/* resolve the gsm_nm_state data structure for a given MO */
798static struct gsm_nm_state *
799mo2nm_state(struct gsm_bts *bts, const struct abis_om2k_mo *mo)
800{
801 struct gsm_bts_trx *trx;
802 struct gsm_nm_state *nm_state = NULL;
803
804 switch (mo->class) {
805 case OM2K_MO_CLS_TRXC:
Harald Welte2d027752016-11-15 22:09:08 +0100[diff] [blame]806 trx = gsm_bts_trx_num(bts, mo->inst);
Harald Welteaf9b8102011-03-06 21:20:38 +0100[diff] [blame]807 if (!trx)
808 return NULL;
Harald Welted64c0bc2011-05-30 12:07:53 +0200[diff] [blame]809 nm_state = &trx->mo.nm_state;
Harald Welteaf9b8102011-03-06 21:20:38 +0100[diff] [blame]810 break;
811 case OM2K_MO_CLS_TS:
812 trx = gsm_bts_trx_num(bts, mo->assoc_so);
813 if (!trx)
814 return NULL;
815 if (mo->inst >= ARRAY_SIZE(trx->ts))
816 return NULL;
Harald Welted64c0bc2011-05-30 12:07:53 +0200[diff] [blame]817 nm_state = &trx->ts[mo->inst].mo.nm_state;
Harald Welteaf9b8102011-03-06 21:20:38 +0100[diff] [blame]818 break;
819 case OM2K_MO_CLS_TF:
Harald Welted64c0bc2011-05-30 12:07:53 +0200[diff] [blame]820 nm_state = &bts->rbs2000.tf.mo.nm_state;
Harald Welteaf9b8102011-03-06 21:20:38 +0100[diff] [blame]821 break;
822 case OM2K_MO_CLS_IS:
Harald Welted64c0bc2011-05-30 12:07:53 +0200[diff] [blame]823 nm_state = &bts->rbs2000.is.mo.nm_state;
Harald Welteaf9b8102011-03-06 21:20:38 +0100[diff] [blame]824 break;
825 case OM2K_MO_CLS_CON:
Harald Welted64c0bc2011-05-30 12:07:53 +0200[diff] [blame]826 nm_state = &bts->rbs2000.con.mo.nm_state;
Harald Welteaf9b8102011-03-06 21:20:38 +0100[diff] [blame]827 break;
828 case OM2K_MO_CLS_DP:
Harald Welted64c0bc2011-05-30 12:07:53 +0200[diff] [blame]829 nm_state = &bts->rbs2000.con.mo.nm_state;
Harald Welteaf9b8102011-03-06 21:20:38 +0100[diff] [blame]830 break;
831 case OM2K_MO_CLS_CF:
Harald Welted64c0bc2011-05-30 12:07:53 +0200[diff] [blame]832 nm_state = &bts->mo.nm_state;
Harald Welteaf9b8102011-03-06 21:20:38 +0100[diff] [blame]833 break;
834 case OM2K_MO_CLS_TX:
Harald Welte2d027752016-11-15 22:09:08 +0100[diff] [blame]835 trx = gsm_bts_trx_num(bts, mo->inst);
Harald Welteaf9b8102011-03-06 21:20:38 +0100[diff] [blame]836 if (!trx)
837 return NULL;
Harald Welte0722ffc2016-11-15 22:58:49 +0100[diff] [blame]838 /* FIXME */
Harald Welteaf9b8102011-03-06 21:20:38 +0100[diff] [blame]839 break;
840 case OM2K_MO_CLS_RX:
Harald Welte2d027752016-11-15 22:09:08 +0100[diff] [blame]841 trx = gsm_bts_trx_num(bts, mo->inst);
Harald Welteaf9b8102011-03-06 21:20:38 +0100[diff] [blame]842 if (!trx)
843 return NULL;
Harald Welte0722ffc2016-11-15 22:58:49 +0100[diff] [blame]844 /* FIXME */
Harald Welteaf9b8102011-03-06 21:20:38 +0100[diff] [blame]845 break;
846 }
847
848 return nm_state;
849}
850
851static void *mo2obj(struct gsm_bts *bts, struct abis_om2k_mo *mo)
852{
853 struct gsm_bts_trx *trx;
854
855 switch (mo->class) {
856 case OM2K_MO_CLS_TX:
857 case OM2K_MO_CLS_RX:
858 case OM2K_MO_CLS_TRXC:
Harald Welte2d027752016-11-15 22:09:08 +0100[diff] [blame]859 return gsm_bts_trx_num(bts, mo->inst);
Harald Welteaf9b8102011-03-06 21:20:38 +0100[diff] [blame]860 case OM2K_MO_CLS_TS:
861 trx = gsm_bts_trx_num(bts, mo->assoc_so);
862 if (!trx)
863 return NULL;
864 if (mo->inst >= ARRAY_SIZE(trx->ts))
865 return NULL;
866 return &trx->ts[mo->inst];
867 case OM2K_MO_CLS_TF:
868 case OM2K_MO_CLS_IS:
869 case OM2K_MO_CLS_CON:
870 case OM2K_MO_CLS_DP:
871 case OM2K_MO_CLS_CF:
872 return bts;
873 }
874
875 return NULL;
876}
877
878static void update_mo_state(struct gsm_bts *bts, struct abis_om2k_mo *mo,
879 uint8_t mo_state)
880{
881 struct gsm_nm_state *nm_state = mo2nm_state(bts, mo);
882 struct gsm_nm_state new_state;
883 struct nm_statechg_signal_data nsd;
884
885 if (!nm_state)
886 return;
887
888 new_state = *nm_state;
889 /* NOTICE: 12.21 Availability state values != OM2000 */
890 new_state.availability = mo_state;
891
892 memset(&nsd, 0, sizeof(nsd));
893
Harald Welte8b277ac2011-03-06 23:00:32 +0100[diff] [blame]894 nsd.bts = bts;
Harald Welteaf9b8102011-03-06 21:20:38 +0100[diff] [blame]895 nsd.obj = mo2obj(bts, mo);
896 nsd.old_state = nm_state;
897 nsd.new_state = &new_state;
898 nsd.om2k_mo = mo;
899
Pablo Neira Ayusobbc5b992011-05-06 12:12:31 +0200[diff] [blame]900 osmo_signal_dispatch(SS_NM, S_NM_STATECHG_ADM, &nsd);
Harald Welteaf9b8102011-03-06 21:20:38 +0100[diff] [blame]901
902 nm_state->availability = new_state.availability;
903}
904
905static void update_op_state(struct gsm_bts *bts, const struct abis_om2k_mo *mo,
906 uint8_t op_state)
907{
908 struct gsm_nm_state *nm_state = mo2nm_state(bts, mo);
909 struct gsm_nm_state new_state;
910
911 if (!nm_state)
912 return;
913
914 new_state = *nm_state;
915 switch (op_state) {
916 case 1:
917 new_state.operational = NM_OPSTATE_ENABLED;
918 break;
919 case 0:
920 new_state.operational = NM_OPSTATE_DISABLED;
921 break;
922 default:
923 new_state.operational = NM_OPSTATE_NULL;
924 break;
925 }
926
927 nm_state->operational = new_state.operational;
928}
929
Harald Weltebc867d92011-02-12 13:09:38 +0100[diff] [blame]930static int abis_om2k_sendmsg(struct gsm_bts *bts, struct msgb *msg)
931{
Harald Welted88a3872011-02-14 15:26:13 +0100[diff] [blame]932 struct abis_om2k_hdr *o2h;
Harald Welte15eae8d2011-09-26 23:43:23 +0200[diff] [blame]933 struct gsm_bts_trx *trx;
Harald Weltebc867d92011-02-12 13:09:38 +0100[diff] [blame]934
Harald Welted88a3872011-02-14 15:26:13 +0100[diff] [blame]935 msg->l2h = msg->data;
936 o2h = (struct abis_om2k_hdr *) msg->l2h;
937
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]938 /* Compute the length in the OML header */
939 o2h->om.length = 6 + msgb_l2len(msg)-sizeof(*o2h);
940
Harald Welted88a3872011-02-14 15:26:13 +0100[diff] [blame]941 switch (o2h->mo.class) {
942 case OM2K_MO_CLS_TRXC:
943 case OM2K_MO_CLS_TX:
944 case OM2K_MO_CLS_RX:
Harald Welted88a3872011-02-14 15:26:13 +0100[diff] [blame]945 /* Route through per-TRX OML Link to the appropriate TRX */
Harald Welte15eae8d2011-09-26 23:43:23 +0200[diff] [blame]946 trx = gsm_bts_trx_by_nr(bts, o2h->mo.inst);
947 if (!trx) {
Harald Welted88a3872011-02-14 15:26:13 +0100[diff] [blame]948 LOGP(DNM, LOGL_ERROR, "MO=%s Tx Dropping msg to "
949 "non-existing TRX\n", om2k_mo_name(&o2h->mo));
950 return -ENODEV;
951 }
Harald Welte0818f312012-09-07 19:09:46 +0200[diff] [blame]952 msg->dst = trx->oml_link;
Harald Welted88a3872011-02-14 15:26:13 +0100[diff] [blame]953 break;
Harald Welte8aeac192011-03-05 20:15:09 +0100[diff] [blame]954 case OM2K_MO_CLS_TS:
955 /* Route through per-TRX OML Link to the appropriate TRX */
Harald Welte15eae8d2011-09-26 23:43:23 +0200[diff] [blame]956 trx = gsm_bts_trx_by_nr(bts, o2h->mo.assoc_so);
957 if (!trx) {
Harald Welte8aeac192011-03-05 20:15:09 +0100[diff] [blame]958 LOGP(DNM, LOGL_ERROR, "MO=%s Tx Dropping msg to "
959 "non-existing TRX\n", om2k_mo_name(&o2h->mo));
960 return -ENODEV;
961 }
Harald Welte0818f312012-09-07 19:09:46 +0200[diff] [blame]962 msg->dst = trx->oml_link;
Harald Welte8aeac192011-03-05 20:15:09 +0100[diff] [blame]963 break;
Harald Welted88a3872011-02-14 15:26:13 +0100[diff] [blame]964 default:
965 /* Route through the IXU/DXU OML Link */
Harald Welte0818f312012-09-07 19:09:46 +0200[diff] [blame]966 msg->dst = bts->oml_link;
Harald Welted88a3872011-02-14 15:26:13 +0100[diff] [blame]967 break;
968 }
969
Harald Welte15eae8d2011-09-26 23:43:23 +0200[diff] [blame]970 return _abis_nm_sendmsg(msg);
Harald Weltebc867d92011-02-12 13:09:38 +0100[diff] [blame]971}
972
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]973static void fill_om2k_hdr(struct abis_om2k_hdr *o2h, const struct abis_om2k_mo *mo,
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]974 uint16_t msg_type)
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]975{
976 o2h->om.mdisc = ABIS_OM_MDISC_FOM;
977 o2h->om.placement = ABIS_OM_PLACEMENT_ONLY;
978 o2h->om.sequence = 0;
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]979 /* We fill o2h->om.length later during om2k_sendmsg() */
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]980 o2h->msg_type = htons(msg_type);
981 memcpy(&o2h->mo, mo, sizeof(o2h->mo));
982}
983
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]984static int abis_om2k_cal_time_resp(struct gsm_bts *bts)
985{
986 struct msgb *msg = om2k_msgb_alloc();
987 struct abis_om2k_hdr *o2k;
988 time_t tm_t;
989 struct tm *tm;
990
991 o2k = (struct abis_om2k_hdr *) msgb_put(msg, sizeof(*o2k));
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]992 fill_om2k_hdr(o2k, &bts->rbs2000.cf.om2k_mo.addr,
993 OM2K_MSGT_CAL_TIME_RESP);
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]994
995 tm_t = time(NULL);
996 tm = localtime(&tm_t);
997
998 msgb_put_u8(msg, OM2K_DEI_CAL_TIME);
999 msgb_put_u8(msg, tm->tm_year % 100);
1000 msgb_put_u8(msg, tm->tm_mon + 1);
1001 msgb_put_u8(msg, tm->tm_mday);
1002 msgb_put_u8(msg, tm->tm_hour);
1003 msgb_put_u8(msg, tm->tm_min);
1004 msgb_put_u8(msg, tm->tm_sec);
1005
Harald Weltebc867d92011-02-12 13:09:38 +0100[diff] [blame]1006 return abis_om2k_sendmsg(bts, msg);
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]1007}
1008
Harald Welte6fec79d2011-02-12 14:57:17 +0100[diff] [blame]1009static int abis_om2k_tx_simple(struct gsm_bts *bts, const struct abis_om2k_mo *mo,
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]1010 uint8_t msg_type)
1011{
1012 struct msgb *msg = om2k_msgb_alloc();
1013 struct abis_om2k_hdr *o2k;
1014
1015 o2k = (struct abis_om2k_hdr *) msgb_put(msg, sizeof(*o2k));
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]1016 fill_om2k_hdr(o2k, mo, msg_type);
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]1017
Harald Welte73541072011-02-12 13:44:14 +0100[diff] [blame]1018 DEBUGP(DNM, "Tx MO=%s %s\n", om2k_mo_name(mo),
1019 get_value_string(om2k_msgcode_vals, msg_type));
1020
Harald Weltebc867d92011-02-12 13:09:38 +0100[diff] [blame]1021 return abis_om2k_sendmsg(bts, msg);
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]1022}
1023
Harald Welte6fec79d2011-02-12 14:57:17 +0100[diff] [blame]1024int abis_om2k_tx_reset_cmd(struct gsm_bts *bts, const struct abis_om2k_mo *mo)
Harald Welte73541072011-02-12 13:44:14 +0100[diff] [blame]1025{
1026 return abis_om2k_tx_simple(bts, mo, OM2K_MSGT_RESET_CMD);
1027}
1028
Harald Welte6fec79d2011-02-12 14:57:17 +0100[diff] [blame]1029int abis_om2k_tx_start_req(struct gsm_bts *bts, const struct abis_om2k_mo *mo)
Harald Welte73541072011-02-12 13:44:14 +0100[diff] [blame]1030{
1031 return abis_om2k_tx_simple(bts, mo, OM2K_MSGT_START_REQ);
1032}
1033
Harald Welte6fec79d2011-02-12 14:57:17 +0100[diff] [blame]1034int abis_om2k_tx_status_req(struct gsm_bts *bts, const struct abis_om2k_mo *mo)
Harald Weltee1d5eca2011-02-12 14:42:59 +0100[diff] [blame]1035{
1036 return abis_om2k_tx_simple(bts, mo, OM2K_MSGT_STATUS_REQ);
1037}
1038
Harald Welte6fec79d2011-02-12 14:57:17 +0100[diff] [blame]1039int abis_om2k_tx_connect_cmd(struct gsm_bts *bts, const struct abis_om2k_mo *mo)
1040{
1041 return abis_om2k_tx_simple(bts, mo, OM2K_MSGT_CONNECT_CMD);
1042}
1043
1044int abis_om2k_tx_disconnect_cmd(struct gsm_bts *bts, const struct abis_om2k_mo *mo)
1045{
1046 return abis_om2k_tx_simple(bts, mo, OM2K_MSGT_DISCONNECT_CMD);
1047}
1048
Harald Welte8024d8f2011-02-12 15:07:30 +0100[diff] [blame]1049int abis_om2k_tx_test_req(struct gsm_bts *bts, const struct abis_om2k_mo *mo)
1050{
1051 return abis_om2k_tx_simple(bts, mo, OM2K_MSGT_TEST_REQ);
1052}
1053
Harald Welte0741ffe2011-02-12 18:48:53 +0100[diff] [blame]1054int abis_om2k_tx_enable_req(struct gsm_bts *bts, const struct abis_om2k_mo *mo)
1055{
1056 return abis_om2k_tx_simple(bts, mo, OM2K_MSGT_ENABLE_REQ);
1057}
1058
1059int abis_om2k_tx_disable_req(struct gsm_bts *bts, const struct abis_om2k_mo *mo)
1060{
1061 return abis_om2k_tx_simple(bts, mo, OM2K_MSGT_DISABLE_REQ);
1062}
1063
Harald Welte6fec79d2011-02-12 14:57:17 +0100[diff] [blame]1064int abis_om2k_tx_op_info(struct gsm_bts *bts, const struct abis_om2k_mo *mo,
1065 uint8_t operational)
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]1066{
1067 struct msgb *msg = om2k_msgb_alloc();
1068 struct abis_om2k_hdr *o2k;
1069
1070 o2k = (struct abis_om2k_hdr *) msgb_put(msg, sizeof(*o2k));
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]1071 fill_om2k_hdr(o2k, mo, OM2K_MSGT_OP_INFO);
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]1072
1073 msgb_tv_put(msg, OM2K_DEI_OP_INFO, operational);
1074
Harald Welte73541072011-02-12 13:44:14 +0100[diff] [blame]1075 DEBUGP(DNM, "Tx MO=%s %s\n", om2k_mo_name(mo),
1076 get_value_string(om2k_msgcode_vals, OM2K_MSGT_OP_INFO));
1077
Harald Welteaf9b8102011-03-06 21:20:38 +0100[diff] [blame]1078 /* we update the state here... and send the signal at ACK */
1079 update_op_state(bts, mo, operational);
1080
Harald Weltebc867d92011-02-12 13:09:38 +0100[diff] [blame]1081 return abis_om2k_sendmsg(bts, msg);
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]1082}
1083
root45799782016-10-15 21:24:57 +0200[diff] [blame]1084int abis_om2k_tx_cap_req(struct gsm_bts *bts, const struct abis_om2k_mo *mo)
1085{
1086 return abis_om2k_tx_simple(bts, mo, OM2K_MSGT_CAPA_REQ);
1087}
1088
Harald Welted529db62011-03-06 21:49:21 +0100[diff] [blame]1089static void om2k_fill_is_conn_grp(struct om2k_is_conn_grp *grp, uint16_t icp1,
1090 uint16_t icp2, uint8_t cont_idx)
1091{
1092 grp->icp1 = htons(icp1);
1093 grp->icp2 = htons(icp2);
1094 grp->cont_idx = cont_idx;
1095}
1096
1097int abis_om2k_tx_is_conf_req(struct gsm_bts *bts)
Harald Welte8bcb1a02011-02-12 20:23:40 +0100[diff] [blame]1098{
1099 struct msgb *msg = om2k_msgb_alloc();
1100 struct abis_om2k_hdr *o2k;
Harald Welted529db62011-03-06 21:49:21 +0100[diff] [blame]1101 struct is_conn_group *grp;
1102 unsigned int num_grps = 0, i = 0;
1103 struct om2k_is_conn_grp *cg;
1104
1105 /* count number of groups in linked list */
1106 llist_for_each_entry(grp, &bts->rbs2000.is.conn_groups, list)
1107 num_grps++;
1108
1109 if (!num_grps)
1110 return -EINVAL;
1111
1112 /* allocate buffer for oml group array */
1113 cg = talloc_zero_array(bts, struct om2k_is_conn_grp, num_grps);
1114
1115 /* fill array with data from linked list */
1116 llist_for_each_entry(grp, &bts->rbs2000.is.conn_groups, list)
1117 om2k_fill_is_conn_grp(&cg[i++], grp->icp1, grp->icp2, grp->ci);
Harald Welte8bcb1a02011-02-12 20:23:40 +0100[diff] [blame]1118
1119 o2k = (struct abis_om2k_hdr *) msgb_put(msg, sizeof(*o2k));
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]1120 fill_om2k_hdr(o2k, &bts->rbs2000.is.om2k_mo.addr,
1121 OM2K_MSGT_IS_CONF_REQ);
Harald Welte8bcb1a02011-02-12 20:23:40 +0100[diff] [blame]1122
1123 msgb_tv_put(msg, OM2K_DEI_LIST_NR, 1);
1124 msgb_tv_put(msg, OM2K_DEI_END_LIST_NR, 1);
1125
1126 msgb_tlv_put(msg, OM2K_DEI_IS_CONN_LIST,
Harald Welted529db62011-03-06 21:49:21 +0100[diff] [blame]1127 num_grps * sizeof(*cg), (uint8_t *)cg);
1128
1129 talloc_free(cg);
Harald Welte8bcb1a02011-02-12 20:23:40 +0100[diff] [blame]1130
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]1131 DEBUGP(DNM, "Tx MO=%s %s\n",
1132 om2k_mo_name(&bts->rbs2000.is.om2k_mo.addr),
Harald Welte79c34ff2012-09-07 20:15:50 +0200[diff] [blame]1133 get_value_string(om2k_msgcode_vals, OM2K_MSGT_IS_CONF_REQ));
1134
Harald Welte8bcb1a02011-02-12 20:23:40 +0100[diff] [blame]1135 return abis_om2k_sendmsg(bts, msg);
1136}
1137
Harald Welteeae68292016-11-11 19:41:59 +0100[diff] [blame]1138int abis_om2k_tx_con_conf_req(struct gsm_bts *bts)
Harald Weltefdb71942011-02-14 15:31:43 +0100[diff] [blame]1139{
1140 struct msgb *msg = om2k_msgb_alloc();
1141 struct abis_om2k_hdr *o2k;
Harald Welteeae68292016-11-11 19:41:59 +0100[diff] [blame]1142 struct con_group *grp;
1143 unsigned int num_grps = 0;
Harald Weltefdb71942011-02-14 15:31:43 +0100[diff] [blame]1144
Harald Welteeae68292016-11-11 19:41:59 +0100[diff] [blame]1145 /* count number of groups in linked list */
1146 llist_for_each_entry(grp, &bts->rbs2000.con.conn_groups, list)
1147 num_grps++;
1148
1149 if (!num_grps)
1150 return -EINVAL;
1151
1152 /* first build the value part of the OM2K_DEI_CON_CONN_LIST DEI */
1153 msgb_put_u8(msg, num_grps);
1154 llist_for_each_entry(grp, &bts->rbs2000.con.conn_groups, list) {
1155 struct con_path *cp;
1156 unsigned int num_paths = 0;
1157 llist_for_each_entry(cp, &grp->paths, list)
1158 num_paths++;
1159 msgb_put_u8(msg, num_paths);
1160 llist_for_each_entry(cp, &grp->paths, list) {
1161 struct om2k_con_path *om2k_cp;
1162 om2k_cp = (struct om2k_con_path *) msgb_put(msg, sizeof(*om2k_cp));
1163 om2k_cp->ccp = htons(cp->ccp);
1164 om2k_cp->ci = cp->ci;
1165 om2k_cp->tag = cp->tag;
1166 om2k_cp->tei = cp->tei;
1167 }
1168 }
1169 msgb_push_u8(msg, msgb_length(msg));
1170 msgb_push_u8(msg, OM2K_DEI_CON_CONN_LIST);
1171
1172 /* pre-pend the list number DEIs */
1173 msgb_tv_push(msg, OM2K_DEI_END_LIST_NR, 1);
1174 msgb_tv_push(msg, OM2K_DEI_LIST_NR, 1);
1175
1176 /* pre-pend the OM2K header */
1177 o2k = (struct abis_om2k_hdr *) msgb_push(msg, sizeof(*o2k));
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]1178 fill_om2k_hdr(o2k, &bts->rbs2000.con.om2k_mo.addr,
1179 OM2K_MSGT_CON_CONF_REQ);
Harald Weltefdb71942011-02-14 15:31:43 +0100[diff] [blame]1180
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]1181 DEBUGP(DNM, "Tx MO=%s %s\n",
1182 om2k_mo_name(&bts->rbs2000.con.om2k_mo.addr),
Harald Welte79c34ff2012-09-07 20:15:50 +0200[diff] [blame]1183 get_value_string(om2k_msgcode_vals, OM2K_MSGT_CON_CONF_REQ));
1184
Harald Weltefdb71942011-02-14 15:31:43 +0100[diff] [blame]1185 return abis_om2k_sendmsg(bts, msg);
1186}
1187
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]1188static void om2k_trx_to_mo(struct abis_om2k_mo *mo,
1189 const struct gsm_bts_trx *trx,
1190 enum abis_om2k_mo_cls cls)
1191{
1192 mo->class = cls;
1193 mo->bts = 0;
1194 mo->inst = trx->nr;
Harald Welte53492c82011-03-05 16:21:01 +0100[diff] [blame]1195 mo->assoc_so = 255;
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]1196}
1197
1198static void om2k_ts_to_mo(struct abis_om2k_mo *mo,
1199 const struct gsm_bts_trx_ts *ts)
1200{
1201 mo->class = OM2K_MO_CLS_TS;
1202 mo->bts = 0;
1203 mo->inst = ts->nr;
1204 mo->assoc_so = ts->trx->nr;
1205}
1206
1207/* Configure a Receiver MO */
1208int abis_om2k_tx_rx_conf_req(struct gsm_bts_trx *trx)
1209{
1210 struct msgb *msg = om2k_msgb_alloc();
1211 struct abis_om2k_hdr *o2k;
1212 struct abis_om2k_mo mo;
1213
1214 om2k_trx_to_mo(&mo, trx, OM2K_MO_CLS_RX);
1215
1216 o2k = (struct abis_om2k_hdr *) msgb_put(msg, sizeof(*o2k));
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]1217 fill_om2k_hdr(o2k, &mo, OM2K_MSGT_RX_CONF_REQ);
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]1218
1219 msgb_tv16_put(msg, OM2K_DEI_FREQ_SPEC_RX, trx->arfcn);
Harald Welte1edc2b42011-03-06 19:01:54 +0100[diff] [blame]1220 msgb_tv_put(msg, OM2K_DEI_RX_DIVERSITY, 0x02); /* A */
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]1221
1222 return abis_om2k_sendmsg(trx->bts, msg);
1223}
1224
1225/* Configure a Transmitter MO */
1226int abis_om2k_tx_tx_conf_req(struct gsm_bts_trx *trx)
1227{
1228 struct msgb *msg = om2k_msgb_alloc();
1229 struct abis_om2k_hdr *o2k;
1230 struct abis_om2k_mo mo;
1231
1232 om2k_trx_to_mo(&mo, trx, OM2K_MO_CLS_TX);
1233
1234 o2k = (struct abis_om2k_hdr *) msgb_put(msg, sizeof(*o2k));
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]1235 fill_om2k_hdr(o2k, &mo, OM2K_MSGT_TX_CONF_REQ);
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]1236
1237 msgb_tv16_put(msg, OM2K_DEI_FREQ_SPEC_TX, trx->arfcn);
1238 msgb_tv_put(msg, OM2K_DEI_POWER, trx->nominal_power-trx->max_power_red);
1239 msgb_tv_put(msg, OM2K_DEI_FILLING_MARKER, 0); /* Filling enabled */
1240 msgb_tv_put(msg, OM2K_DEI_BCC, trx->bts->bsic & 0x7);
1241 /* Dedication Information is optional */
1242
1243 return abis_om2k_sendmsg(trx->bts, msg);
1244}
1245
Harald Weltef9cf9612011-03-05 14:36:47 +0100[diff] [blame]1246enum abis_om2k_tf_mode {
1247 OM2K_TF_MODE_MASTER = 0x00,
1248 OM2K_TF_MODE_STANDALONE = 0x01,
1249 OM2K_TF_MODE_SLAVE = 0x02,
1250 OM2K_TF_MODE_UNDEFINED = 0xff,
1251};
1252
1253static const uint8_t fs_offset_undef[5] = { 0xff, 0xff, 0xff, 0xff, 0xff };
1254
1255int abis_om2k_tx_tf_conf_req(struct gsm_bts *bts)
1256{
1257 struct msgb *msg = om2k_msgb_alloc();
1258 struct abis_om2k_hdr *o2k;
1259
1260 o2k = (struct abis_om2k_hdr *) msgb_put(msg, sizeof(*o2k));
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]1261 fill_om2k_hdr(o2k, &bts->rbs2000.tf.om2k_mo.addr,
1262 OM2K_MSGT_TF_CONF_REQ);
Harald Weltef9cf9612011-03-05 14:36:47 +0100[diff] [blame]1263
1264 msgb_tv_put(msg, OM2K_DEI_TF_MODE, OM2K_TF_MODE_STANDALONE);
Harald Welteba9adbb2011-03-06 19:01:16 +0100[diff] [blame]1265 msgb_tv_put(msg, OM2K_DEI_TF_SYNC_SRC, 0x00);
Harald Weltef9cf9612011-03-05 14:36:47 +0100[diff] [blame]1266 msgb_tv_fixed_put(msg, OM2K_DEI_FS_OFFSET,
1267 sizeof(fs_offset_undef), fs_offset_undef);
1268
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]1269 DEBUGP(DNM, "Tx MO=%s %s\n",
1270 om2k_mo_name(&bts->rbs2000.tf.om2k_mo.addr),
Harald Welte79c34ff2012-09-07 20:15:50 +0200[diff] [blame]1271 get_value_string(om2k_msgcode_vals, OM2K_MSGT_TF_CONF_REQ));
1272
Harald Weltef9cf9612011-03-05 14:36:47 +0100[diff] [blame]1273 return abis_om2k_sendmsg(bts, msg);
1274}
1275
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]1276static uint8_t pchan2comb(enum gsm_phys_chan_config pchan)
1277{
1278 switch (pchan) {
1279 case GSM_PCHAN_CCCH:
1280 return 4;
1281 case GSM_PCHAN_CCCH_SDCCH4:
1282 return 5;
1283 case GSM_PCHAN_SDCCH8_SACCH8C:
1284 return 3;
1285 case GSM_PCHAN_TCH_F:
1286 case GSM_PCHAN_TCH_H:
1287 case GSM_PCHAN_PDCH:
Harald Welte80ccb952016-11-15 23:23:42 +0100[diff] [blame]1288 case GSM_PCHAN_TCH_F_PDCH:
1289 case GSM_PCHAN_TCH_F_TCH_H_PDCH:
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]1290 return 8;
1291 default:
1292 return 0;
1293 }
1294}
1295
Neels Hofmeyr23c3aa32016-09-25 15:15:59 +0200[diff] [blame]1296static uint8_t ts2comb(struct gsm_bts_trx_ts *ts)
1297{
1298 switch (ts->pchan) {
1299 case GSM_PCHAN_TCH_F_PDCH:
Neels Hofmeyr87ef68e2016-11-10 02:18:00 +0100[diff] [blame]1300 LOGP(DNM, LOGL_ERROR, "%s pchan %s not intended for use"
1301 " with OM2000, use %s instead\n",
1302 gsm_ts_and_pchan_name(ts),
1303 gsm_pchan_name(GSM_PCHAN_TCH_F_PDCH),
1304 gsm_pchan_name(GSM_PCHAN_TCH_F_TCH_H_PDCH));
1305 /* If we allowed initialization of TCH/F_PDCH, it would fail
1306 * when we try to send the ip.access specific RSL PDCH Act
1307 * message for it. Rather fail completely right now: */
1308 return 0;
Neels Hofmeyr23c3aa32016-09-25 15:15:59 +0200[diff] [blame]1309 case GSM_PCHAN_TCH_F_TCH_H_PDCH:
Neels Hofmeyrf926f452016-10-31 18:16:34 +0100[diff] [blame]1310 return pchan2comb(GSM_PCHAN_TCH_F);
Neels Hofmeyr23c3aa32016-09-25 15:15:59 +0200[diff] [blame]1311 default:
1312 return pchan2comb(ts->pchan);
1313 }
1314}
1315
Harald Welte5748c202011-03-05 17:30:07 +0100[diff] [blame]1316static int put_freq_list(uint8_t *buf, uint16_t arfcn)
1317{
1318 buf[0] = 0x00; /* TX/RX address */
1319 buf[1] = (arfcn >> 8);
1320 buf[2] = (arfcn & 0xff);
1321
1322 return 3;
1323}
1324
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]1325/* Compute a frequency list in OM2000 fomrmat */
1326static int om2k_gen_freq_list(uint8_t *list, struct gsm_bts_trx_ts *ts)
1327{
1328 uint8_t *cur = list;
Harald Weltee6e83832011-03-05 17:52:09 +0100[diff] [blame]1329 int len;
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]1330
1331 if (ts->hopping.enabled) {
1332 unsigned int i;
1333 for (i = 0; i < ts->hopping.arfcns.data_len*8; i++) {
Harald Welte5748c202011-03-05 17:30:07 +0100[diff] [blame]1334 if (bitvec_get_bit_pos(&ts->hopping.arfcns, i))
1335 cur += put_freq_list(cur, i);
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]1336 }
Harald Welte5748c202011-03-05 17:30:07 +0100[diff] [blame]1337 } else
1338 cur += put_freq_list(cur, ts->trx->arfcn);
1339
Harald Weltee6e83832011-03-05 17:52:09 +0100[diff] [blame]1340 len = cur - list;
1341
1342 return len;
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]1343}
1344
Harald Welte75755c52011-03-05 20:38:35 +0100[diff] [blame]1345const uint8_t icm_bound_params[] = { 0x02, 0x06, 0x0c, 0x16, 0x06 };
1346
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]1347int abis_om2k_tx_ts_conf_req(struct gsm_bts_trx_ts *ts)
1348{
1349 struct msgb *msg = om2k_msgb_alloc();
1350 struct abis_om2k_hdr *o2k;
1351 struct abis_om2k_mo mo;
1352 uint8_t freq_list[64*3]; /* BA max size: 64 ARFCN */
1353 int freq_list_len;
1354
1355 om2k_ts_to_mo(&mo, ts);
1356
Harald Welte5748c202011-03-05 17:30:07 +0100[diff] [blame]1357 memset(freq_list, 0, sizeof(freq_list));
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]1358 freq_list_len = om2k_gen_freq_list(freq_list, ts);
1359 if (freq_list_len < 0)
1360 return freq_list_len;
1361
1362 o2k = (struct abis_om2k_hdr *) msgb_put(msg, sizeof(*o2k));
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]1363 fill_om2k_hdr(o2k, &mo, OM2K_MSGT_TS_CONF_REQ);
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]1364
Neels Hofmeyr23c3aa32016-09-25 15:15:59 +0200[diff] [blame]1365 msgb_tv_put(msg, OM2K_DEI_COMBINATION, ts2comb(ts));
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]1366 msgb_tv_put(msg, OM2K_DEI_TS_NR, ts->nr);
1367 msgb_tlv_put(msg, OM2K_DEI_FREQ_LIST, freq_list_len, freq_list);
1368 msgb_tv_put(msg, OM2K_DEI_HSN, ts->hopping.hsn);
1369 msgb_tv_put(msg, OM2K_DEI_MAIO, ts->hopping.maio);
1370 msgb_tv_put(msg, OM2K_DEI_BSIC, ts->trx->bts->bsic);
Harald Welte1edc2b42011-03-06 19:01:54 +0100[diff] [blame]1371 msgb_tv_put(msg, OM2K_DEI_RX_DIVERSITY, 0x02); /* A */
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]1372 msgb_tv16_put(msg, OM2K_DEI_FN_OFFSET, 0);
1373 msgb_tv_put(msg, OM2K_DEI_EXT_RANGE, 0); /* Off */
1374 /* Optional: Interference Rejection Combining */
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]1375 msgb_tv_put(msg, OM2K_DEI_INTERF_REJ_COMB, 0x00);
1376 switch (ts->pchan) {
1377 case GSM_PCHAN_CCCH:
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]1378 msgb_tv_put(msg, OM2K_DEI_BA_PA_MFRMS, 0x06);
1379 msgb_tv_put(msg, OM2K_DEI_BS_AG_BKS_RES, 0x01);
1380 msgb_tv_put(msg, OM2K_DEI_DRX_DEV_MAX, 0x05);
1381 /* Repeat Paging/IMM.ASS: True, Allow Paging Type 3: Yes, Page for 5 seconds (default) */
1382 msgb_tv_put(msg, OM2K_DEI_CCCH_OPTIONS, 0x01);
1383 break;
Harald Welte75755c52011-03-05 20:38:35 +0100[diff] [blame]1384 case GSM_PCHAN_CCCH_SDCCH4:
Harald Welte67161f22012-06-03 13:01:47 +0200[diff] [blame]1385 msgb_tv_put(msg, OM2K_DEI_T3105, ts->trx->bts->network->T3105 / 10);
Harald Welte75755c52011-03-05 20:38:35 +0100[diff] [blame]1386 msgb_tv_put(msg, OM2K_DEI_NY1, 35);
1387 msgb_tv_put(msg, OM2K_DEI_BA_PA_MFRMS, 0x06);
1388 msgb_tv_put(msg, OM2K_DEI_CBCH_INDICATOR, 0);
Harald Welte94bc1e02014-01-19 17:19:10 +0100[diff] [blame]1389 msgb_tv_put(msg, OM2K_DEI_TSC, gsm_ts_tsc(ts));
Harald Welte75755c52011-03-05 20:38:35 +0100[diff] [blame]1390 msgb_tv_put(msg, OM2K_DEI_BS_AG_BKS_RES, 0x01);
1391 msgb_tv_put(msg, OM2K_DEI_ICM_INDICATOR, 0);
1392 msgb_tv_put(msg, OM2K_DEI_DRX_DEV_MAX, 0x05);
1393 /* Repeat Paging/IMM.ASS: True, Allow Paging Type 3: Yes, Page for 5 seconds (default) */
1394 msgb_tv_put(msg, OM2K_DEI_CCCH_OPTIONS, 0x01);
1395 msgb_tv_fixed_put(msg, OM2K_DEI_ICM_BOUND_PARAMS,
1396 sizeof(icm_bound_params), icm_bound_params);
1397 break;
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]1398 case GSM_PCHAN_SDCCH8_SACCH8C:
Harald Welte67161f22012-06-03 13:01:47 +0200[diff] [blame]1399 msgb_tv_put(msg, OM2K_DEI_T3105, ts->trx->bts->network->T3105 / 10);
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]1400 msgb_tv_put(msg, OM2K_DEI_NY1, 35);
1401 msgb_tv_put(msg, OM2K_DEI_CBCH_INDICATOR, 0);
Harald Welte94bc1e02014-01-19 17:19:10 +0100[diff] [blame]1402 msgb_tv_put(msg, OM2K_DEI_TSC, gsm_ts_tsc(ts));
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]1403 /* Disable RF RESOURCE INDICATION on idle channels */
1404 msgb_tv_put(msg, OM2K_DEI_ICM_INDICATOR, 0);
Harald Welte75755c52011-03-05 20:38:35 +0100[diff] [blame]1405 msgb_tv_fixed_put(msg, OM2K_DEI_ICM_BOUND_PARAMS,
1406 sizeof(icm_bound_params), icm_bound_params);
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]1407 break;
1408 default:
Harald Welte67161f22012-06-03 13:01:47 +0200[diff] [blame]1409 msgb_tv_put(msg, OM2K_DEI_T3105, ts->trx->bts->network->T3105 / 10);
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]1410 msgb_tv_put(msg, OM2K_DEI_NY1, 35);
Harald Welte94bc1e02014-01-19 17:19:10 +0100[diff] [blame]1411 msgb_tv_put(msg, OM2K_DEI_TSC, gsm_ts_tsc(ts));
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]1412 /* Disable RF RESOURCE INDICATION on idle channels */
1413 msgb_tv_put(msg, OM2K_DEI_ICM_INDICATOR, 0);
Harald Welte75755c52011-03-05 20:38:35 +0100[diff] [blame]1414 msgb_tv_fixed_put(msg, OM2K_DEI_ICM_BOUND_PARAMS,
1415 sizeof(icm_bound_params), icm_bound_params);
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]1416 msgb_tv_put(msg, OM2K_DEI_TTA, 10); /* Timer for Time Alignment */
Harald Welte75755c52011-03-05 20:38:35 +0100[diff] [blame]1417 if (ts->pchan == GSM_PCHAN_TCH_H)
1418 msgb_tv_put(msg, OM2K_DEI_ICM_CHAN_RATE, 1); /* TCH/H */
1419 else
1420 msgb_tv_put(msg, OM2K_DEI_ICM_CHAN_RATE, 0); /* TCH/F */
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]1421 msgb_tv_put(msg, OM2K_DEI_LSC, 1); /* enabled */
Harald Welte1edc2b42011-03-06 19:01:54 +0100[diff] [blame]1422 msgb_tv_put(msg, OM2K_DEI_LSC_FILT_TIME, 10); /* units of 100ms */
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]1423 msgb_tv_put(msg, OM2K_DEI_CALL_SUPV_TIME, 8);
1424 msgb_tv_put(msg, OM2K_DEI_ENCR_ALG, 0x00);
Harald Welte96638d12016-11-15 23:23:56 +0100[diff] [blame]1425 /* Not sure what those below mean */
1426 msgb_tv_put(msg, 0x9e, 0x00);
1427 msgb_tv_put(msg, 0x9f, 0x37);
1428 msgb_tv_put(msg, 0xa0, 0x01);
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]1429 break;
1430 }
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]1431
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]1432 DEBUGP(DNM, "Tx MO=%s %s\n",
1433 om2k_mo_name(&mo),
1434 get_value_string(om2k_msgcode_vals, OM2K_MSGT_TS_CONF_REQ));
1435
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]1436 return abis_om2k_sendmsg(ts->trx->bts, msg);
1437}
Harald Weltefdb71942011-02-14 15:31:43 +0100[diff] [blame]1438
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]1439
1440/***********************************************************************
1441 * OM2000 Managed Object (MO) FSM
1442 ***********************************************************************/
1443
1444#define S(x) (1 << (x))
1445
1446enum om2k_event_name {
1447 OM2K_MO_EVT_START,
1448 OM2K_MO_EVT_RX_CONN_COMPL,
1449 OM2K_MO_EVT_RX_RESET_COMPL,
1450 OM2K_MO_EVT_RX_START_REQ_ACCEPT,
1451 OM2K_MO_EVT_RX_START_RES,
1452 OM2K_MO_EVT_RX_CFG_REQ_ACCEPT,
1453 OM2K_MO_EVT_RX_CFG_RES,
1454 OM2K_MO_EVT_RX_ENA_REQ_ACCEPT,
1455 OM2K_MO_EVT_RX_ENA_RES,
1456 OM2K_MO_EVT_RX_OPINFO_ACC,
1457};
1458
1459static const struct value_string om2k_event_names[] = {
1460 { OM2K_MO_EVT_START, "START" },
1461 { OM2K_MO_EVT_RX_CONN_COMPL, "RX-CONN-COMPL" },
1462 { OM2K_MO_EVT_RX_RESET_COMPL, "RX-RESET-COMPL" },
1463 { OM2K_MO_EVT_RX_START_REQ_ACCEPT, "RX-RESET-REQ-ACCEPT" },
1464 { OM2K_MO_EVT_RX_START_RES, "RX-START-RESULT" },
1465 { OM2K_MO_EVT_RX_CFG_REQ_ACCEPT, "RX-CFG-REQ-ACCEPT" },
1466 { OM2K_MO_EVT_RX_CFG_RES, "RX-CFG-RESULT" },
1467 { OM2K_MO_EVT_RX_ENA_REQ_ACCEPT, "RX-ENABLE-REQ-ACCEPT" },
1468 { OM2K_MO_EVT_RX_ENA_RES, "RX-ENABLE-RESULT" },
1469 { OM2K_MO_EVT_RX_OPINFO_ACC, "RX-OPINFO-ACCEPT" },
1470 { 0, NULL }
1471};
1472
1473enum om2k_mo_fsm_state {
1474 OM2K_ST_INIT,
1475 OM2K_ST_WAIT_CONN_COMPL,
1476 OM2K_ST_WAIT_RES_COMPL,
1477 OM2K_ST_WAIT_START_ACCEPT,
1478 OM2K_ST_WAIT_START_RES,
1479 OM2K_ST_WAIT_CFG_ACCEPT,
1480 OM2K_ST_WAIT_CFG_RES,
1481 OM2K_ST_WAIT_ENABLE_ACCEPT,
1482 OM2K_ST_WAIT_ENABLE_RES,
1483 OM2K_ST_WAIT_OPINFO_ACCEPT,
1484 OM2K_ST_DONE,
1485 OM2K_ST_ERROR,
1486};
1487
1488struct om2k_mo_fsm_priv {
1489 struct gsm_bts_trx *trx;
1490 struct om2k_mo *mo;
1491 uint8_t ts_nr;
1492};
1493
1494static void om2k_mo_st_init(struct osmo_fsm_inst *fi, uint32_t event, void *data)
1495{
1496 struct om2k_mo_fsm_priv *omfp = fi->priv;
1497
1498 OSMO_ASSERT(event == OM2K_MO_EVT_START);
1499
1500 switch (omfp->mo->addr.class) {
1501 case OM2K_MO_CLS_CF:
1502 /* no Connect required, is always connected */
1503 osmo_fsm_inst_state_chg(fi, OM2K_ST_WAIT_START_ACCEPT,
1504 OM2K_TIMEOUT, 0);
1505 abis_om2k_tx_start_req(omfp->trx->bts, &omfp->mo->addr);
1506 break;
1507 case OM2K_MO_CLS_TRXC:
1508 /* no Connect required, start with Reset */
1509 osmo_fsm_inst_state_chg(fi, OM2K_ST_WAIT_RES_COMPL,
1510 OM2K_TIMEOUT, 0);
1511 abis_om2k_tx_reset_cmd(omfp->trx->bts, &omfp->mo->addr);
1512 break;
1513 default:
1514 /* start with Connect */
1515 osmo_fsm_inst_state_chg(fi, OM2K_ST_WAIT_CONN_COMPL,
1516 OM2K_TIMEOUT, 0);
1517 abis_om2k_tx_connect_cmd(omfp->trx->bts, &omfp->mo->addr);
1518 break;
1519 }
1520}
1521
1522static void om2k_mo_st_wait_conn_compl(struct osmo_fsm_inst *fi, uint32_t event, void *data)
1523{
1524 struct om2k_mo_fsm_priv *omfp = fi->priv;
1525
1526 switch (omfp->mo->addr.class) {
1527#if 0
1528 case OM2K_MO_CLS_TF:
1529 /* skip the reset, hope that helps */
1530 osmo_fsm_inst_state_chg(fi, OM2K_ST_WAIT_START_ACCEPT,
1531 OM2K_TIMEOUT, 0);
1532 abis_om2k_tx_start_req(omfp->trx->bts, &omfp->mo->addr);
1533 break;
1534#endif
1535 default:
1536 osmo_fsm_inst_state_chg(fi, OM2K_ST_WAIT_RES_COMPL,
1537 OM2K_TIMEOUT, 0);
1538 abis_om2k_tx_reset_cmd(omfp->trx->bts, &omfp->mo->addr);
1539 break;
1540 }
1541}
1542
1543static void om2k_mo_st_wait_res_compl(struct osmo_fsm_inst *fi, uint32_t event, void *data)
1544{
1545 struct om2k_mo_fsm_priv *omfp = fi->priv;
1546
1547 osmo_fsm_inst_state_chg(fi, OM2K_ST_WAIT_START_ACCEPT,
1548 OM2K_TIMEOUT, 0);
1549 abis_om2k_tx_start_req(omfp->trx->bts, &omfp->mo->addr);
1550}
1551
1552static void om2k_mo_st_wait_start_accept(struct osmo_fsm_inst *fi, uint32_t event, void *data)
1553{
1554 struct om2k_decoded_msg *omd = data;
1555
1556 switch (omd->msg_type) {
1557 case OM2K_MSGT_START_REQ_ACK:
1558 osmo_fsm_inst_state_chg(fi, OM2K_ST_WAIT_START_RES,
1559 OM2K_TIMEOUT, 0);
1560 break;
1561 case OM2K_MSGT_START_REQ_REJ:
1562 osmo_fsm_inst_state_chg(fi, OM2K_ST_ERROR, 0, 0);
1563 break;
1564 }
1565}
1566
1567static void om2k_mo_st_wait_start_res(struct osmo_fsm_inst *fi, uint32_t event, void *data)
1568{
1569 struct om2k_mo_fsm_priv *omfp = fi->priv;
1570 struct gsm_bts_trx_ts *ts;
1571
1572 switch (omfp->mo->addr.class) {
1573 case OM2K_MO_CLS_CF:
1574 case OM2K_MO_CLS_TRXC:
1575 /* Transition directly to Operational Info */
1576 osmo_fsm_inst_state_chg(fi, OM2K_ST_WAIT_OPINFO_ACCEPT,
1577 OM2K_TIMEOUT, 0);
1578 abis_om2k_tx_op_info(omfp->trx->bts, &omfp->mo->addr, 1);
Harald Welte424656e2016-10-15 16:30:35 +0200[diff] [blame]1579 return;
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]1580 case OM2K_MO_CLS_DP:
1581 /* Transition directoy to WAIT_ENABLE_ACCEPT */
1582 osmo_fsm_inst_state_chg(fi, OM2K_ST_WAIT_ENABLE_ACCEPT,
1583 OM2K_TIMEOUT, 0);
1584 abis_om2k_tx_enable_req(omfp->trx->bts, &omfp->mo->addr);
1585 return;
1586#if 0
1587 case OM2K_MO_CLS_TF:
1588 /* skip the config, hope that helps speeding things up */
1589 osmo_fsm_inst_state_chg(fi, OM2K_ST_WAIT_ENABLE_ACCEPT,
1590 OM2K_TIMEOUT, 0);
1591 abis_om2k_tx_enable_req(omfp->trx->bts, &omfp->mo->addr);
1592 return;
1593#endif
1594 }
1595
1596 osmo_fsm_inst_state_chg(fi, OM2K_ST_WAIT_CFG_ACCEPT,
1597 OM2K_TIMEOUT, 0);
1598 switch (omfp->mo->addr.class) {
1599 case OM2K_MO_CLS_TF:
1600 abis_om2k_tx_tf_conf_req(omfp->trx->bts);
1601 break;
1602 case OM2K_MO_CLS_IS:
1603 abis_om2k_tx_is_conf_req(omfp->trx->bts);
1604 break;
1605 case OM2K_MO_CLS_CON:
Harald Welteeae68292016-11-11 19:41:59 +0100[diff] [blame]1606 abis_om2k_tx_con_conf_req(omfp->trx->bts);
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]1607 break;
1608 case OM2K_MO_CLS_TX:
1609 abis_om2k_tx_tx_conf_req(omfp->trx);
1610 break;
1611 case OM2K_MO_CLS_RX:
1612 abis_om2k_tx_rx_conf_req(omfp->trx);
1613 break;
1614 case OM2K_MO_CLS_TS:
1615 ts = mo2obj(omfp->trx->bts, &omfp->mo->addr);
1616 abis_om2k_tx_ts_conf_req(ts);
1617 break;
1618 }
1619}
1620
1621static void om2k_mo_st_wait_cfg_accept(struct osmo_fsm_inst *fi, uint32_t event, void *data)
1622{
1623 struct om2k_mo_fsm_priv *omfp = fi->priv;
1624 uint32_t timeout = OM2K_TIMEOUT;
1625
1626 if (omfp->mo->addr.class == OM2K_MO_CLS_TF)
1627 timeout = 600;
1628
1629 osmo_fsm_inst_state_chg(fi, OM2K_ST_WAIT_CFG_RES, timeout, 0);
1630}
1631
1632static void om2k_mo_st_wait_cfg_res(struct osmo_fsm_inst *fi, uint32_t event, void *data)
1633{
1634 struct om2k_mo_fsm_priv *omfp = fi->priv;
1635 struct om2k_decoded_msg *omd = data;
1636 uint8_t accordance;
1637
1638 if (!TLVP_PRESENT(&omd->tp, OM2K_DEI_ACCORDANCE_IND)) {
1639 osmo_fsm_inst_state_chg(fi, OM2K_ST_ERROR, 0, 0);
1640 return;
1641 }
1642 accordance = *TLVP_VAL(&omd->tp, OM2K_DEI_ACCORDANCE_IND);
1643
1644 if (accordance != 0) {
1645 /* accordance not OK */
1646 osmo_fsm_inst_state_chg(fi, OM2K_ST_ERROR, 0, 0);
1647 return;
1648 }
1649
1650 osmo_fsm_inst_state_chg(fi, OM2K_ST_WAIT_ENABLE_ACCEPT,
1651 OM2K_TIMEOUT, 0);
1652 abis_om2k_tx_enable_req(omfp->trx->bts, &omfp->mo->addr);
1653}
1654
1655static void om2k_mo_st_wait_enable_accept(struct osmo_fsm_inst *fi, uint32_t event, void *data)
1656{
Harald Weltece492582016-11-15 22:59:24 +0100[diff] [blame^]1657 struct om2k_mo_fsm_priv *omfp = fi->priv;
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]1658 struct om2k_decoded_msg *omd = data;
1659
1660 switch (omd->msg_type) {
1661 case OM2K_MSGT_ENABLE_REQ_REJ:
1662 osmo_fsm_inst_state_chg(fi, OM2K_ST_ERROR, 0, 0);
1663 break;
1664 case OM2K_MSGT_ENABLE_REQ_ACK:
Harald Weltece492582016-11-15 22:59:24 +0100[diff] [blame^]1665 if (omfp->mo->addr.class == OM2K_MO_CLS_IS &&
1666 omfp->trx->bts->rbs2000.use_superchannel)
1667 e1inp_ericsson_set_altc(omfp->trx->bts->oml_link->ts->line, 1);
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]1668 osmo_fsm_inst_state_chg(fi, OM2K_ST_WAIT_ENABLE_RES,
1669 OM2K_TIMEOUT, 0);
1670 }
1671}
1672
1673static void om2k_mo_st_wait_enable_res(struct osmo_fsm_inst *fi, uint32_t event, void *data)
1674{
1675 struct om2k_mo_fsm_priv *omfp = fi->priv;
1676 //struct om2k_decoded_msg *omd = data;
1677 /* TODO: check if state is actually enabled now? */
1678
1679 osmo_fsm_inst_state_chg(fi, OM2K_ST_WAIT_OPINFO_ACCEPT,
1680 OM2K_TIMEOUT, 0);
1681 abis_om2k_tx_op_info(omfp->trx->bts, &omfp->mo->addr, 1);
1682}
1683
1684static void om2k_mo_st_wait_opinfo_accept(struct osmo_fsm_inst *fi, uint32_t event, void *data)
1685{
Harald Welte80ccb952016-11-15 23:23:42 +0100[diff] [blame]1686 struct om2k_mo_fsm_priv *omfp = fi->priv;
1687
1688 /* if we have just received opinfo accept for the timeslot,
1689 * start dynamic TCH switching procedures */
1690 if (omfp->mo->addr.class == OM2K_MO_CLS_TS) {
Neels Hofmeyr2b9c5342016-12-02 01:58:08 +0100[diff] [blame]1691 struct gsm_bts_trx_ts *ts;
Harald Welte80ccb952016-11-15 23:23:42 +0100[diff] [blame]1692 ts = mo2obj(omfp->trx->bts, &omfp->mo->addr);
1693 dyn_ts_init(ts);
1694 }
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]1695 osmo_fsm_inst_state_chg(fi, OM2K_ST_DONE, 0, 0);
1696}
1697
1698static void om2k_mo_s_done_onenter(struct osmo_fsm_inst *fi, uint32_t prev_state)
1699{
1700 osmo_fsm_inst_term(fi, OSMO_FSM_TERM_REGULAR, NULL);
1701}
1702
1703static const struct osmo_fsm_state om2k_is_states[] = {
1704 [OM2K_ST_INIT] = {
1705 .name = "INIT",
1706 .in_event_mask = S(OM2K_MO_EVT_START),
1707 .out_state_mask = S(OM2K_ST_DONE) |
1708 S(OM2K_ST_ERROR) |
1709 S(OM2K_ST_WAIT_CONN_COMPL) |
1710 S(OM2K_ST_WAIT_START_ACCEPT) |
1711 S(OM2K_ST_WAIT_RES_COMPL),
1712 .action = om2k_mo_st_init,
1713 },
1714 [OM2K_ST_WAIT_CONN_COMPL] = {
1715 .name = "WAIT-CONN-COMPL",
1716 .in_event_mask = S(OM2K_MO_EVT_RX_CONN_COMPL),
1717 .out_state_mask = S(OM2K_ST_DONE) |
1718 S(OM2K_ST_ERROR) |
1719 S(OM2K_ST_WAIT_START_ACCEPT) |
1720 S(OM2K_ST_WAIT_RES_COMPL),
1721 .action = om2k_mo_st_wait_conn_compl,
1722 },
1723 [OM2K_ST_WAIT_RES_COMPL] = {
1724 .name = "WAIT-RES-COMPL",
1725 .in_event_mask = S(OM2K_MO_EVT_RX_RESET_COMPL),
1726 .out_state_mask = S(OM2K_ST_DONE) |
1727 S(OM2K_ST_ERROR) |
1728 S(OM2K_ST_WAIT_START_ACCEPT),
1729 .action = om2k_mo_st_wait_res_compl,
1730 },
1731 [OM2K_ST_WAIT_START_ACCEPT] = {
1732 .name = "WAIT-START-ACCEPT",
1733 .in_event_mask = S(OM2K_MO_EVT_RX_START_REQ_ACCEPT),
1734 .out_state_mask = S(OM2K_ST_DONE) |
1735 S(OM2K_ST_ERROR) |
1736 S(OM2K_ST_WAIT_START_RES),
1737 .action =om2k_mo_st_wait_start_accept,
1738 },
1739 [OM2K_ST_WAIT_START_RES] = {
1740 .name = "WAIT-START-RES",
1741 .in_event_mask = S(OM2K_MO_EVT_RX_START_RES),
1742 .out_state_mask = S(OM2K_ST_DONE) |
1743 S(OM2K_ST_ERROR) |
1744 S(OM2K_ST_WAIT_CFG_ACCEPT) |
1745 S(OM2K_ST_WAIT_OPINFO_ACCEPT),
1746 .action = om2k_mo_st_wait_start_res,
1747 },
1748 [OM2K_ST_WAIT_CFG_ACCEPT] = {
1749 .name = "WAIT-CFG-ACCEPT",
1750 .in_event_mask = S(OM2K_MO_EVT_RX_CFG_REQ_ACCEPT),
1751 .out_state_mask = S(OM2K_ST_DONE) |
1752 S(OM2K_ST_ERROR) |
1753 S(OM2K_ST_WAIT_CFG_RES),
1754 .action = om2k_mo_st_wait_cfg_accept,
1755 },
1756 [OM2K_ST_WAIT_CFG_RES] = {
1757 .name = "WAIT-CFG-RES",
1758 .in_event_mask = S(OM2K_MO_EVT_RX_CFG_RES),
1759 .out_state_mask = S(OM2K_ST_DONE) |
1760 S(OM2K_ST_ERROR) |
1761 S(OM2K_ST_WAIT_ENABLE_ACCEPT),
1762 .action = om2k_mo_st_wait_cfg_res,
1763 },
1764 [OM2K_ST_WAIT_ENABLE_ACCEPT] = {
1765 .name = "WAIT-ENABLE-ACCEPT",
1766 .in_event_mask = S(OM2K_MO_EVT_RX_ENA_REQ_ACCEPT),
1767 .out_state_mask = S(OM2K_ST_DONE) |
1768 S(OM2K_ST_ERROR) |
1769 S(OM2K_ST_WAIT_ENABLE_RES),
1770 .action = om2k_mo_st_wait_enable_accept,
1771 },
1772 [OM2K_ST_WAIT_ENABLE_RES] = {
1773 .name = "WAIT-ENABLE-RES",
1774 .in_event_mask = S(OM2K_MO_EVT_RX_ENA_RES),
1775 .out_state_mask = S(OM2K_ST_DONE) |
1776 S(OM2K_ST_ERROR) |
1777 S(OM2K_ST_WAIT_OPINFO_ACCEPT),
1778 .action = om2k_mo_st_wait_enable_res,
1779 },
1780 [OM2K_ST_WAIT_OPINFO_ACCEPT] = {
1781 .name = "WAIT-OPINFO-ACCEPT",
1782 .in_event_mask = S(OM2K_MO_EVT_RX_OPINFO_ACC),
1783 .out_state_mask = S(OM2K_ST_DONE) |
1784 S(OM2K_ST_ERROR),
1785 .action = om2k_mo_st_wait_opinfo_accept,
1786 },
1787 [OM2K_ST_DONE] = {
1788 .name = "DONE",
1789 .in_event_mask = 0,
1790 .out_state_mask = 0,
1791 .onenter = om2k_mo_s_done_onenter,
1792 },
1793 [OM2K_ST_ERROR] = {
1794 .name = "ERROR",
1795 .in_event_mask = 0,
1796 .out_state_mask = 0,
1797 .onenter = om2k_mo_s_done_onenter,
1798 },
1799
1800};
1801
1802static int om2k_mo_timer_cb(struct osmo_fsm_inst *fi)
1803{
1804 osmo_fsm_inst_state_chg(fi, OM2K_ST_ERROR, 0, 0);
1805 return 0;
1806}
1807
1808static struct osmo_fsm om2k_mo_fsm = {
1809 .name = "OM2000-MO",
1810 .states = om2k_is_states,
1811 .num_states = ARRAY_SIZE(om2k_is_states),
1812 .log_subsys = DNM,
1813 .event_names = om2k_event_names,
1814 .timer_cb = om2k_mo_timer_cb,
1815};
1816
1817struct osmo_fsm_inst *om2k_mo_fsm_start(struct osmo_fsm_inst *parent,
1818 uint32_t term_event,
1819 struct gsm_bts_trx *trx, struct om2k_mo *mo)
1820{
1821 struct osmo_fsm_inst *fi;
1822 struct om2k_mo_fsm_priv *omfp;
1823 char idbuf[64];
1824
1825 snprintf(idbuf, sizeof(idbuf), "%s-%s", parent->id,
1826 om2k_mo_name(&mo->addr));
1827
1828 fi = osmo_fsm_inst_alloc_child_id(&om2k_mo_fsm, parent,
1829 term_event, idbuf);
1830 if (!fi)
1831 return NULL;
1832
1833 mo->fsm = fi;
1834 omfp = talloc_zero(fi, struct om2k_mo_fsm_priv);
1835 omfp->mo = mo;
1836 omfp->trx = trx;
1837 fi->priv = omfp;
1838
1839 osmo_fsm_inst_dispatch(fi, OM2K_MO_EVT_START, NULL);
1840
1841 return fi;
1842}
1843
1844int om2k_mo_fsm_recvmsg(struct gsm_bts *bts, struct om2k_mo *mo,
1845 struct om2k_decoded_msg *odm)
1846{
1847 switch (odm->msg_type) {
1848 case OM2K_MSGT_CONNECT_COMPL:
1849 case OM2K_MSGT_CONNECT_REJ:
1850 osmo_fsm_inst_dispatch(mo->fsm,
1851 OM2K_MO_EVT_RX_CONN_COMPL, odm);
1852 break;
1853
1854 case OM2K_MSGT_RESET_COMPL:
1855 case OM2K_MSGT_RESET_REJ:
1856 osmo_fsm_inst_dispatch(mo->fsm,
1857 OM2K_MO_EVT_RX_RESET_COMPL, odm);
1858 break;
1859
1860 case OM2K_MSGT_START_REQ_ACK:
1861 case OM2K_MSGT_START_REQ_REJ:
1862 osmo_fsm_inst_dispatch(mo->fsm,
1863 OM2K_MO_EVT_RX_START_REQ_ACCEPT, odm);
1864 break;
1865
1866 case OM2K_MSGT_START_RES:
1867 osmo_fsm_inst_dispatch(mo->fsm,
1868 OM2K_MO_EVT_RX_START_RES, odm);
1869 break;
1870
1871 case OM2K_MSGT_CON_CONF_REQ_ACK:
1872 case OM2K_MSGT_IS_CONF_REQ_ACK:
1873 case OM2K_MSGT_RX_CONF_REQ_ACK:
1874 case OM2K_MSGT_TF_CONF_REQ_ACK:
1875 case OM2K_MSGT_TS_CONF_REQ_ACK:
1876 case OM2K_MSGT_TX_CONF_REQ_ACK:
1877 osmo_fsm_inst_dispatch(mo->fsm,
1878 OM2K_MO_EVT_RX_CFG_REQ_ACCEPT, odm);
1879 break;
1880
1881 case OM2K_MSGT_CON_CONF_RES:
1882 case OM2K_MSGT_IS_CONF_RES:
1883 case OM2K_MSGT_RX_CONF_RES:
1884 case OM2K_MSGT_TF_CONF_RES:
1885 case OM2K_MSGT_TS_CONF_RES:
1886 case OM2K_MSGT_TX_CONF_RES:
1887 osmo_fsm_inst_dispatch(mo->fsm,
1888 OM2K_MO_EVT_RX_CFG_RES, odm);
1889 break;
1890
1891 case OM2K_MSGT_ENABLE_REQ_ACK:
1892 case OM2K_MSGT_ENABLE_REQ_REJ:
1893 osmo_fsm_inst_dispatch(mo->fsm,
1894 OM2K_MO_EVT_RX_ENA_REQ_ACCEPT, odm);
1895 break;
1896 case OM2K_MSGT_ENABLE_RES:
1897 osmo_fsm_inst_dispatch(mo->fsm,
1898 OM2K_MO_EVT_RX_ENA_RES, odm);
1899 break;
1900
1901 case OM2K_MSGT_OP_INFO_ACK:
1902 case OM2K_MSGT_OP_INFO_REJ:
1903 osmo_fsm_inst_dispatch(mo->fsm,
1904 OM2K_MO_EVT_RX_OPINFO_ACC, odm);
1905 break;
1906 default:
1907 return -1;
1908 }
1909
1910 return 0;
1911}
1912
1913/***********************************************************************
1914 * OM2000 TRX Finite State Machine, initializes TRXC and all siblings
1915 ***********************************************************************/
1916
1917enum om2k_trx_event {
1918 OM2K_TRX_EVT_START,
1919 OM2K_TRX_EVT_TRXC_DONE,
1920 OM2K_TRX_EVT_TX_DONE,
1921 OM2K_TRX_EVT_RX_DONE,
1922 OM2K_TRX_EVT_TS_DONE,
1923 OM2K_TRX_EVT_STOP,
1924};
1925
1926static struct value_string om2k_trx_events[] = {
1927 { OM2K_TRX_EVT_START, "START" },
1928 { OM2K_TRX_EVT_TRXC_DONE, "TRXC-DONE" },
1929 { OM2K_TRX_EVT_TX_DONE, "TX-DONE" },
1930 { OM2K_TRX_EVT_RX_DONE, "RX-DONE" },
1931 { OM2K_TRX_EVT_TS_DONE, "TS-DONE" },
1932 { OM2K_TRX_EVT_STOP, "STOP" },
1933 { 0, NULL }
1934};
1935
1936enum om2k_trx_state {
1937 OM2K_TRX_S_INIT,
1938 OM2K_TRX_S_WAIT_TRXC,
1939 OM2K_TRX_S_WAIT_TX,
1940 OM2K_TRX_S_WAIT_RX,
1941 OM2K_TRX_S_WAIT_TS,
1942 OM2K_TRX_S_DONE,
1943 OM2K_TRX_S_ERROR
1944};
1945
1946struct om2k_trx_fsm_priv {
1947 struct gsm_bts_trx *trx;
1948 uint8_t next_ts_nr;
1949};
1950
1951static void om2k_trx_s_init(struct osmo_fsm_inst *fi, uint32_t event, void *data)
1952{
1953 struct om2k_trx_fsm_priv *otfp = fi->priv;
1954
1955 /* First initialize TRXC */
1956 osmo_fsm_inst_state_chg(fi, OM2K_TRX_S_WAIT_TRXC,
1957 TRX_FSM_TIMEOUT, 0);
1958 om2k_mo_fsm_start(fi, OM2K_TRX_EVT_TRXC_DONE, otfp->trx,
1959 &otfp->trx->rbs2000.trxc.om2k_mo);
1960}
1961
1962static void om2k_trx_s_wait_trxc(struct osmo_fsm_inst *fi, uint32_t event, void *data)
1963{
1964 struct om2k_trx_fsm_priv *otfp = fi->priv;
1965
1966 /* Initialize TX after TRXC */
1967 osmo_fsm_inst_state_chg(fi, OM2K_TRX_S_WAIT_TX,
1968 TRX_FSM_TIMEOUT, 0);
1969 om2k_mo_fsm_start(fi, OM2K_TRX_EVT_TX_DONE, otfp->trx,
1970 &otfp->trx->rbs2000.tx.om2k_mo);
1971}
1972
1973static void om2k_trx_s_wait_tx(struct osmo_fsm_inst *fi, uint32_t event, void *data)
1974{
1975 struct om2k_trx_fsm_priv *otfp = fi->priv;
1976
1977 /* Initialize RX after TX */
1978 osmo_fsm_inst_state_chg(fi, OM2K_TRX_S_WAIT_RX,
1979 TRX_FSM_TIMEOUT, 0);
1980 om2k_mo_fsm_start(fi, OM2K_TRX_EVT_RX_DONE, otfp->trx,
1981 &otfp->trx->rbs2000.rx.om2k_mo);
1982}
1983
1984static void om2k_trx_s_wait_rx(struct osmo_fsm_inst *fi, uint32_t event, void *data)
1985{
1986 struct om2k_trx_fsm_priv *otfp = fi->priv;
1987 struct gsm_bts_trx_ts *ts;
1988
1989 /* Initialize Timeslots after TX */
1990 osmo_fsm_inst_state_chg(fi, OM2K_TRX_S_WAIT_TS,
1991 TRX_FSM_TIMEOUT, 0);
1992 otfp->next_ts_nr = 0;
1993 ts = &otfp->trx->ts[otfp->next_ts_nr++];
1994 om2k_mo_fsm_start(fi, OM2K_TRX_EVT_TS_DONE, otfp->trx,
1995 &ts->rbs2000.om2k_mo);
1996}
1997
1998static void om2k_trx_s_wait_ts(struct osmo_fsm_inst *fi, uint32_t event, void *data)
1999{
2000 struct om2k_trx_fsm_priv *otfp = fi->priv;
2001 struct gsm_bts_trx_ts *ts;
2002
2003 if (otfp->next_ts_nr < 8) {
2004 /* iterate to the next timeslot */
2005 ts = &otfp->trx->ts[otfp->next_ts_nr++];
2006 om2k_mo_fsm_start(fi, OM2K_TRX_EVT_TS_DONE, otfp->trx,
2007 &ts->rbs2000.om2k_mo);
2008 } else {
2009 /* only after all 8 TS */
2010 osmo_fsm_inst_state_chg(fi, OM2K_TRX_S_DONE, 0, 0);
2011 }
2012}
2013
2014static void om2k_trx_s_done_onenter(struct osmo_fsm_inst *fi, uint32_t prev_state)
2015{
2016 struct om2k_trx_fsm_priv *otfp = fi->priv;
2017 gsm_bts_trx_set_system_infos(otfp->trx);
2018 osmo_fsm_inst_term(fi, OSMO_FSM_TERM_REGULAR, NULL);
2019}
2020
2021static const struct osmo_fsm_state om2k_trx_states[] = {
2022 [OM2K_TRX_S_INIT] = {
2023 .in_event_mask = S(OM2K_TRX_EVT_START),
2024 .out_state_mask = S(OM2K_TRX_S_WAIT_TRXC),
2025 .name = "INIT",
2026 .action = om2k_trx_s_init,
2027 },
2028 [OM2K_TRX_S_WAIT_TRXC] = {
2029 .in_event_mask = S(OM2K_TRX_EVT_TRXC_DONE),
2030 .out_state_mask = S(OM2K_TRX_S_ERROR) |
2031 S(OM2K_TRX_S_WAIT_TX),
2032 .name = "WAIT-TRXC",
2033 .action = om2k_trx_s_wait_trxc,
2034 },
2035 [OM2K_TRX_S_WAIT_TX] = {
2036 .in_event_mask = S(OM2K_TRX_EVT_TX_DONE),
2037 .out_state_mask = S(OM2K_TRX_S_ERROR) |
2038 S(OM2K_TRX_S_WAIT_RX),
2039 .name = "WAIT-TX",
2040 .action = om2k_trx_s_wait_tx,
2041 },
2042 [OM2K_TRX_S_WAIT_RX] = {
2043 .in_event_mask = S(OM2K_TRX_EVT_RX_DONE),
2044 .out_state_mask = S(OM2K_TRX_S_ERROR) |
2045 S(OM2K_TRX_S_WAIT_TS),
2046 .name = "WAIT-RX",
2047 .action = om2k_trx_s_wait_rx,
2048 },
2049 [OM2K_TRX_S_WAIT_TS] = {
2050 .in_event_mask = S(OM2K_TRX_EVT_TS_DONE),
2051 .out_state_mask = S(OM2K_TRX_S_ERROR) |
2052 S(OM2K_TRX_S_DONE),
2053 .name = "WAIT-TS",
2054 .action = om2k_trx_s_wait_ts,
2055 },
2056 [OM2K_TRX_S_DONE] = {
2057 .name = "DONE",
2058 .onenter = om2k_trx_s_done_onenter,
2059 },
2060 [OM2K_TRX_S_ERROR] = {
2061 .name = "ERROR",
2062 },
2063};
2064
2065static int om2k_trx_timer_cb(struct osmo_fsm_inst *fi)
2066{
2067 osmo_fsm_inst_state_chg(fi, OM2K_TRX_S_ERROR, 0, 0);
2068 return 0;
2069}
2070
2071static struct osmo_fsm om2k_trx_fsm = {
2072 .name = "OM2000-TRX",
2073 .states = om2k_trx_states,
2074 .num_states = ARRAY_SIZE(om2k_trx_states),
2075 .log_subsys = DNM,
2076 .event_names = om2k_trx_events,
2077 .timer_cb = om2k_trx_timer_cb,
2078};
2079
2080struct osmo_fsm_inst *om2k_trx_fsm_start(struct osmo_fsm_inst *parent,
2081 struct gsm_bts_trx *trx,
2082 uint32_t term_event)
2083{
2084 struct osmo_fsm_inst *fi;
2085 struct om2k_trx_fsm_priv *otfp;
2086 char idbuf[32];
2087
2088 snprintf(idbuf, sizeof(idbuf), "%u/%u", trx->bts->nr, trx->nr);
2089
2090 fi = osmo_fsm_inst_alloc_child_id(&om2k_trx_fsm, parent, term_event,
2091 idbuf);
2092 if (!fi)
2093 return NULL;
2094
2095 otfp = talloc_zero(fi, struct om2k_trx_fsm_priv);
2096 otfp->trx = trx;
2097 fi->priv = otfp;
2098
2099 osmo_fsm_inst_dispatch(fi, OM2K_TRX_EVT_START, NULL);
2100
2101 return fi;
2102}
2103
2104
2105/***********************************************************************
2106 * OM2000 BTS Finite State Machine, initializes CF and all siblings
2107 ***********************************************************************/
2108
2109enum om2k_bts_event {
2110 OM2K_BTS_EVT_START,
2111 OM2K_BTS_EVT_CF_DONE,
2112 OM2K_BTS_EVT_IS_DONE,
Harald Welteeae68292016-11-11 19:41:59 +0100[diff] [blame]2113 OM2K_BTS_EVT_CON_DONE,
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]2114 OM2K_BTS_EVT_TF_DONE,
2115 OM2K_BTS_EVT_TRX_DONE,
2116 OM2K_BTS_EVT_STOP,
2117};
2118
2119static const struct value_string om2k_bts_events[] = {
2120 { OM2K_BTS_EVT_START, "START" },
2121 { OM2K_BTS_EVT_CF_DONE, "CF-DONE" },
2122 { OM2K_BTS_EVT_IS_DONE, "IS-DONE" },
Harald Welteeae68292016-11-11 19:41:59 +0100[diff] [blame]2123 { OM2K_BTS_EVT_CON_DONE, "CON-DONE" },
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]2124 { OM2K_BTS_EVT_TF_DONE, "TF-DONE" },
2125 { OM2K_BTS_EVT_TRX_DONE, "TRX-DONE" },
2126 { OM2K_BTS_EVT_STOP, "STOP" },
2127 { 0, NULL }
2128};
2129
2130enum om2k_bts_state {
2131 OM2K_BTS_S_INIT,
2132 OM2K_BTS_S_WAIT_CF,
2133 OM2K_BTS_S_WAIT_IS,
Harald Welteeae68292016-11-11 19:41:59 +0100[diff] [blame]2134 OM2K_BTS_S_WAIT_CON,
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]2135 OM2K_BTS_S_WAIT_TF,
2136 OM2K_BTS_S_WAIT_TRX,
2137 OM2K_BTS_S_DONE,
2138 OM2K_BTS_S_ERROR,
2139};
2140
2141struct om2k_bts_fsm_priv {
2142 struct gsm_bts *bts;
2143 uint8_t next_trx_nr;
2144};
2145
2146static void om2k_bts_s_init(struct osmo_fsm_inst *fi, uint32_t event, void *data)
2147{
2148 struct om2k_bts_fsm_priv *obfp = fi->priv;
2149 struct gsm_bts *bts = obfp->bts;
2150
2151 OSMO_ASSERT(event == OM2K_BTS_EVT_START);
2152 osmo_fsm_inst_state_chg(fi, OM2K_BTS_S_WAIT_CF,
2153 BTS_FSM_TIMEOUT, 0);
2154 om2k_mo_fsm_start(fi, OM2K_BTS_EVT_CF_DONE, bts->c0,
2155 &bts->rbs2000.cf.om2k_mo);
2156}
2157
2158static void om2k_bts_s_wait_cf(struct osmo_fsm_inst *fi, uint32_t event, void *data)
2159{
2160 struct om2k_bts_fsm_priv *obfp = fi->priv;
2161 struct gsm_bts *bts = obfp->bts;
2162
2163 OSMO_ASSERT(event == OM2K_BTS_EVT_CF_DONE);
Harald Weltec103c642017-03-13 09:39:08 +0100[diff] [blame]2164 /* TF can take a long time to initialize, wait for 10min */
2165 osmo_fsm_inst_state_chg(fi, OM2K_BTS_S_WAIT_TF, 600, 0);
2166 om2k_mo_fsm_start(fi, OM2K_BTS_EVT_TF_DONE, bts->c0,
2167 &bts->rbs2000.tf.om2k_mo);
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]2168}
2169
Harald Weltec103c642017-03-13 09:39:08 +0100[diff] [blame]2170static void om2k_bts_s_wait_tf(struct osmo_fsm_inst *fi, uint32_t event, void *data)
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]2171{
2172 struct om2k_bts_fsm_priv *obfp = fi->priv;
2173 struct gsm_bts *bts = obfp->bts;
2174
Harald Weltec103c642017-03-13 09:39:08 +0100[diff] [blame]2175 OSMO_ASSERT(event == OM2K_BTS_EVT_TF_DONE);
2176
Harald Welteeae68292016-11-11 19:41:59 +0100[diff] [blame]2177 osmo_fsm_inst_state_chg(fi, OM2K_BTS_S_WAIT_CON,
2178 BTS_FSM_TIMEOUT, 0);
2179 om2k_mo_fsm_start(fi, OM2K_BTS_EVT_CON_DONE, bts->c0,
2180 &bts->rbs2000.con.om2k_mo);
2181}
2182
2183static void om2k_bts_s_wait_con(struct osmo_fsm_inst *fi, uint32_t event, void *data)
2184{
2185 struct om2k_bts_fsm_priv *obfp = fi->priv;
2186 struct gsm_bts *bts = obfp->bts;
2187
2188 OSMO_ASSERT(event == OM2K_BTS_EVT_CON_DONE);
Harald Weltec103c642017-03-13 09:39:08 +0100[diff] [blame]2189
2190 osmo_fsm_inst_state_chg(fi, OM2K_BTS_S_WAIT_IS,
2191 BTS_FSM_TIMEOUT, 0);
2192 om2k_mo_fsm_start(fi, OM2K_BTS_EVT_IS_DONE, bts->c0,
2193 &bts->rbs2000.is.om2k_mo);
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]2194}
2195
Harald Weltec103c642017-03-13 09:39:08 +0100[diff] [blame]2196static void om2k_bts_s_wait_is(struct osmo_fsm_inst *fi, uint32_t event, void *data)
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]2197{
2198 struct om2k_bts_fsm_priv *obfp = fi->priv;
2199 struct gsm_bts_trx *trx;
2200
Harald Weltec103c642017-03-13 09:39:08 +0100[diff] [blame]2201 OSMO_ASSERT(event == OM2K_BTS_EVT_IS_DONE);
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]2202
2203 osmo_fsm_inst_state_chg(fi, OM2K_BTS_S_WAIT_TRX,
2204 BTS_FSM_TIMEOUT, 0);
2205 obfp->next_trx_nr = 0;
2206 trx = gsm_bts_trx_num(obfp->bts, obfp->next_trx_nr++);
2207 om2k_trx_fsm_start(fi, trx, OM2K_BTS_EVT_TRX_DONE);
2208}
2209
2210static void om2k_bts_s_wait_trx(struct osmo_fsm_inst *fi, uint32_t event, void *data)
2211{
2212 struct om2k_bts_fsm_priv *obfp = fi->priv;
2213
2214 OSMO_ASSERT(event == OM2K_BTS_EVT_TRX_DONE);
2215
2216 if (obfp->next_trx_nr < obfp->bts->num_trx) {
2217 struct gsm_bts_trx *trx;
2218 trx = gsm_bts_trx_num(obfp->bts, obfp->next_trx_nr++);
2219 om2k_trx_fsm_start(fi, trx, OM2K_BTS_EVT_TRX_DONE);
2220 } else {
2221 osmo_fsm_inst_state_chg(fi, OM2K_BTS_S_DONE, 0, 0);
2222 }
2223}
2224
2225static void om2k_bts_s_done_onenter(struct osmo_fsm_inst *fi, uint32_t prev_state)
2226{
2227 osmo_fsm_inst_term(fi, OSMO_FSM_TERM_REGULAR, NULL);
2228}
2229
2230static const struct osmo_fsm_state om2k_bts_states[] = {
2231 [OM2K_BTS_S_INIT] = {
2232 .in_event_mask = S(OM2K_BTS_EVT_START),
2233 .out_state_mask = S(OM2K_BTS_S_WAIT_CF),
2234 .name = "INIT",
2235 .action = om2k_bts_s_init,
2236 },
2237 [OM2K_BTS_S_WAIT_CF] = {
2238 .in_event_mask = S(OM2K_BTS_EVT_CF_DONE),
2239 .out_state_mask = S(OM2K_BTS_S_ERROR) |
Harald Weltec103c642017-03-13 09:39:08 +0100[diff] [blame]2240 S(OM2K_BTS_S_WAIT_TF),
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]2241 .name = "WAIT-CF",
2242 .action = om2k_bts_s_wait_cf,
2243 },
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]2244 [OM2K_BTS_S_WAIT_TF] = {
2245 .in_event_mask = S(OM2K_BTS_EVT_TF_DONE),
2246 .out_state_mask = S(OM2K_BTS_S_ERROR) |
Harald Weltec103c642017-03-13 09:39:08 +0100[diff] [blame]2247 S(OM2K_BTS_S_WAIT_CON),
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]2248 .name = "WAIT-TF",
2249 .action = om2k_bts_s_wait_tf,
2250 },
Harald Weltec103c642017-03-13 09:39:08 +0100[diff] [blame]2251 [OM2K_BTS_S_WAIT_CON] = {
2252 .in_event_mask = S(OM2K_BTS_EVT_CON_DONE),
2253 .out_state_mask = S(OM2K_BTS_S_ERROR) |
2254 S(OM2K_BTS_S_WAIT_IS),
2255 .name = "WAIT-CON",
2256 .action = om2k_bts_s_wait_con,
2257 },
2258 [OM2K_BTS_S_WAIT_IS] = {
2259 .in_event_mask = S(OM2K_BTS_EVT_IS_DONE),
2260 .out_state_mask = S(OM2K_BTS_S_ERROR) |
2261 S(OM2K_BTS_S_WAIT_TRX),
2262 .name = "WAIT-IS",
2263 .action = om2k_bts_s_wait_is,
2264 },
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]2265 [OM2K_BTS_S_WAIT_TRX] = {
2266 .in_event_mask = S(OM2K_BTS_EVT_TRX_DONE),
2267 .out_state_mask = S(OM2K_BTS_S_ERROR) |
2268 S(OM2K_BTS_S_DONE),
2269 .name = "WAIT-TRX",
2270 .action = om2k_bts_s_wait_trx,
2271 },
2272 [OM2K_BTS_S_DONE] = {
2273 .name = "DONE",
2274 .onenter = om2k_bts_s_done_onenter,
2275 },
2276 [OM2K_BTS_S_ERROR] = {
2277 .name = "ERROR",
2278 },
2279};
2280
2281static int om2k_bts_timer_cb(struct osmo_fsm_inst *fi)
2282{
2283 osmo_fsm_inst_state_chg(fi, OM2K_BTS_S_ERROR, 0, 0);
2284 return 0;
2285}
2286
2287static struct osmo_fsm om2k_bts_fsm = {
2288 .name = "OM2000-BTS",
2289 .states = om2k_bts_states,
2290 .num_states = ARRAY_SIZE(om2k_bts_states),
2291 .log_subsys = DNM,
2292 .event_names = om2k_bts_events,
2293 .timer_cb = om2k_bts_timer_cb,
2294};
2295
2296struct osmo_fsm_inst *
2297om2k_bts_fsm_start(struct gsm_bts *bts)
2298{
2299 struct osmo_fsm_inst *fi;
2300 struct om2k_bts_fsm_priv *obfp;
2301 char idbuf[16];
2302
2303 snprintf(idbuf, sizeof(idbuf), "%u", bts->nr);
2304
2305 fi = osmo_fsm_inst_alloc(&om2k_bts_fsm, bts, NULL,
2306 LOGL_DEBUG, idbuf);
2307 if (!fi)
2308 return NULL;
2309 fi->priv = obfp = talloc_zero(fi, struct om2k_bts_fsm_priv);
2310 obfp->bts = bts;
2311
2312 osmo_fsm_inst_dispatch(fi, OM2K_BTS_EVT_START, NULL);
2313
2314 return fi;
2315}
2316
2317
2318/***********************************************************************
2319 * OM2000 Negotiation
2320 ***********************************************************************/
2321
Harald Welte6fec79d2011-02-12 14:57:17 +0100[diff] [blame]2322static int abis_om2k_tx_negot_req_ack(struct gsm_bts *bts, const struct abis_om2k_mo *mo,
Harald Welte73541072011-02-12 13:44:14 +0100[diff] [blame]2323 uint8_t *data, unsigned int len)
2324{
2325 struct msgb *msg = om2k_msgb_alloc();
2326 struct abis_om2k_hdr *o2k;
2327
2328 o2k = (struct abis_om2k_hdr *) msgb_put(msg, sizeof(*o2k));
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]2329 fill_om2k_hdr(o2k, mo, OM2K_MSGT_NEGOT_REQ_ACK);
Harald Welte73541072011-02-12 13:44:14 +0100[diff] [blame]2330
2331 msgb_tlv_put(msg, OM2K_DEI_NEGOT_REC2, len, data);
2332
2333 DEBUGP(DNM, "Tx MO=%s %s\n", om2k_mo_name(mo),
2334 get_value_string(om2k_msgcode_vals, OM2K_MSGT_NEGOT_REQ_ACK));
2335
2336 return abis_om2k_sendmsg(bts, msg);
2337}
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]2338
Harald Welte563d3162011-02-12 18:11:16 +0100[diff] [blame]2339struct iwd_version {
2340 uint8_t gen_char[3+1];
2341 uint8_t rev_char[3+1];
2342};
2343
2344struct iwd_type {
2345 uint8_t num_vers;
2346 struct iwd_version v[8];
2347};
2348
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]2349static int om2k_rx_negot_req(struct msgb *msg)
2350{
Pablo Neira Ayuso7abecfc2011-08-17 22:43:54 +0200[diff] [blame]2351 struct e1inp_sign_link *sign_link = (struct e1inp_sign_link *)msg->dst;
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]2352 struct abis_om2k_hdr *o2h = msgb_l2(msg);
Harald Welte563d3162011-02-12 18:11:16 +0100[diff] [blame]2353 struct iwd_type iwd_types[16];
2354 uint8_t num_iwd_types = o2h->data[2];
2355 uint8_t *cur = o2h->data+3;
2356 unsigned int i, v;
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]2357
Harald Welte563d3162011-02-12 18:11:16 +0100[diff] [blame]2358 uint8_t out_buf[1024];
2359 uint8_t *out_cur = out_buf+1;
2360 uint8_t out_num_types = 0;
2361
2362 memset(iwd_types, 0, sizeof(iwd_types));
2363
2364 /* Parse the RBS-supported IWD versions into iwd_types array */
2365 for (i = 0; i < num_iwd_types; i++) {
2366 uint8_t num_versions = *cur++;
2367 uint8_t iwd_type = *cur++;
2368
2369 iwd_types[iwd_type].num_vers = num_versions;
2370
2371 for (v = 0; v < num_versions; v++) {
2372 struct iwd_version *iwd_v = &iwd_types[iwd_type].v[v];
2373
2374 memcpy(iwd_v->gen_char, cur, 3);
Harald Welte56ee6b82011-02-12 18:13:37 +0100[diff] [blame]2375 cur += 3;
2376 memcpy(iwd_v->rev_char, cur, 3);
2377 cur += 3;
2378
Harald Welte563d3162011-02-12 18:11:16 +0100[diff] [blame]2379 DEBUGP(DNM, "\tIWD Type %u Gen %s Rev %s\n", iwd_type,
2380 iwd_v->gen_char, iwd_v->rev_char);
2381 }
2382 }
2383
2384 /* Select the last version for each IWD type */
2385 for (i = 0; i < ARRAY_SIZE(iwd_types); i++) {
2386 struct iwd_type *type = &iwd_types[i];
2387 struct iwd_version *last_v;
2388
2389 if (type->num_vers == 0)
2390 continue;
2391
2392 out_num_types++;
2393
2394 last_v = &type->v[type->num_vers-1];
2395
2396 *out_cur++ = i;
2397 memcpy(out_cur, last_v->gen_char, 3);
2398 out_cur += 3;
2399 memcpy(out_cur, last_v->rev_char, 3);
2400 out_cur += 3;
2401 }
2402
2403 out_buf[0] = out_num_types;
2404
Pablo Neira Ayuso7abecfc2011-08-17 22:43:54 +0200[diff] [blame]2405 return abis_om2k_tx_negot_req_ack(sign_link->trx->bts, &o2h->mo, out_buf, out_cur - out_buf);
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]2406}
2407
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]2408
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]2409/***********************************************************************
2410 * OM2000 Receive Message Handler
2411 ***********************************************************************/
Harald Weltee898ecc2011-03-06 19:26:11 +0100[diff] [blame]2412
Harald Weltee6e83832011-03-05 17:52:09 +0100[diff] [blame]2413static int om2k_rx_nack(struct msgb *msg)
2414{
2415 struct abis_om2k_hdr *o2h = msgb_l2(msg);
2416 uint16_t msg_type = ntohs(o2h->msg_type);
2417 struct tlv_parsed tp;
2418
2419 LOGP(DNM, LOGL_ERROR, "Rx MO=%s %s", om2k_mo_name(&o2h->mo),
2420 get_value_string(om2k_msgcode_vals, msg_type));
2421
Harald Weltee898ecc2011-03-06 19:26:11 +0100[diff] [blame]2422 abis_om2k_msg_tlv_parse(&tp, o2h);
Harald Weltee6e83832011-03-05 17:52:09 +0100[diff] [blame]2423 if (TLVP_PRESENT(&tp, OM2K_DEI_REASON_CODE))
2424 LOGPC(DNM, LOGL_ERROR, ", Reason 0x%02x",
2425 *TLVP_VAL(&tp, OM2K_DEI_REASON_CODE));
2426
2427 if (TLVP_PRESENT(&tp, OM2K_DEI_RESULT_CODE))
2428 LOGPC(DNM, LOGL_ERROR, ", Result %s",
2429 get_value_string(om2k_result_strings,
2430 *TLVP_VAL(&tp, OM2K_DEI_RESULT_CODE)));
2431 LOGPC(DNM, LOGL_ERROR, "\n");
2432
2433 return 0;
2434}
2435
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]2436static int process_mo_state(struct gsm_bts *bts, struct om2k_decoded_msg *odm)
Harald Weltee898ecc2011-03-06 19:26:11 +0100[diff] [blame]2437{
Harald Weltee898ecc2011-03-06 19:26:11 +0100[diff] [blame]2438 uint8_t mo_state;
2439
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]2440 if (!TLVP_PRESENT(&odm->tp, OM2K_DEI_MO_STATE))
Harald Weltee898ecc2011-03-06 19:26:11 +0100[diff] [blame]2441 return -EIO;
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]2442 mo_state = *TLVP_VAL(&odm->tp, OM2K_DEI_MO_STATE);
Harald Weltee898ecc2011-03-06 19:26:11 +0100[diff] [blame]2443
2444 LOGP(DNM, LOGL_DEBUG, "Rx MO=%s %s, MO State: %s\n",
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]2445 om2k_mo_name(&odm->o2h.mo),
2446 get_value_string(om2k_msgcode_vals, odm->msg_type),
Harald Weltee898ecc2011-03-06 19:26:11 +0100[diff] [blame]2447 get_value_string(om2k_mostate_vals, mo_state));
2448
Philippb4ecc1d2016-10-20 13:55:21 +0200[diff] [blame]2449 /* Throw error message in case we see an enable rsponse that does
2450 * not yield an enabled mo-state */
2451 if (odm->msg_type == OM2K_MSGT_ENABLE_RES
2452 && mo_state != OM2K_MO_S_ENABLED) {
2453 LOGP(DNM, LOGL_ERROR,
2454 "Rx MO=%s %s Failed to enable MO State!\n",
2455 om2k_mo_name(&odm->o2h.mo),
2456 get_value_string(om2k_msgcode_vals, odm->msg_type));
2457 }
2458
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]2459 update_mo_state(bts, &odm->o2h.mo, mo_state);
Harald Welteaf9b8102011-03-06 21:20:38 +0100[diff] [blame]2460
Harald Weltee898ecc2011-03-06 19:26:11 +0100[diff] [blame]2461 return 0;
2462}
2463
Philipp8136e4b2016-10-19 10:14:35 +0200[diff] [blame]2464/* Display fault report bits (helper function of display_fault_maps()) */
Philipp38cba5a2016-11-15 19:27:20 +0100[diff] [blame]2465static bool display_fault_bits(const uint8_t *vect, uint16_t len,
Philipp8136e4b2016-10-19 10:14:35 +0200[diff] [blame]2466 uint8_t dei, const struct abis_om2k_mo *mo)
2467{
Philipp38cba5a2016-11-15 19:27:20 +0100[diff] [blame]2468 uint16_t i;
Philipp8136e4b2016-10-19 10:14:35 +0200[diff] [blame]2469 int k;
2470 bool faults_present = false;
2471 int first = 1;
2472 char string[255];
2473
2474 /* Check if errors are present at all */
2475 for (i = 0; i < len; i++)
2476 if (vect[i])
2477 faults_present = true;
2478 if (!faults_present)
2479 return false;
2480
2481 sprintf(string, "Fault Report: %s (",
2482 get_value_string(om2k_attr_vals, dei));
2483
2484 for (i = 0; i < len; i++) {
2485 for (k = 0; k < 8; k++) {
2486 if ((vect[i] >> k) & 1) {
2487 if (!first)
2488 sprintf(string + strlen(string), ",");
2489 sprintf(string + strlen(string), "%d", k + i*8);
2490 first = 0;
2491 }
2492 }
2493 }
2494
2495 sprintf(string + strlen(string), ")\n");
2496 DEBUGP(DNM, "Rx MO=%s %s", om2k_mo_name(mo), string);
2497
2498 return true;
2499}
2500
2501/* Display fault report maps */
2502static void display_fault_maps(const uint8_t *src, unsigned int src_len,
2503 const struct abis_om2k_mo *mo)
2504{
2505 uint8_t tag;
2506 uint16_t tag_len;
2507 const uint8_t *val;
2508 int src_pos = 0;
2509 int rc;
2510 int tlv_count = 0;
2511 uint16_t msg_code;
2512 bool faults_present = false;
2513
2514 /* Chop off header */
2515 src+=4;
2516 src_len-=4;
2517
2518 /* Check message type */
2519 msg_code = (*src & 0xff) << 8;
2520 src++;
2521 src_len--;
2522 msg_code |= (*src & 0xff);
2523 src++;
2524 src_len--;
2525 if (msg_code != OM2K_MSGT_FAULT_REP) {
2526 LOGP(DNM, LOGL_ERROR, "Rx MO=%s Fault report: invalid message code!\n",
2527 om2k_mo_name(mo));
2528 return;
2529 }
2530
2531 /* Chop off mo-interface */
2532 src += 4;
2533 src_len -= 4;
2534
2535 /* Iterate over each TLV element */
2536 while (1) {
2537
2538 /* Bail if an the maximum number of TLV fields
2539 * have been parsed */
2540 if (tlv_count >= 11) {
2541 LOGP(DNM, LOGL_ERROR,
2542 "Rx MO=%s Fault Report: too many tlv elements!\n",
2543 om2k_mo_name(mo));
2544 return;
2545 }
2546
2547 /* Parse TLV field */
2548 rc = tlv_parse_one(&tag, &tag_len, &val, &om2k_att_tlvdef,
2549 src + src_pos, src_len - src_pos);
2550 if (rc > 0)
2551 src_pos += rc;
2552 else {
2553 LOGP(DNM, LOGL_ERROR,
2554 "Rx MO=%s Fault Report: invalid tlv element!\n",
2555 om2k_mo_name(mo));
2556 return;
2557 }
2558
2559 switch (tag) {
2560 case OM2K_DEI_INT_FAULT_MAP_1A:
2561 case OM2K_DEI_INT_FAULT_MAP_1B:
2562 case OM2K_DEI_INT_FAULT_MAP_2A:
2563 case OM2K_DEI_EXT_COND_MAP_1:
2564 case OM2K_DEI_EXT_COND_MAP_2:
2565 case OM2K_DEI_REPL_UNIT_MAP:
2566 case OM2K_DEI_INT_FAULT_MAP_2A_EXT:
2567 case OM2K_DEI_EXT_COND_MAP_2_EXT:
2568 case OM2K_DEI_REPL_UNIT_MAP_EXT:
2569 faults_present |= display_fault_bits(val, tag_len,
2570 tag, mo);
2571 break;
2572 }
2573
2574 /* Stop when no further TLV elements can be expected */
2575 if (src_len - src_pos < 2)
2576 break;
2577
2578 tlv_count++;
2579 }
2580
2581 if (!faults_present) {
2582 DEBUGP(DNM, "Rx MO=%s Fault Report: All faults ceased!\n",
2583 om2k_mo_name(mo));
2584 }
2585}
2586
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]2587int abis_om2k_rcvmsg(struct msgb *msg)
2588{
Pablo Neira Ayuso7abecfc2011-08-17 22:43:54 +0200[diff] [blame]2589 struct e1inp_sign_link *sign_link = (struct e1inp_sign_link *)msg->dst;
2590 struct gsm_bts *bts = sign_link->trx->bts;
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]2591 struct abis_om2k_hdr *o2h = msgb_l2(msg);
2592 struct abis_om_hdr *oh = &o2h->om;
Harald Weltebc867d92011-02-12 13:09:38 +0100[diff] [blame]2593 uint16_t msg_type = ntohs(o2h->msg_type);
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]2594 struct om2k_decoded_msg odm;
2595 struct om2k_mo *mo;
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]2596 int rc = 0;
2597
2598 /* Various consistency checks */
2599 if (oh->placement != ABIS_OM_PLACEMENT_ONLY) {
2600 LOGP(DNM, LOGL_ERROR, "ABIS OML placement 0x%x not supported\n",
2601 oh->placement);
2602 if (oh->placement != ABIS_OM_PLACEMENT_FIRST)
2603 return -EINVAL;
2604 }
2605 if (oh->sequence != 0) {
2606 LOGP(DNM, LOGL_ERROR, "ABIS OML sequence 0x%x != 0x00\n",
2607 oh->sequence);
2608 return -EINVAL;
2609 }
2610
2611 msg->l3h = (unsigned char *)o2h + sizeof(*o2h);
2612
2613 if (oh->mdisc != ABIS_OM_MDISC_FOM) {
2614 LOGP(DNM, LOGL_ERROR, "unknown ABIS OM2000 message discriminator 0x%x\n",
2615 oh->mdisc);
2616 return -EINVAL;
2617 }
2618
Harald Welte73541072011-02-12 13:44:14 +0100[diff] [blame]2619 DEBUGP(DNM, "Rx MO=%s %s (%s)\n", om2k_mo_name(&o2h->mo),
Harald Weltebc867d92011-02-12 13:09:38 +0100[diff] [blame]2620 get_value_string(om2k_msgcode_vals, msg_type),
Pablo Neira Ayusoc0d17f22011-05-07 12:12:48 +0200[diff] [blame]2621 osmo_hexdump(msg->l2h, msgb_l2len(msg)));
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]2622
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]2623 om2k_decode_msg(&odm, msg);
2624
2625 process_mo_state(bts, &odm);
2626
Harald Weltebc867d92011-02-12 13:09:38 +0100[diff] [blame]2627 switch (msg_type) {
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]2628 case OM2K_MSGT_CAL_TIME_REQ:
2629 rc = abis_om2k_cal_time_resp(bts);
2630 break;
2631 case OM2K_MSGT_FAULT_REP:
Philipp8136e4b2016-10-19 10:14:35 +0200[diff] [blame]2632 display_fault_maps(msg->l2h, msgb_l2len(msg), &o2h->mo);
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]2633 rc = abis_om2k_tx_simple(bts, &o2h->mo, OM2K_MSGT_FAULT_REP_ACK);
2634 break;
2635 case OM2K_MSGT_NEGOT_REQ:
2636 rc = om2k_rx_negot_req(msg);
2637 break;
2638 case OM2K_MSGT_START_RES:
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]2639 /* common processing here */
2640 rc = abis_om2k_tx_simple(bts, &o2h->mo, OM2K_MSGT_START_RES_ACK);
2641 /* below we dispatch into MO */
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]2642 break;
2643 case OM2K_MSGT_IS_CONF_RES:
2644 rc = abis_om2k_tx_simple(bts, &o2h->mo, OM2K_MSGT_IS_CONF_RES_ACK);
2645 break;
Harald Weltefdb71942011-02-14 15:31:43 +0100[diff] [blame]2646 case OM2K_MSGT_CON_CONF_RES:
2647 rc = abis_om2k_tx_simple(bts, &o2h->mo, OM2K_MSGT_CON_CONF_RES_ACK);
2648 break;
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]2649 case OM2K_MSGT_TX_CONF_RES:
2650 rc = abis_om2k_tx_simple(bts, &o2h->mo, OM2K_MSGT_TX_CONF_RES_ACK);
2651 break;
2652 case OM2K_MSGT_RX_CONF_RES:
2653 rc = abis_om2k_tx_simple(bts, &o2h->mo, OM2K_MSGT_RX_CONF_RES_ACK);
2654 break;
2655 case OM2K_MSGT_TS_CONF_RES:
2656 rc = abis_om2k_tx_simple(bts, &o2h->mo, OM2K_MSGT_TS_CONF_RES_ACK);
2657 break;
Harald Weltef9cf9612011-03-05 14:36:47 +0100[diff] [blame]2658 case OM2K_MSGT_TF_CONF_RES:
2659 rc = abis_om2k_tx_simple(bts, &o2h->mo, OM2K_MSGT_TF_CONF_RES_ACK);
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]2660 break;
Harald Welteb3d70fd2011-02-13 12:43:44 +0100[diff] [blame]2661 case OM2K_MSGT_ENABLE_RES:
2662 rc = abis_om2k_tx_simple(bts, &o2h->mo, OM2K_MSGT_ENABLE_RES_ACK);
2663 break;
Harald Weltefdb71942011-02-14 15:31:43 +0100[diff] [blame]2664 case OM2K_MSGT_DISABLE_RES:
2665 rc = abis_om2k_tx_simple(bts, &o2h->mo, OM2K_MSGT_DISABLE_RES_ACK);
2666 break;
2667 case OM2K_MSGT_TEST_RES:
2668 rc = abis_om2k_tx_simple(bts, &o2h->mo, OM2K_MSGT_TEST_RES_ACK);
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]2669 break;
root45799782016-10-15 21:24:57 +0200[diff] [blame]2670 case OM2K_MSGT_CAPA_RES:
2671 rc = abis_om2k_tx_simple(bts, &o2h->mo, OM2K_MSGT_CAPA_RES_ACK);
2672 break;
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]2673 /* ERrors */
Harald Weltee6e83832011-03-05 17:52:09 +0100[diff] [blame]2674 case OM2K_MSGT_START_REQ_REJ:
Harald Welte3ede7232011-03-05 17:58:13 +0100[diff] [blame]2675 case OM2K_MSGT_CONNECT_REJ:
Harald Welteaff63bc2011-03-05 19:42:16 +0100[diff] [blame]2676 case OM2K_MSGT_OP_INFO_REJ:
Harald Welte3ede7232011-03-05 17:58:13 +0100[diff] [blame]2677 case OM2K_MSGT_DISCONNECT_REJ:
Harald Welteaff63bc2011-03-05 19:42:16 +0100[diff] [blame]2678 case OM2K_MSGT_TEST_REQ_REJ:
Harald Weltee6e83832011-03-05 17:52:09 +0100[diff] [blame]2679 case OM2K_MSGT_CON_CONF_REQ_REJ:
2680 case OM2K_MSGT_IS_CONF_REQ_REJ:
2681 case OM2K_MSGT_TX_CONF_REQ_REJ:
2682 case OM2K_MSGT_RX_CONF_REQ_REJ:
2683 case OM2K_MSGT_TS_CONF_REQ_REJ:
2684 case OM2K_MSGT_TF_CONF_REQ_REJ:
2685 case OM2K_MSGT_ENABLE_REQ_REJ:
2686 case OM2K_MSGT_ALARM_STATUS_REQ_REJ:
2687 case OM2K_MSGT_DISABLE_REQ_REJ:
2688 rc = om2k_rx_nack(msg);
2689 break;
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]2690 }
2691
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]2692 /* Resolve the MO for this message */
2693 mo = get_om2k_mo(bts, &o2h->mo);
2694 if (!mo) {
2695 LOGP(DNM, LOGL_ERROR, "Couldn't resolve MO for OM2K msg "
2696 "%s: %s\n", get_value_string(om2k_msgcode_vals, msg_type),
2697 msgb_hexdump(msg));
2698 return 0;
2699 }
2700
2701 /* Dispatch message to that MO */
2702 om2k_mo_fsm_recvmsg(bts, mo, &odm);
2703
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]2704 msgb_free(msg);
2705 return rc;
2706}
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]2707
2708static void om2k_mo_init(struct om2k_mo *mo, uint8_t class,
2709 uint8_t bts_nr, uint8_t assoc_so, uint8_t inst)
2710{
2711 mo->addr.class = class;
2712 mo->addr.bts = bts_nr;
2713 mo->addr.assoc_so = assoc_so;
2714 mo->addr.inst = inst;
2715}
2716
2717/* initialize the OM2K_MO members of gsm_bts_trx and its timeslots */
2718void abis_om2k_trx_init(struct gsm_bts_trx *trx)
2719{
2720 struct gsm_bts *bts = trx->bts;
2721 unsigned int i;
2722
2723 OSMO_ASSERT(bts->type == GSM_BTS_TYPE_RBS2000);
2724
2725 om2k_mo_init(&trx->rbs2000.trxc.om2k_mo, OM2K_MO_CLS_TRXC,
2726 bts->nr, 255, trx->nr);
2727 om2k_mo_init(&trx->rbs2000.tx.om2k_mo, OM2K_MO_CLS_TX,
2728 bts->nr, 255, trx->nr);
2729 om2k_mo_init(&trx->rbs2000.rx.om2k_mo, OM2K_MO_CLS_RX,
2730 bts->nr, 255, trx->nr);
2731
2732 for (i = 0; i < ARRAY_SIZE(trx->ts); i++) {
2733 om2k_mo_init(&trx->ts[i].rbs2000.om2k_mo, OM2K_MO_CLS_TS,
2734 bts->nr, trx->nr, i);
2735 }
2736}
2737
2738/* initialize the OM2K_MO members of gsm_bts */
2739void abis_om2k_bts_init(struct gsm_bts *bts)
2740{
2741 OSMO_ASSERT(bts->type == GSM_BTS_TYPE_RBS2000);
2742
2743 om2k_mo_init(&bts->rbs2000.cf.om2k_mo, OM2K_MO_CLS_CF,
2744 bts->nr, 0xFF, 0);
2745 om2k_mo_init(&bts->rbs2000.is.om2k_mo, OM2K_MO_CLS_IS,
2746 bts->nr, 0xFF, 0);
2747 om2k_mo_init(&bts->rbs2000.con.om2k_mo, OM2K_MO_CLS_CON,
2748 bts->nr, 0xFF, 0);
2749 om2k_mo_init(&bts->rbs2000.dp.om2k_mo, OM2K_MO_CLS_DP,
2750 bts->nr, 0xFF, 0);
2751 om2k_mo_init(&bts->rbs2000.tf.om2k_mo, OM2K_MO_CLS_TF,
2752 bts->nr, 0xFF, 0);
2753}
2754
2755static __attribute__((constructor)) void abis_om2k_init(void)
2756{
2757 osmo_fsm_register(&om2k_mo_fsm);
2758 osmo_fsm_register(&om2k_bts_fsm);
2759 osmo_fsm_register(&om2k_trx_fsm);
2760}