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gerrit.osmocom.org / osmo-msc / 2d02775b919d4d56b960cd76b792db95aee539dc / . / openbsc / src / libbsc / abis_om2000.c
blob: 6c987d8d23de22de5b665df5ff58809c828bea7a [file] [log] [blame]
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]1/* Ericsson RBS 2xxx GSM O&M (OM2000) messages on the A-bis interface
2 * implemented based on protocol trace analysis, no formal documentation */
3
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]4/* (C) 2010-2011,2016 by Harald Welte <laforge@gnumonks.org>
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]5 *
6 * All Rights Reserved
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU Affero General Public License as published by
10 * the Free Software Foundation; either version 3 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU Affero General Public License for more details.
17 *
18 * You should have received a copy of the GNU Affero General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 *
21 */
22
23
24#include <errno.h>
25#include <unistd.h>
26#include <stdio.h>
27#include <stdlib.h>
28#include <time.h>
29#include <stdint.h>
30
31#include <arpa/inet.h>
32
Pablo Neira Ayuso136f4532011-03-22 16:47:59 +0100[diff] [blame]33#include <osmocom/core/msgb.h>
34#include <osmocom/gsm/tlv.h>
35#include <osmocom/core/talloc.h>
36#include <osmocom/core/utils.h>
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]37#include <osmocom/core/fsm.h>
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]38
39#include <openbsc/gsm_data.h>
40#include <openbsc/debug.h>
41#include <openbsc/abis_nm.h>
Harald Welte80ccb952016-11-15 23:23:42 +0100[diff] [blame]42#include <openbsc/abis_rsl.h>
Harald Welte73541072011-02-12 13:44:14 +0100[diff] [blame]43#include <openbsc/abis_om2000.h>
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]44#include <openbsc/signal.h>
Pablo Neira Ayusoed5cacb2011-08-17 22:44:07 +0200[diff] [blame]45#include <osmocom/abis/e1_input.h>
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]46
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]47/* FIXME: move to libosmocore */
48struct osmo_fsm_inst *osmo_fsm_inst_alloc_child_id(struct osmo_fsm *fsm,
49 struct osmo_fsm_inst *parent,
50 uint32_t parent_term_event,
51 const char *id)
52{
53 struct osmo_fsm_inst *fi;
54
55 fi = osmo_fsm_inst_alloc(fsm, parent, NULL, parent->log_level,
56 id ? id : parent->id);
57 if (!fi) {
58 /* indicate immediate termination to caller */
59 osmo_fsm_inst_dispatch(parent, parent_term_event, NULL);
60 return NULL;
61 }
62
63 LOGPFSM(fi, "is child of %s\n", osmo_fsm_inst_name(parent));
64
65 fi->proc.parent = parent;
66 fi->proc.parent_term_event = parent_term_event;
67 llist_add(&fi->proc.child, &parent->proc.children);
68
69 return fi;
70}
71
72
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]73#define OM_ALLOC_SIZE 1024
74#define OM_HEADROOM_SIZE 128
75
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]76#define OM2K_TIMEOUT 10
77#define TRX_FSM_TIMEOUT 60
78#define BTS_FSM_TIMEOUT 60
79
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]80/* use following functions from abis_nm.c:
81 * om2k_msgb_alloc()
Harald Weltebc867d92011-02-12 13:09:38 +0100[diff] [blame]82 * abis_om2k_sendmsg()
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]83 */
84
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]85struct abis_om2k_hdr {
86 struct abis_om_hdr om;
87 uint16_t msg_type;
88 struct abis_om2k_mo mo;
89 uint8_t data[0];
90} __attribute__ ((packed));
91
92enum abis_om2k_msgtype {
93 OM2K_MSGT_ABORT_SP_CMD = 0x0000,
94 OM2K_MSGT_ABORT_SP_COMPL = 0x0002,
95 OM2K_MSGT_ALARM_REP_ACK = 0x0004,
96 OM2K_MSGT_ALARM_REP_NACK = 0x0005,
97 OM2K_MSGT_ALARM_REP = 0x0006,
98 OM2K_MSGT_ALARM_STATUS_REQ = 0x0008,
99 OM2K_MSGT_ALARM_STATUS_REQ_ACK = 0x000a,
100 OM2K_MSGT_ALARM_STATUS_REQ_REJ = 0x000b,
101 OM2K_MSGT_ALARM_STATUS_RES_ACK = 0x000c,
102 OM2K_MSGT_ALARM_STATUS_RES_NACK = 0x000d,
103 OM2K_MSGT_ALARM_STATUS_RES = 0x000e,
104 OM2K_MSGT_CAL_TIME_RESP = 0x0010,
105 OM2K_MSGT_CAL_TIME_REJ = 0x0011,
106 OM2K_MSGT_CAL_TIME_REQ = 0x0012,
107
Harald Weltefdb71942011-02-14 15:31:43 +0100[diff] [blame]108 OM2K_MSGT_CON_CONF_REQ = 0x0014,
109 OM2K_MSGT_CON_CONF_REQ_ACK = 0x0016,
110 OM2K_MSGT_CON_CONF_REQ_REJ = 0x0017,
111 OM2K_MSGT_CON_CONF_RES_ACK = 0x0018,
112 OM2K_MSGT_CON_CONF_RES_NACK = 0x0019,
113 OM2K_MSGT_CON_CONF_RES = 0x001a,
114
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]115 OM2K_MSGT_CONNECT_CMD = 0x001c,
116 OM2K_MSGT_CONNECT_COMPL = 0x001e,
117 OM2K_MSGT_CONNECT_REJ = 0x001f,
118
Harald Welte0741ffe2011-02-12 18:48:53 +0100[diff] [blame]119 OM2K_MSGT_DISABLE_REQ = 0x0028,
120 OM2K_MSGT_DISABLE_REQ_ACK = 0x002a,
121 OM2K_MSGT_DISABLE_REQ_REJ = 0x002b,
122 OM2K_MSGT_DISABLE_RES_ACK = 0x002c,
123 OM2K_MSGT_DISABLE_RES_NACK = 0x002d,
124 OM2K_MSGT_DISABLE_RES = 0x002e,
Harald Welte6fec79d2011-02-12 14:57:17 +0100[diff] [blame]125 OM2K_MSGT_DISCONNECT_CMD = 0x0030,
126 OM2K_MSGT_DISCONNECT_COMPL = 0x0032,
127 OM2K_MSGT_DISCONNECT_REJ = 0x0033,
Harald Welte0741ffe2011-02-12 18:48:53 +0100[diff] [blame]128 OM2K_MSGT_ENABLE_REQ = 0x0034,
129 OM2K_MSGT_ENABLE_REQ_ACK = 0x0036,
130 OM2K_MSGT_ENABLE_REQ_REJ = 0x0037,
131 OM2K_MSGT_ENABLE_RES_ACK = 0x0038,
132 OM2K_MSGT_ENABLE_RES_NACK = 0x0039,
133 OM2K_MSGT_ENABLE_RES = 0x003a,
Harald Welte6fec79d2011-02-12 14:57:17 +0100[diff] [blame]134
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]135 OM2K_MSGT_FAULT_REP_ACK = 0x0040,
136 OM2K_MSGT_FAULT_REP_NACK = 0x0041,
137 OM2K_MSGT_FAULT_REP = 0x0042,
138
139 OM2K_MSGT_IS_CONF_REQ = 0x0060,
140 OM2K_MSGT_IS_CONF_REQ_ACK = 0x0062,
141 OM2K_MSGT_IS_CONF_REQ_REJ = 0x0063,
142 OM2K_MSGT_IS_CONF_RES_ACK = 0x0064,
143 OM2K_MSGT_IS_CONF_RES_NACK = 0x0065,
144 OM2K_MSGT_IS_CONF_RES = 0x0066,
145
146 OM2K_MSGT_OP_INFO = 0x0074,
147 OM2K_MSGT_OP_INFO_ACK = 0x0076,
148 OM2K_MSGT_OP_INFO_REJ = 0x0077,
149 OM2K_MSGT_RESET_CMD = 0x0078,
150 OM2K_MSGT_RESET_COMPL = 0x007a,
151 OM2K_MSGT_RESET_REJ = 0x007b,
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]152 OM2K_MSGT_RX_CONF_REQ = 0x007c,
153 OM2K_MSGT_RX_CONF_REQ_ACK = 0x007e,
154 OM2K_MSGT_RX_CONF_REQ_REJ = 0x007f,
155 OM2K_MSGT_RX_CONF_RES_ACK = 0x0080,
156 OM2K_MSGT_RX_CONF_RES_NACK = 0x0081,
157 OM2K_MSGT_RX_CONF_RES = 0x0082,
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]158 OM2K_MSGT_START_REQ = 0x0084,
159 OM2K_MSGT_START_REQ_ACK = 0x0086,
160 OM2K_MSGT_START_REQ_REJ = 0x0087,
161 OM2K_MSGT_START_RES_ACK = 0x0088,
162 OM2K_MSGT_START_RES_NACK = 0x0089,
163 OM2K_MSGT_START_RES = 0x008a,
Harald Weltee1d5eca2011-02-12 14:42:59 +0100[diff] [blame]164 OM2K_MSGT_STATUS_REQ = 0x008c,
165 OM2K_MSGT_STATUS_RESP = 0x008e,
166 OM2K_MSGT_STATUS_REJ = 0x008f,
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]167
Harald Welte8024d8f2011-02-12 15:07:30 +0100[diff] [blame]168 OM2K_MSGT_TEST_REQ = 0x0094,
169 OM2K_MSGT_TEST_REQ_ACK = 0x0096,
170 OM2K_MSGT_TEST_REQ_REJ = 0x0097,
171 OM2K_MSGT_TEST_RES_ACK = 0x0098,
172 OM2K_MSGT_TEST_RES_NACK = 0x0099,
173 OM2K_MSGT_TEST_RES = 0x009a,
174
Harald Weltef9cf9612011-03-05 14:36:47 +0100[diff] [blame]175 OM2K_MSGT_TF_CONF_REQ = 0x00a0,
176 OM2K_MSGT_TF_CONF_REQ_ACK = 0x00a2,
177 OM2K_MSGT_TF_CONF_REQ_REJ = 0x00a3,
178 OM2K_MSGT_TF_CONF_RES_ACK = 0x00a4,
179 OM2K_MSGT_TF_CONF_RES_NACK = 0x00a5,
180 OM2K_MSGT_TF_CONF_RES = 0x00a6,
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]181 OM2K_MSGT_TS_CONF_REQ = 0x00a8,
182 OM2K_MSGT_TS_CONF_REQ_ACK = 0x00aa,
183 OM2K_MSGT_TS_CONF_REQ_REJ = 0x00ab,
184 OM2K_MSGT_TS_CONF_RES_ACK = 0x00ac,
185 OM2K_MSGT_TS_CONF_RES_NACK = 0x00ad,
186 OM2K_MSGT_TS_CONF_RES = 0x00ae,
187 OM2K_MSGT_TX_CONF_REQ = 0x00b0,
188 OM2K_MSGT_TX_CONF_REQ_ACK = 0x00b2,
189 OM2K_MSGT_TX_CONF_REQ_REJ = 0x00b3,
190 OM2K_MSGT_TX_CONF_RES_ACK = 0x00b4,
191 OM2K_MSGT_TX_CONF_RES_NACK = 0x00b5,
192 OM2K_MSGT_TX_CONF_RES = 0x00b6,
193
root45799782016-10-15 21:24:57 +0200[diff] [blame]194 OM2K_MSGT_CAPA_REQ = 0x00e8,
195 OM2K_MSGT_CAPA_REQ_ACK = 0x00ea,
196 OM2K_MSGT_CAPA_REQ_REJ = 0x00eb,
197 OM2K_MSGT_CAPA_RES = 0x00ee,
198 OM2K_MSGT_CAPA_RES_ACK = 0x00ec,
199 OM2K_MSGT_CAPA_RES_NACK = 0x00ed,
200
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]201 OM2K_MSGT_NEGOT_REQ_ACK = 0x0104,
202 OM2K_MSGT_NEGOT_REQ_NACK = 0x0105,
203 OM2K_MSGT_NEGOT_REQ = 0x0106,
204};
205
206enum abis_om2k_dei {
Harald Weltee898ecc2011-03-06 19:26:11 +0100[diff] [blame]207 OM2K_DEI_ACCORDANCE_IND = 0x00,
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]208 OM2K_DEI_BCC = 0x06,
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]209 OM2K_DEI_BS_AG_BKS_RES = 0x07,
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]210 OM2K_DEI_BSIC = 0x09,
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]211 OM2K_DEI_BA_PA_MFRMS = 0x0a,
212 OM2K_DEI_CBCH_INDICATOR = 0x0b,
213 OM2K_DEI_CCCH_OPTIONS = 0x0c,
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]214 OM2K_DEI_CAL_TIME = 0x0d,
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]215 OM2K_DEI_COMBINATION = 0x0f,
Harald Weltefdb71942011-02-14 15:31:43 +0100[diff] [blame]216 OM2K_DEI_CON_CONN_LIST = 0x10,
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]217 OM2K_DEI_DRX_DEV_MAX = 0x12,
Harald Welte8bcb1a02011-02-12 20:23:40 +0100[diff] [blame]218 OM2K_DEI_END_LIST_NR = 0x13,
Harald Weltef6d6b212011-03-05 20:13:52 +0100[diff] [blame]219 OM2K_DEI_EXT_COND_MAP_1 = 0x14,
220 OM2K_DEI_EXT_COND_MAP_2 = 0x15,
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]221 OM2K_DEI_FILLING_MARKER = 0x1c,
222 OM2K_DEI_FN_OFFSET = 0x1d,
223 OM2K_DEI_FREQ_LIST = 0x1e,
224 OM2K_DEI_FREQ_SPEC_RX = 0x1f,
225 OM2K_DEI_FREQ_SPEC_TX = 0x20,
226 OM2K_DEI_HSN = 0x21,
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]227 OM2K_DEI_ICM_INDICATOR = 0x22,
Harald Weltef6d6b212011-03-05 20:13:52 +0100[diff] [blame]228 OM2K_DEI_INT_FAULT_MAP_1A = 0x23,
229 OM2K_DEI_INT_FAULT_MAP_1B = 0x24,
230 OM2K_DEI_INT_FAULT_MAP_2A = 0x25,
231 OM2K_DEI_INT_FAULT_MAP_2A_EXT = 0x26,
Harald Welte8bcb1a02011-02-12 20:23:40 +0100[diff] [blame]232 OM2K_DEI_IS_CONN_LIST = 0x27,
233 OM2K_DEI_LIST_NR = 0x28,
Harald Weltef6d6b212011-03-05 20:13:52 +0100[diff] [blame]234 OM2K_DEI_LOCAL_ACCESS = 0x2a,
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]235 OM2K_DEI_MAIO = 0x2b,
Harald Weltef6d6b212011-03-05 20:13:52 +0100[diff] [blame]236 OM2K_DEI_MO_STATE = 0x2c,
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]237 OM2K_DEI_NY1 = 0x2d,
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]238 OM2K_DEI_OP_INFO = 0x2e,
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]239 OM2K_DEI_POWER = 0x2f,
Harald Weltee6e83832011-03-05 17:52:09 +0100[diff] [blame]240 OM2K_DEI_REASON_CODE = 0x32,
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]241 OM2K_DEI_RX_DIVERSITY = 0x33,
Philipp8136e4b2016-10-19 10:14:35 +0200[diff] [blame]242 OM2K_DEI_REPL_UNIT_MAP = 0x34,
Harald Weltee6e83832011-03-05 17:52:09 +0100[diff] [blame]243 OM2K_DEI_RESULT_CODE = 0x35,
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]244 OM2K_DEI_T3105 = 0x38,
Harald Weltef9cf9612011-03-05 14:36:47 +0100[diff] [blame]245 OM2K_DEI_TF_MODE = 0x3a,
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]246 OM2K_DEI_TS_NR = 0x3c,
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]247 OM2K_DEI_TSC = 0x3d,
Harald Weltef6d6b212011-03-05 20:13:52 +0100[diff] [blame]248 OM2K_DEI_BTS_VERSION = 0x40,
249 OM2K_DEI_OML_IWD_VERSION = 0x41,
250 OM2K_DEI_RSL_IWD_VERSION = 0x42,
251 OM2K_DEI_OML_FUNC_MAP_1 = 0x43,
252 OM2K_DEI_OML_FUNC_MAP_2 = 0x44,
253 OM2K_DEI_RSL_FUNC_MAP_1 = 0x45,
254 OM2K_DEI_RSL_FUNC_MAP_2 = 0x46,
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]255 OM2K_DEI_EXT_RANGE = 0x47,
Harald Weltef6d6b212011-03-05 20:13:52 +0100[diff] [blame]256 OM2K_DEI_REQ_IND = 0x48,
Philipp8136e4b2016-10-19 10:14:35 +0200[diff] [blame]257 OM2K_DEI_REPL_UNIT_MAP_EXT = 0x50,
Harald Welte75755c52011-03-05 20:38:35 +0100[diff] [blame]258 OM2K_DEI_ICM_BOUND_PARAMS = 0x74,
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]259 OM2K_DEI_LSC = 0x79,
260 OM2K_DEI_LSC_FILT_TIME = 0x7a,
261 OM2K_DEI_CALL_SUPV_TIME = 0x7b,
Harald Welte75755c52011-03-05 20:38:35 +0100[diff] [blame]262 OM2K_DEI_ICM_CHAN_RATE = 0x7e,
Harald Weltef6d6b212011-03-05 20:13:52 +0100[diff] [blame]263 OM2K_DEI_HW_INFO_SIG = 0x84,
Harald Welteba9adbb2011-03-06 19:01:16 +0100[diff] [blame]264 OM2K_DEI_TF_SYNC_SRC = 0x86,
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]265 OM2K_DEI_TTA = 0x87,
Harald Weltef6d6b212011-03-05 20:13:52 +0100[diff] [blame]266 OM2K_DEI_CAPA_SIG = 0x8a,
Harald Welte73541072011-02-12 13:44:14 +0100[diff] [blame]267 OM2K_DEI_NEGOT_REC1 = 0x90,
268 OM2K_DEI_NEGOT_REC2 = 0x91,
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]269 OM2K_DEI_ENCR_ALG = 0x92,
270 OM2K_DEI_INTERF_REJ_COMB = 0x94,
Harald Weltef9cf9612011-03-05 14:36:47 +0100[diff] [blame]271 OM2K_DEI_FS_OFFSET = 0x98,
Harald Weltef6d6b212011-03-05 20:13:52 +0100[diff] [blame]272 OM2K_DEI_EXT_COND_MAP_2_EXT = 0x9c,
Philipp8136e4b2016-10-19 10:14:35 +0200[diff] [blame]273 OM2K_DEI_TSS_MO_STATE = 0x9d,
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]274};
275
Harald Weltee6e83832011-03-05 17:52:09 +0100[diff] [blame]276const struct tlv_definition om2k_att_tlvdef = {
277 .def = {
Harald Weltee898ecc2011-03-06 19:26:11 +0100[diff] [blame]278 [OM2K_DEI_ACCORDANCE_IND] = { TLV_TYPE_TV },
Harald Weltee6e83832011-03-05 17:52:09 +0100[diff] [blame]279 [OM2K_DEI_BCC] = { TLV_TYPE_TV },
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]280 [OM2K_DEI_BS_AG_BKS_RES] = { TLV_TYPE_TV },
Harald Weltee6e83832011-03-05 17:52:09 +0100[diff] [blame]281 [OM2K_DEI_BSIC] = { TLV_TYPE_TV },
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]282 [OM2K_DEI_BA_PA_MFRMS] = { TLV_TYPE_TV },
283 [OM2K_DEI_CBCH_INDICATOR] = { TLV_TYPE_TV },
Harald Weltef6d6b212011-03-05 20:13:52 +0100[diff] [blame]284 [OM2K_DEI_INT_FAULT_MAP_1A] = { TLV_TYPE_FIXED, 6 },
285 [OM2K_DEI_INT_FAULT_MAP_1B] = { TLV_TYPE_FIXED, 6 },
286 [OM2K_DEI_INT_FAULT_MAP_2A] = { TLV_TYPE_FIXED, 6 },
287 [OM2K_DEI_INT_FAULT_MAP_2A_EXT]={ TLV_TYPE_FIXED, 6 },
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]288 [OM2K_DEI_CCCH_OPTIONS] = { TLV_TYPE_TV },
Harald Weltee6e83832011-03-05 17:52:09 +0100[diff] [blame]289 [OM2K_DEI_CAL_TIME] = { TLV_TYPE_FIXED, 6 },
290 [OM2K_DEI_COMBINATION] = { TLV_TYPE_TV },
291 [OM2K_DEI_CON_CONN_LIST] = { TLV_TYPE_TLV },
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]292 [OM2K_DEI_DRX_DEV_MAX] = { TLV_TYPE_TV },
Harald Weltee6e83832011-03-05 17:52:09 +0100[diff] [blame]293 [OM2K_DEI_END_LIST_NR] = { TLV_TYPE_TV },
Harald Weltef6d6b212011-03-05 20:13:52 +0100[diff] [blame]294 [OM2K_DEI_EXT_COND_MAP_1] = { TLV_TYPE_FIXED, 2 },
295 [OM2K_DEI_EXT_COND_MAP_2] = { TLV_TYPE_FIXED, 2 },
Harald Weltee6e83832011-03-05 17:52:09 +0100[diff] [blame]296 [OM2K_DEI_FILLING_MARKER] = { TLV_TYPE_TV },
297 [OM2K_DEI_FN_OFFSET] = { TLV_TYPE_FIXED, 2 },
298 [OM2K_DEI_FREQ_LIST] = { TLV_TYPE_TLV },
299 [OM2K_DEI_FREQ_SPEC_RX] = { TLV_TYPE_FIXED, 2 },
300 [OM2K_DEI_FREQ_SPEC_TX] = { TLV_TYPE_FIXED, 2 },
301 [OM2K_DEI_HSN] = { TLV_TYPE_TV },
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]302 [OM2K_DEI_ICM_INDICATOR] = { TLV_TYPE_TV },
Harald Weltee6e83832011-03-05 17:52:09 +0100[diff] [blame]303 [OM2K_DEI_IS_CONN_LIST] = { TLV_TYPE_TLV },
304 [OM2K_DEI_LIST_NR] = { TLV_TYPE_TV },
Harald Weltef6d6b212011-03-05 20:13:52 +0100[diff] [blame]305 [OM2K_DEI_LOCAL_ACCESS] = { TLV_TYPE_TV },
Harald Weltee6e83832011-03-05 17:52:09 +0100[diff] [blame]306 [OM2K_DEI_MAIO] = { TLV_TYPE_TV },
Harald Weltef6d6b212011-03-05 20:13:52 +0100[diff] [blame]307 [OM2K_DEI_MO_STATE] = { TLV_TYPE_TV },
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]308 [OM2K_DEI_NY1] = { TLV_TYPE_TV },
Harald Weltee6e83832011-03-05 17:52:09 +0100[diff] [blame]309 [OM2K_DEI_OP_INFO] = { TLV_TYPE_TV },
310 [OM2K_DEI_POWER] = { TLV_TYPE_TV },
311 [OM2K_DEI_REASON_CODE] = { TLV_TYPE_TV },
312 [OM2K_DEI_RX_DIVERSITY] = { TLV_TYPE_TV },
313 [OM2K_DEI_RESULT_CODE] = { TLV_TYPE_TV },
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]314 [OM2K_DEI_T3105] = { TLV_TYPE_TV },
Harald Weltee6e83832011-03-05 17:52:09 +0100[diff] [blame]315 [OM2K_DEI_TF_MODE] = { TLV_TYPE_TV },
316 [OM2K_DEI_TS_NR] = { TLV_TYPE_TV },
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]317 [OM2K_DEI_TSC] = { TLV_TYPE_TV },
Harald Weltef6d6b212011-03-05 20:13:52 +0100[diff] [blame]318 [OM2K_DEI_BTS_VERSION] = { TLV_TYPE_FIXED, 12 },
319 [OM2K_DEI_OML_IWD_VERSION] = { TLV_TYPE_FIXED, 6 },
320 [OM2K_DEI_RSL_IWD_VERSION] = { TLV_TYPE_FIXED, 6 },
321 [OM2K_DEI_OML_FUNC_MAP_1] = { TLV_TYPE_TLV },
322 [OM2K_DEI_OML_FUNC_MAP_2] = { TLV_TYPE_TLV },
323 [OM2K_DEI_RSL_FUNC_MAP_1] = { TLV_TYPE_TLV },
324 [OM2K_DEI_RSL_FUNC_MAP_2] = { TLV_TYPE_TLV },
Harald Weltee6e83832011-03-05 17:52:09 +0100[diff] [blame]325 [OM2K_DEI_EXT_RANGE] = { TLV_TYPE_TV },
Harald Weltef6d6b212011-03-05 20:13:52 +0100[diff] [blame]326 [OM2K_DEI_REQ_IND] = { TLV_TYPE_TV },
327 [OM2K_DEI_REPL_UNIT_MAP] = { TLV_TYPE_FIXED, 6 },
Philipp8136e4b2016-10-19 10:14:35 +0200[diff] [blame]328 [OM2K_DEI_REPL_UNIT_MAP_EXT] = {TLV_TYPE_FIXED, 6},
Harald Welte75755c52011-03-05 20:38:35 +0100[diff] [blame]329 [OM2K_DEI_ICM_BOUND_PARAMS] = { TLV_TYPE_FIXED, 5 },
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]330 [OM2K_DEI_LSC] = { TLV_TYPE_TV },
331 [OM2K_DEI_LSC_FILT_TIME] = { TLV_TYPE_TV },
332 [OM2K_DEI_CALL_SUPV_TIME] = { TLV_TYPE_TV },
Harald Welte75755c52011-03-05 20:38:35 +0100[diff] [blame]333 [OM2K_DEI_ICM_CHAN_RATE] = { TLV_TYPE_TV },
Harald Weltef6d6b212011-03-05 20:13:52 +0100[diff] [blame]334 [OM2K_DEI_HW_INFO_SIG] = { TLV_TYPE_FIXED, 2 },
Harald Welteba9adbb2011-03-06 19:01:16 +0100[diff] [blame]335 [OM2K_DEI_TF_SYNC_SRC] = { TLV_TYPE_TV },
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]336 [OM2K_DEI_TTA] = { TLV_TYPE_TV },
Harald Weltef6d6b212011-03-05 20:13:52 +0100[diff] [blame]337 [OM2K_DEI_CAPA_SIG] = { TLV_TYPE_FIXED, 2 },
Harald Weltee6e83832011-03-05 17:52:09 +0100[diff] [blame]338 [OM2K_DEI_NEGOT_REC1] = { TLV_TYPE_TLV },
339 [OM2K_DEI_NEGOT_REC2] = { TLV_TYPE_TLV },
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]340 [OM2K_DEI_ENCR_ALG] = { TLV_TYPE_TV },
341 [OM2K_DEI_INTERF_REJ_COMB] = { TLV_TYPE_TV },
Harald Weltee6e83832011-03-05 17:52:09 +0100[diff] [blame]342 [OM2K_DEI_FS_OFFSET] = { TLV_TYPE_FIXED, 5 },
Harald Weltef6d6b212011-03-05 20:13:52 +0100[diff] [blame]343 [OM2K_DEI_EXT_COND_MAP_2_EXT] = { TLV_TYPE_FIXED, 4 },
Philipp8136e4b2016-10-19 10:14:35 +0200[diff] [blame]344 [OM2K_DEI_TSS_MO_STATE] = { TLV_TYPE_FIXED, 4 },
Harald Weltee6e83832011-03-05 17:52:09 +0100[diff] [blame]345 },
346};
347
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]348static const struct value_string om2k_msgcode_vals[] = {
349 { 0x0000, "Abort SP Command" },
350 { 0x0002, "Abort SP Complete" },
351 { 0x0004, "Alarm Report ACK" },
352 { 0x0005, "Alarm Report NACK" },
353 { 0x0006, "Alarm Report" },
354 { 0x0008, "Alarm Status Request" },
355 { 0x000a, "Alarm Status Request Accept" },
356 { 0x000b, "Alarm Status Request Reject" },
357 { 0x000c, "Alarm Status Result ACK" },
358 { 0x000d, "Alarm Status Result NACK" },
359 { 0x000e, "Alarm Status Result" },
360 { 0x0010, "Calendar Time Response" },
361 { 0x0011, "Calendar Time Reject" },
362 { 0x0012, "Calendar Time Request" },
363 { 0x0014, "CON Configuration Request" },
364 { 0x0016, "CON Configuration Request Accept" },
365 { 0x0017, "CON Configuration Request Reject" },
366 { 0x0018, "CON Configuration Result ACK" },
367 { 0x0019, "CON Configuration Result NACK" },
368 { 0x001a, "CON Configuration Result" },
369 { 0x001c, "Connect Command" },
370 { 0x001e, "Connect Complete" },
Harald Welte3ede7232011-03-05 17:58:13 +0100[diff] [blame]371 { 0x001f, "Connect Reject" },
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]372 { 0x0028, "Disable Request" },
373 { 0x002a, "Disable Request Accept" },
374 { 0x002b, "Disable Request Reject" },
375 { 0x002c, "Disable Result ACK" },
376 { 0x002d, "Disable Result NACK" },
377 { 0x002e, "Disable Result" },
378 { 0x0030, "Disconnect Command" },
379 { 0x0032, "Disconnect Complete" },
380 { 0x0033, "Disconnect Reject" },
381 { 0x0034, "Enable Request" },
382 { 0x0036, "Enable Request Accept" },
383 { 0x0037, "Enable Request Reject" },
384 { 0x0038, "Enable Result ACK" },
385 { 0x0039, "Enable Result NACK" },
386 { 0x003a, "Enable Result" },
387 { 0x003c, "Escape Downlink Normal" },
388 { 0x003d, "Escape Downlink NACK" },
389 { 0x003e, "Escape Uplink Normal" },
390 { 0x003f, "Escape Uplink NACK" },
391 { 0x0040, "Fault Report ACK" },
392 { 0x0041, "Fault Report NACK" },
393 { 0x0042, "Fault Report" },
394 { 0x0044, "File Package End Command" },
395 { 0x0046, "File Package End Result" },
396 { 0x0047, "File Package End Reject" },
397 { 0x0048, "File Relation Request" },
398 { 0x004a, "File Relation Response" },
399 { 0x004b, "File Relation Request Reject" },
400 { 0x004c, "File Segment Transfer" },
401 { 0x004e, "File Segment Transfer Complete" },
402 { 0x004f, "File Segment Transfer Reject" },
403 { 0x0050, "HW Information Request" },
404 { 0x0052, "HW Information Request Accept" },
405 { 0x0053, "HW Information Request Reject" },
406 { 0x0054, "HW Information Result ACK" },
407 { 0x0055, "HW Information Result NACK" },
408 { 0x0056, "HW Information Result" },
409 { 0x0060, "IS Configuration Request" },
410 { 0x0062, "IS Configuration Request Accept" },
411 { 0x0063, "IS Configuration Request Reject" },
412 { 0x0064, "IS Configuration Result ACK" },
413 { 0x0065, "IS Configuration Result NACK" },
414 { 0x0066, "IS Configuration Result" },
415 { 0x0068, "Load Data End" },
416 { 0x006a, "Load Data End Result" },
417 { 0x006b, "Load Data End Reject" },
418 { 0x006c, "Load Data Init" },
419 { 0x006e, "Load Data Init Accept" },
420 { 0x006f, "Load Data Init Reject" },
421 { 0x0070, "Loop Control Command" },
422 { 0x0072, "Loop Control Complete" },
423 { 0x0073, "Loop Control Reject" },
424 { 0x0074, "Operational Information" },
425 { 0x0076, "Operational Information Accept" },
426 { 0x0077, "Operational Information Reject" },
427 { 0x0078, "Reset Command" },
428 { 0x007a, "Reset Complete" },
429 { 0x007b, "Reset Reject" },
430 { 0x007c, "RX Configuration Request" },
431 { 0x007e, "RX Configuration Request Accept" },
432 { 0x007f, "RX Configuration Request Reject" },
433 { 0x0080, "RX Configuration Result ACK" },
434 { 0x0081, "RX Configuration Result NACK" },
435 { 0x0082, "RX Configuration Result" },
436 { 0x0084, "Start Request" },
437 { 0x0086, "Start Request Accept" },
438 { 0x0087, "Start Request Reject" },
439 { 0x0088, "Start Result ACK" },
440 { 0x0089, "Start Result NACK" },
441 { 0x008a, "Start Result" },
442 { 0x008c, "Status Request" },
443 { 0x008e, "Status Response" },
444 { 0x008f, "Status Reject" },
445 { 0x0094, "Test Request" },
446 { 0x0096, "Test Request Accept" },
447 { 0x0097, "Test Request Reject" },
448 { 0x0098, "Test Result ACK" },
449 { 0x0099, "Test Result NACK" },
450 { 0x009a, "Test Result" },
451 { 0x00a0, "TF Configuration Request" },
452 { 0x00a2, "TF Configuration Request Accept" },
453 { 0x00a3, "TF Configuration Request Reject" },
454 { 0x00a4, "TF Configuration Result ACK" },
455 { 0x00a5, "TF Configuration Result NACK" },
456 { 0x00a6, "TF Configuration Result" },
457 { 0x00a8, "TS Configuration Request" },
458 { 0x00aa, "TS Configuration Request Accept" },
459 { 0x00ab, "TS Configuration Request Reject" },
460 { 0x00ac, "TS Configuration Result ACK" },
461 { 0x00ad, "TS Configuration Result NACK" },
462 { 0x00ae, "TS Configuration Result" },
463 { 0x00b0, "TX Configuration Request" },
464 { 0x00b2, "TX Configuration Request Accept" },
465 { 0x00b3, "TX Configuration Request Reject" },
466 { 0x00b4, "TX Configuration Result ACK" },
467 { 0x00b5, "TX Configuration Result NACK" },
468 { 0x00b6, "TX Configuration Result" },
469 { 0x00bc, "DIP Alarm Report ACK" },
470 { 0x00bd, "DIP Alarm Report NACK" },
471 { 0x00be, "DIP Alarm Report" },
472 { 0x00c0, "DIP Alarm Status Request" },
473 { 0x00c2, "DIP Alarm Status Response" },
474 { 0x00c3, "DIP Alarm Status Reject" },
475 { 0x00c4, "DIP Quality Report I ACK" },
476 { 0x00c5, "DIP Quality Report I NACK" },
477 { 0x00c6, "DIP Quality Report I" },
478 { 0x00c8, "DIP Quality Report II ACK" },
479 { 0x00c9, "DIP Quality Report II NACK" },
480 { 0x00ca, "DIP Quality Report II" },
481 { 0x00dc, "DP Configuration Request" },
482 { 0x00de, "DP Configuration Request Accept" },
483 { 0x00df, "DP Configuration Request Reject" },
484 { 0x00e0, "DP Configuration Result ACK" },
485 { 0x00e1, "DP Configuration Result NACK" },
486 { 0x00e2, "DP Configuration Result" },
487 { 0x00e4, "Capabilities HW Info Report ACK" },
488 { 0x00e5, "Capabilities HW Info Report NACK" },
489 { 0x00e6, "Capabilities HW Info Report" },
490 { 0x00e8, "Capabilities Request" },
491 { 0x00ea, "Capabilities Request Accept" },
492 { 0x00eb, "Capabilities Request Reject" },
493 { 0x00ec, "Capabilities Result ACK" },
494 { 0x00ed, "Capabilities Result NACK" },
495 { 0x00ee, "Capabilities Result" },
496 { 0x00f0, "FM Configuration Request" },
497 { 0x00f2, "FM Configuration Request Accept" },
498 { 0x00f3, "FM Configuration Request Reject" },
499 { 0x00f4, "FM Configuration Result ACK" },
500 { 0x00f5, "FM Configuration Result NACK" },
501 { 0x00f6, "FM Configuration Result" },
502 { 0x00f8, "FM Report Request" },
503 { 0x00fa, "FM Report Response" },
504 { 0x00fb, "FM Report Reject" },
505 { 0x00fc, "FM Start Command" },
506 { 0x00fe, "FM Start Complete" },
507 { 0x00ff, "FM Start Reject" },
508 { 0x0100, "FM Stop Command" },
509 { 0x0102, "FM Stop Complete" },
510 { 0x0103, "FM Stop Reject" },
511 { 0x0104, "Negotiation Request ACK" },
512 { 0x0105, "Negotiation Request NACK" },
513 { 0x0106, "Negotiation Request" },
514 { 0x0108, "BTS Initiated Request ACK" },
515 { 0x0109, "BTS Initiated Request NACK" },
516 { 0x010a, "BTS Initiated Request" },
517 { 0x010c, "Radio Channels Release Command" },
518 { 0x010e, "Radio Channels Release Complete" },
519 { 0x010f, "Radio Channels Release Reject" },
520 { 0x0118, "Feature Control Command" },
521 { 0x011a, "Feature Control Complete" },
522 { 0x011b, "Feature Control Reject" },
523
524 { 0, NULL }
525};
526
527/* TS 12.21 Section 9.4: Attributes */
528static const struct value_string om2k_attr_vals[] = {
529 { 0x00, "Accordance indication" },
530 { 0x01, "Alarm Id" },
531 { 0x02, "Alarm Data" },
532 { 0x03, "Alarm Severity" },
533 { 0x04, "Alarm Status" },
534 { 0x05, "Alarm Status Type" },
535 { 0x06, "BCC" },
536 { 0x07, "BS_AG_BKS_RES" },
537 { 0x09, "BSIC" },
538 { 0x0a, "BA_PA_MFRMS" },
539 { 0x0b, "CBCH Indicator" },
540 { 0x0c, "CCCH Options" },
541 { 0x0d, "Calendar Time" },
542 { 0x0f, "Channel Combination" },
543 { 0x10, "CON Connection List" },
544 { 0x11, "Data End Indication" },
545 { 0x12, "DRX_DEV_MAX" },
546 { 0x13, "End List Number" },
547 { 0x14, "External Condition Map Class 1" },
548 { 0x15, "External Condition Map Class 2" },
549 { 0x16, "File Relation Indication" },
550 { 0x17, "File Revision" },
551 { 0x18, "File Segment Data" },
552 { 0x19, "File Segment Length" },
553 { 0x1a, "File Segment Sequence Number" },
554 { 0x1b, "File Size" },
555 { 0x1c, "Filling Marker" },
556 { 0x1d, "FN Offset" },
557 { 0x1e, "Frequency List" },
558 { 0x1f, "Frequency Specifier RX" },
559 { 0x20, "Frequency Specifier TX" },
560 { 0x21, "HSN" },
561 { 0x22, "ICM Indicator" },
562 { 0x23, "Internal Fault Map Class 1A" },
563 { 0x24, "Internal Fault Map Class 1B" },
564 { 0x25, "Internal Fault Map Class 2A" },
565 { 0x26, "Internal Fault Map Class 2A Extension" },
566 { 0x27, "IS Connection List" },
567 { 0x28, "List Number" },
568 { 0x29, "File Package State Indication" },
569 { 0x2a, "Local Access State" },
570 { 0x2b, "MAIO" },
571 { 0x2c, "MO State" },
572 { 0x2d, "Ny1" },
573 { 0x2e, "Operational Information" },
574 { 0x2f, "Power" },
575 { 0x30, "RU Position Data" },
576 { 0x31, "Protocol Error" },
577 { 0x32, "Reason Code" },
578 { 0x33, "Receiver Diversity" },
579 { 0x34, "Replacement Unit Map" },
580 { 0x35, "Result Code" },
581 { 0x36, "RU Revision Data" },
582 { 0x38, "T3105" },
583 { 0x39, "Test Loop Setting" },
584 { 0x3a, "TF Mode" },
585 { 0x3b, "TF Compensation Value" },
586 { 0x3c, "Time Slot Number" },
587 { 0x3d, "TSC" },
588 { 0x3e, "RU Logical Id" },
589 { 0x3f, "RU Serial Number Data" },
590 { 0x40, "BTS Version" },
591 { 0x41, "OML IWD Version" },
592 { 0x42, "RWL IWD Version" },
593 { 0x43, "OML Function Map 1" },
594 { 0x44, "OML Function Map 2" },
595 { 0x45, "RSL Function Map 1" },
596 { 0x46, "RSL Function Map 2" },
597 { 0x47, "Extended Range Indicator" },
598 { 0x48, "Request Indicators" },
599 { 0x49, "DIP Alarm Condition Map" },
600 { 0x4a, "ES Incoming" },
601 { 0x4b, "ES Outgoing" },
602 { 0x4e, "SES Incoming" },
603 { 0x4f, "SES Outgoing" },
604 { 0x50, "Replacement Unit Map Extension" },
605 { 0x52, "UAS Incoming" },
606 { 0x53, "UAS Outgoing" },
607 { 0x58, "DF Incoming" },
608 { 0x5a, "DF Outgoing" },
609 { 0x5c, "SF" },
610 { 0x60, "S Bits Setting" },
611 { 0x61, "CRC-4 Use Option" },
612 { 0x62, "T Parameter" },
613 { 0x63, "N Parameter" },
614 { 0x64, "N1 Parameter" },
615 { 0x65, "N3 Parameter" },
616 { 0x66, "N4 Parameter" },
617 { 0x67, "P Parameter" },
618 { 0x68, "Q Parameter" },
619 { 0x69, "BI_Q1" },
620 { 0x6a, "BI_Q2" },
621 { 0x74, "ICM Boundary Parameters" },
622 { 0x77, "AFT" },
623 { 0x78, "AFT RAI" },
624 { 0x79, "Link Supervision Control" },
625 { 0x7a, "Link Supervision Filtering Time" },
626 { 0x7b, "Call Supervision Time" },
627 { 0x7c, "Interval Length UAS Incoming" },
628 { 0x7d, "Interval Length UAS Outgoing" },
629 { 0x7e, "ICM Channel Rate" },
630 { 0x7f, "Attribute Identifier" },
631 { 0x80, "FM Frequency List" },
632 { 0x81, "FM Frequency Report" },
633 { 0x82, "FM Percentile" },
634 { 0x83, "FM Clear Indication" },
635 { 0x84, "HW Info Signature" },
636 { 0x85, "MO Record" },
637 { 0x86, "TF Synchronisation Source" },
638 { 0x87, "TTA" },
639 { 0x88, "End Segment Number" },
640 { 0x89, "Segment Number" },
641 { 0x8a, "Capabilities Signature" },
642 { 0x8c, "File Relation List" },
643 { 0x90, "Negotiation Record I" },
644 { 0x91, "Negotiation Record II" },
645 { 0x92, "Encryption Algorithm" },
646 { 0x94, "Interference Rejection Combining" },
647 { 0x95, "Dedication Information" },
648 { 0x97, "Feature Code" },
649 { 0x98, "FS Offset" },
650 { 0x99, "ESB Timeslot" },
651 { 0x9a, "Master TG Instance" },
652 { 0x9b, "Master TX Chain Delay" },
653 { 0x9c, "External Condition Class 2 Extension" },
654 { 0x9d, "TSs MO State" },
655 { 0, NULL }
656};
657
Harald Weltee1d5eca2011-02-12 14:42:59 +0100[diff] [blame]658const struct value_string om2k_mo_class_short_vals[] = {
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]659 { 0x01, "TRXC" },
660 { 0x03, "TS" },
661 { 0x04, "TF" },
662 { 0x05, "IS" },
663 { 0x06, "CON" },
664 { 0x07, "DP" },
665 { 0x0a, "CF" },
666 { 0x0b, "TX" },
667 { 0x0c, "RX" },
668 { 0, NULL }
669};
670
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]671const struct value_string om2k_result_strings[] = {
672 { 0x02, "Wrong state or out of sequence" },
673 { 0x03, "File error" },
674 { 0x04, "Fault, unspecified" },
675 { 0x05, "Tuning fault" },
676 { 0x06, "Protocol error" },
677 { 0x07, "MO not connected" },
678 { 0x08, "Parameter error" },
679 { 0x09, "Optional function not supported" },
680 { 0x0a, "Local access state LOCALLY DISCONNECTED" },
681 { 0, NULL }
682};
683
684const struct value_string om2k_accordance_strings[] = {
685 { 0x00, "Data according to request" },
686 { 0x01, "Data not according to request" },
687 { 0x02, "Inconsistent MO data" },
688 { 0x03, "Capability constraint violation" },
689 { 0, NULL }
690};
691
692const struct value_string om2k_mostate_vals[] = {
693 { 0x00, "RESET" },
694 { 0x01, "STARTED" },
695 { 0x02, "ENABLED" },
696 { 0x03, "DISABLED" },
697 { 0, NULL }
698};
699
700/* entire decoded OM2K message (header + parsed TLV) */
701struct om2k_decoded_msg {
702 struct abis_om2k_hdr o2h;
703 uint16_t msg_type;
704 struct tlv_parsed tp;
705};
706
707/* resolve the OM2000 Managed Object by BTS + MO Address */
708static struct om2k_mo *
709get_om2k_mo(struct gsm_bts *bts, const struct abis_om2k_mo *abis_mo)
710{
711 struct om2k_mo *mo = NULL;
712 struct gsm_bts_trx *trx;
713
714 switch (abis_mo->class) {
715 case OM2K_MO_CLS_CF:
716 mo = &bts->rbs2000.cf.om2k_mo;
717 break;
718 case OM2K_MO_CLS_CON:
719 mo = &bts->rbs2000.con.om2k_mo;
720 break;
721 case OM2K_MO_CLS_IS:
722 mo = &bts->rbs2000.is.om2k_mo;
723 break;
724 case OM2K_MO_CLS_TF:
725 mo = &bts->rbs2000.tf.om2k_mo;
726 break;
727
728 case OM2K_MO_CLS_TRXC:
729 trx = gsm_bts_trx_num(bts, abis_mo->inst);
730 if (!trx)
731 return NULL;
732 mo = &trx->rbs2000.trxc.om2k_mo;
733 break;
734 case OM2K_MO_CLS_TX:
735 trx = gsm_bts_trx_num(bts, abis_mo->inst);
736 if (!trx)
737 return NULL;
738 mo = &trx->rbs2000.tx.om2k_mo;
739 break;
740 case OM2K_MO_CLS_RX:
741 trx = gsm_bts_trx_num(bts, abis_mo->inst);
742 if (!trx)
743 return NULL;
744 mo = &trx->rbs2000.rx.om2k_mo;
745 break;
746 case OM2K_MO_CLS_TS:
747 trx = gsm_bts_trx_num(bts, abis_mo->assoc_so);
748 if (!trx)
749 return NULL;
750 if (abis_mo->inst >= ARRAY_SIZE(trx->ts))
751 return NULL;
752 mo = &trx->ts[abis_mo->inst].rbs2000.om2k_mo;
753 break;
754 default:
755 return NULL;
756 };
757
758 return mo;
759}
760
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]761static struct msgb *om2k_msgb_alloc(void)
762{
763 return msgb_alloc_headroom(OM_ALLOC_SIZE, OM_HEADROOM_SIZE,
764 "OM2000");
765}
766
Holger Hans Peter Freytherc42ad8b2011-04-18 17:04:00 +0200[diff] [blame]767static int abis_om2k_tlv_parse(struct tlv_parsed *tp, const uint8_t *buf, int len)
Harald Weltee6e83832011-03-05 17:52:09 +0100[diff] [blame]768{
769 return tlv_parse(tp, &om2k_att_tlvdef, buf, len, 0, 0);
770}
771
Harald Weltee898ecc2011-03-06 19:26:11 +0100[diff] [blame]772static int abis_om2k_msg_tlv_parse(struct tlv_parsed *tp, struct abis_om2k_hdr *oh)
773{
774 return abis_om2k_tlv_parse(tp, oh->data, oh->om.length - 6);
775}
776
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]777/* decode/parse the message */
778static int om2k_decode_msg(struct om2k_decoded_msg *odm, struct msgb *msg)
779{
780 struct abis_om2k_hdr *o2h = msgb_l2(msg);
781 odm->msg_type = ntohs(o2h->msg_type);
782 odm->o2h = *o2h;
783 return abis_om2k_msg_tlv_parse(&odm->tp, o2h);
784}
785
Harald Welted88a3872011-02-14 15:26:13 +0100[diff] [blame]786static char *om2k_mo_name(const struct abis_om2k_mo *mo)
787{
788 static char mo_buf[64];
789
790 memset(mo_buf, 0, sizeof(mo_buf));
791 snprintf(mo_buf, sizeof(mo_buf), "%s/%02x/%02x/%02x",
792 get_value_string(om2k_mo_class_short_vals, mo->class),
793 mo->bts, mo->assoc_so, mo->inst);
794 return mo_buf;
795}
796
Harald Welteaf9b8102011-03-06 21:20:38 +0100[diff] [blame]797/* resolve the gsm_nm_state data structure for a given MO */
798static struct gsm_nm_state *
799mo2nm_state(struct gsm_bts *bts, const struct abis_om2k_mo *mo)
800{
801 struct gsm_bts_trx *trx;
802 struct gsm_nm_state *nm_state = NULL;
803
804 switch (mo->class) {
805 case OM2K_MO_CLS_TRXC:
Harald Welte2d027752016-11-15 22:09:08 +0100[diff] [blame^]806 trx = gsm_bts_trx_num(bts, mo->inst);
Harald Welteaf9b8102011-03-06 21:20:38 +0100[diff] [blame]807 if (!trx)
808 return NULL;
Harald Welted64c0bc2011-05-30 12:07:53 +0200[diff] [blame]809 nm_state = &trx->mo.nm_state;
Harald Welteaf9b8102011-03-06 21:20:38 +0100[diff] [blame]810 break;
811 case OM2K_MO_CLS_TS:
812 trx = gsm_bts_trx_num(bts, mo->assoc_so);
813 if (!trx)
814 return NULL;
815 if (mo->inst >= ARRAY_SIZE(trx->ts))
816 return NULL;
Harald Welted64c0bc2011-05-30 12:07:53 +0200[diff] [blame]817 nm_state = &trx->ts[mo->inst].mo.nm_state;
Harald Welteaf9b8102011-03-06 21:20:38 +0100[diff] [blame]818 break;
819 case OM2K_MO_CLS_TF:
Harald Welted64c0bc2011-05-30 12:07:53 +0200[diff] [blame]820 nm_state = &bts->rbs2000.tf.mo.nm_state;
Harald Welteaf9b8102011-03-06 21:20:38 +0100[diff] [blame]821 break;
822 case OM2K_MO_CLS_IS:
Harald Welted64c0bc2011-05-30 12:07:53 +0200[diff] [blame]823 nm_state = &bts->rbs2000.is.mo.nm_state;
Harald Welteaf9b8102011-03-06 21:20:38 +0100[diff] [blame]824 break;
825 case OM2K_MO_CLS_CON:
Harald Welted64c0bc2011-05-30 12:07:53 +0200[diff] [blame]826 nm_state = &bts->rbs2000.con.mo.nm_state;
Harald Welteaf9b8102011-03-06 21:20:38 +0100[diff] [blame]827 break;
828 case OM2K_MO_CLS_DP:
Harald Welted64c0bc2011-05-30 12:07:53 +0200[diff] [blame]829 nm_state = &bts->rbs2000.con.mo.nm_state;
Harald Welteaf9b8102011-03-06 21:20:38 +0100[diff] [blame]830 break;
831 case OM2K_MO_CLS_CF:
Harald Welted64c0bc2011-05-30 12:07:53 +0200[diff] [blame]832 nm_state = &bts->mo.nm_state;
Harald Welteaf9b8102011-03-06 21:20:38 +0100[diff] [blame]833 break;
834 case OM2K_MO_CLS_TX:
Harald Welte2d027752016-11-15 22:09:08 +0100[diff] [blame^]835 trx = gsm_bts_trx_num(bts, mo->inst);
Harald Welteaf9b8102011-03-06 21:20:38 +0100[diff] [blame]836 if (!trx)
837 return NULL;
838 break;
839 case OM2K_MO_CLS_RX:
Harald Welte2d027752016-11-15 22:09:08 +0100[diff] [blame^]840 trx = gsm_bts_trx_num(bts, mo->inst);
Harald Welteaf9b8102011-03-06 21:20:38 +0100[diff] [blame]841 if (!trx)
842 return NULL;
843 break;
844 }
845
846 return nm_state;
847}
848
849static void *mo2obj(struct gsm_bts *bts, struct abis_om2k_mo *mo)
850{
851 struct gsm_bts_trx *trx;
852
853 switch (mo->class) {
854 case OM2K_MO_CLS_TX:
855 case OM2K_MO_CLS_RX:
856 case OM2K_MO_CLS_TRXC:
Harald Welte2d027752016-11-15 22:09:08 +0100[diff] [blame^]857 return gsm_bts_trx_num(bts, mo->inst);
Harald Welteaf9b8102011-03-06 21:20:38 +0100[diff] [blame]858 case OM2K_MO_CLS_TS:
859 trx = gsm_bts_trx_num(bts, mo->assoc_so);
860 if (!trx)
861 return NULL;
862 if (mo->inst >= ARRAY_SIZE(trx->ts))
863 return NULL;
864 return &trx->ts[mo->inst];
865 case OM2K_MO_CLS_TF:
866 case OM2K_MO_CLS_IS:
867 case OM2K_MO_CLS_CON:
868 case OM2K_MO_CLS_DP:
869 case OM2K_MO_CLS_CF:
870 return bts;
871 }
872
873 return NULL;
874}
875
876static void update_mo_state(struct gsm_bts *bts, struct abis_om2k_mo *mo,
877 uint8_t mo_state)
878{
879 struct gsm_nm_state *nm_state = mo2nm_state(bts, mo);
880 struct gsm_nm_state new_state;
881 struct nm_statechg_signal_data nsd;
882
883 if (!nm_state)
884 return;
885
886 new_state = *nm_state;
887 /* NOTICE: 12.21 Availability state values != OM2000 */
888 new_state.availability = mo_state;
889
890 memset(&nsd, 0, sizeof(nsd));
891
Harald Welte8b277ac2011-03-06 23:00:32 +0100[diff] [blame]892 nsd.bts = bts;
Harald Welteaf9b8102011-03-06 21:20:38 +0100[diff] [blame]893 nsd.obj = mo2obj(bts, mo);
894 nsd.old_state = nm_state;
895 nsd.new_state = &new_state;
896 nsd.om2k_mo = mo;
897
Pablo Neira Ayusobbc5b992011-05-06 12:12:31 +0200[diff] [blame]898 osmo_signal_dispatch(SS_NM, S_NM_STATECHG_ADM, &nsd);
Harald Welteaf9b8102011-03-06 21:20:38 +0100[diff] [blame]899
900 nm_state->availability = new_state.availability;
901}
902
903static void update_op_state(struct gsm_bts *bts, const struct abis_om2k_mo *mo,
904 uint8_t op_state)
905{
906 struct gsm_nm_state *nm_state = mo2nm_state(bts, mo);
907 struct gsm_nm_state new_state;
908
909 if (!nm_state)
910 return;
911
912 new_state = *nm_state;
913 switch (op_state) {
914 case 1:
915 new_state.operational = NM_OPSTATE_ENABLED;
916 break;
917 case 0:
918 new_state.operational = NM_OPSTATE_DISABLED;
919 break;
920 default:
921 new_state.operational = NM_OPSTATE_NULL;
922 break;
923 }
924
925 nm_state->operational = new_state.operational;
926}
927
Harald Weltebc867d92011-02-12 13:09:38 +0100[diff] [blame]928static int abis_om2k_sendmsg(struct gsm_bts *bts, struct msgb *msg)
929{
Harald Welted88a3872011-02-14 15:26:13 +0100[diff] [blame]930 struct abis_om2k_hdr *o2h;
Harald Welte15eae8d2011-09-26 23:43:23 +0200[diff] [blame]931 struct gsm_bts_trx *trx;
Harald Weltebc867d92011-02-12 13:09:38 +0100[diff] [blame]932
Harald Welted88a3872011-02-14 15:26:13 +0100[diff] [blame]933 msg->l2h = msg->data;
934 o2h = (struct abis_om2k_hdr *) msg->l2h;
935
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]936 /* Compute the length in the OML header */
937 o2h->om.length = 6 + msgb_l2len(msg)-sizeof(*o2h);
938
Harald Welted88a3872011-02-14 15:26:13 +0100[diff] [blame]939 switch (o2h->mo.class) {
940 case OM2K_MO_CLS_TRXC:
941 case OM2K_MO_CLS_TX:
942 case OM2K_MO_CLS_RX:
Harald Welted88a3872011-02-14 15:26:13 +0100[diff] [blame]943 /* Route through per-TRX OML Link to the appropriate TRX */
Harald Welte15eae8d2011-09-26 23:43:23 +0200[diff] [blame]944 trx = gsm_bts_trx_by_nr(bts, o2h->mo.inst);
945 if (!trx) {
Harald Welted88a3872011-02-14 15:26:13 +0100[diff] [blame]946 LOGP(DNM, LOGL_ERROR, "MO=%s Tx Dropping msg to "
947 "non-existing TRX\n", om2k_mo_name(&o2h->mo));
948 return -ENODEV;
949 }
Harald Welte0818f312012-09-07 19:09:46 +0200[diff] [blame]950 msg->dst = trx->oml_link;
Harald Welted88a3872011-02-14 15:26:13 +0100[diff] [blame]951 break;
Harald Welte8aeac192011-03-05 20:15:09 +0100[diff] [blame]952 case OM2K_MO_CLS_TS:
953 /* Route through per-TRX OML Link to the appropriate TRX */
Harald Welte15eae8d2011-09-26 23:43:23 +0200[diff] [blame]954 trx = gsm_bts_trx_by_nr(bts, o2h->mo.assoc_so);
955 if (!trx) {
Harald Welte8aeac192011-03-05 20:15:09 +0100[diff] [blame]956 LOGP(DNM, LOGL_ERROR, "MO=%s Tx Dropping msg to "
957 "non-existing TRX\n", om2k_mo_name(&o2h->mo));
958 return -ENODEV;
959 }
Harald Welte0818f312012-09-07 19:09:46 +0200[diff] [blame]960 msg->dst = trx->oml_link;
Harald Welte8aeac192011-03-05 20:15:09 +0100[diff] [blame]961 break;
Harald Welted88a3872011-02-14 15:26:13 +0100[diff] [blame]962 default:
963 /* Route through the IXU/DXU OML Link */
Harald Welte0818f312012-09-07 19:09:46 +0200[diff] [blame]964 msg->dst = bts->oml_link;
Harald Welted88a3872011-02-14 15:26:13 +0100[diff] [blame]965 break;
966 }
967
Harald Welte15eae8d2011-09-26 23:43:23 +0200[diff] [blame]968 return _abis_nm_sendmsg(msg);
Harald Weltebc867d92011-02-12 13:09:38 +0100[diff] [blame]969}
970
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]971static void fill_om2k_hdr(struct abis_om2k_hdr *o2h, const struct abis_om2k_mo *mo,
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]972 uint16_t msg_type)
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]973{
974 o2h->om.mdisc = ABIS_OM_MDISC_FOM;
975 o2h->om.placement = ABIS_OM_PLACEMENT_ONLY;
976 o2h->om.sequence = 0;
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]977 /* We fill o2h->om.length later during om2k_sendmsg() */
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]978 o2h->msg_type = htons(msg_type);
979 memcpy(&o2h->mo, mo, sizeof(o2h->mo));
980}
981
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]982static int abis_om2k_cal_time_resp(struct gsm_bts *bts)
983{
984 struct msgb *msg = om2k_msgb_alloc();
985 struct abis_om2k_hdr *o2k;
986 time_t tm_t;
987 struct tm *tm;
988
989 o2k = (struct abis_om2k_hdr *) msgb_put(msg, sizeof(*o2k));
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]990 fill_om2k_hdr(o2k, &bts->rbs2000.cf.om2k_mo.addr,
991 OM2K_MSGT_CAL_TIME_RESP);
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]992
993 tm_t = time(NULL);
994 tm = localtime(&tm_t);
995
996 msgb_put_u8(msg, OM2K_DEI_CAL_TIME);
997 msgb_put_u8(msg, tm->tm_year % 100);
998 msgb_put_u8(msg, tm->tm_mon + 1);
999 msgb_put_u8(msg, tm->tm_mday);
1000 msgb_put_u8(msg, tm->tm_hour);
1001 msgb_put_u8(msg, tm->tm_min);
1002 msgb_put_u8(msg, tm->tm_sec);
1003
Harald Weltebc867d92011-02-12 13:09:38 +0100[diff] [blame]1004 return abis_om2k_sendmsg(bts, msg);
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]1005}
1006
Harald Welte6fec79d2011-02-12 14:57:17 +0100[diff] [blame]1007static int abis_om2k_tx_simple(struct gsm_bts *bts, const struct abis_om2k_mo *mo,
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]1008 uint8_t msg_type)
1009{
1010 struct msgb *msg = om2k_msgb_alloc();
1011 struct abis_om2k_hdr *o2k;
1012
1013 o2k = (struct abis_om2k_hdr *) msgb_put(msg, sizeof(*o2k));
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]1014 fill_om2k_hdr(o2k, mo, msg_type);
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]1015
Harald Welte73541072011-02-12 13:44:14 +0100[diff] [blame]1016 DEBUGP(DNM, "Tx MO=%s %s\n", om2k_mo_name(mo),
1017 get_value_string(om2k_msgcode_vals, msg_type));
1018
Harald Weltebc867d92011-02-12 13:09:38 +0100[diff] [blame]1019 return abis_om2k_sendmsg(bts, msg);
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]1020}
1021
Harald Welte6fec79d2011-02-12 14:57:17 +0100[diff] [blame]1022int abis_om2k_tx_reset_cmd(struct gsm_bts *bts, const struct abis_om2k_mo *mo)
Harald Welte73541072011-02-12 13:44:14 +0100[diff] [blame]1023{
1024 return abis_om2k_tx_simple(bts, mo, OM2K_MSGT_RESET_CMD);
1025}
1026
Harald Welte6fec79d2011-02-12 14:57:17 +0100[diff] [blame]1027int abis_om2k_tx_start_req(struct gsm_bts *bts, const struct abis_om2k_mo *mo)
Harald Welte73541072011-02-12 13:44:14 +0100[diff] [blame]1028{
1029 return abis_om2k_tx_simple(bts, mo, OM2K_MSGT_START_REQ);
1030}
1031
Harald Welte6fec79d2011-02-12 14:57:17 +0100[diff] [blame]1032int abis_om2k_tx_status_req(struct gsm_bts *bts, const struct abis_om2k_mo *mo)
Harald Weltee1d5eca2011-02-12 14:42:59 +0100[diff] [blame]1033{
1034 return abis_om2k_tx_simple(bts, mo, OM2K_MSGT_STATUS_REQ);
1035}
1036
Harald Welte6fec79d2011-02-12 14:57:17 +0100[diff] [blame]1037int abis_om2k_tx_connect_cmd(struct gsm_bts *bts, const struct abis_om2k_mo *mo)
1038{
1039 return abis_om2k_tx_simple(bts, mo, OM2K_MSGT_CONNECT_CMD);
1040}
1041
1042int abis_om2k_tx_disconnect_cmd(struct gsm_bts *bts, const struct abis_om2k_mo *mo)
1043{
1044 return abis_om2k_tx_simple(bts, mo, OM2K_MSGT_DISCONNECT_CMD);
1045}
1046
Harald Welte8024d8f2011-02-12 15:07:30 +0100[diff] [blame]1047int abis_om2k_tx_test_req(struct gsm_bts *bts, const struct abis_om2k_mo *mo)
1048{
1049 return abis_om2k_tx_simple(bts, mo, OM2K_MSGT_TEST_REQ);
1050}
1051
Harald Welte0741ffe2011-02-12 18:48:53 +0100[diff] [blame]1052int abis_om2k_tx_enable_req(struct gsm_bts *bts, const struct abis_om2k_mo *mo)
1053{
1054 return abis_om2k_tx_simple(bts, mo, OM2K_MSGT_ENABLE_REQ);
1055}
1056
1057int abis_om2k_tx_disable_req(struct gsm_bts *bts, const struct abis_om2k_mo *mo)
1058{
1059 return abis_om2k_tx_simple(bts, mo, OM2K_MSGT_DISABLE_REQ);
1060}
1061
Harald Welte6fec79d2011-02-12 14:57:17 +0100[diff] [blame]1062int abis_om2k_tx_op_info(struct gsm_bts *bts, const struct abis_om2k_mo *mo,
1063 uint8_t operational)
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]1064{
1065 struct msgb *msg = om2k_msgb_alloc();
1066 struct abis_om2k_hdr *o2k;
1067
1068 o2k = (struct abis_om2k_hdr *) msgb_put(msg, sizeof(*o2k));
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]1069 fill_om2k_hdr(o2k, mo, OM2K_MSGT_OP_INFO);
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]1070
1071 msgb_tv_put(msg, OM2K_DEI_OP_INFO, operational);
1072
Harald Welte73541072011-02-12 13:44:14 +0100[diff] [blame]1073 DEBUGP(DNM, "Tx MO=%s %s\n", om2k_mo_name(mo),
1074 get_value_string(om2k_msgcode_vals, OM2K_MSGT_OP_INFO));
1075
Harald Welteaf9b8102011-03-06 21:20:38 +0100[diff] [blame]1076 /* we update the state here... and send the signal at ACK */
1077 update_op_state(bts, mo, operational);
1078
Harald Weltebc867d92011-02-12 13:09:38 +0100[diff] [blame]1079 return abis_om2k_sendmsg(bts, msg);
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]1080}
1081
root45799782016-10-15 21:24:57 +0200[diff] [blame]1082int abis_om2k_tx_cap_req(struct gsm_bts *bts, const struct abis_om2k_mo *mo)
1083{
1084 return abis_om2k_tx_simple(bts, mo, OM2K_MSGT_CAPA_REQ);
1085}
1086
Harald Welted529db62011-03-06 21:49:21 +0100[diff] [blame]1087static void om2k_fill_is_conn_grp(struct om2k_is_conn_grp *grp, uint16_t icp1,
1088 uint16_t icp2, uint8_t cont_idx)
1089{
1090 grp->icp1 = htons(icp1);
1091 grp->icp2 = htons(icp2);
1092 grp->cont_idx = cont_idx;
1093}
1094
1095int abis_om2k_tx_is_conf_req(struct gsm_bts *bts)
Harald Welte8bcb1a02011-02-12 20:23:40 +0100[diff] [blame]1096{
1097 struct msgb *msg = om2k_msgb_alloc();
1098 struct abis_om2k_hdr *o2k;
Harald Welted529db62011-03-06 21:49:21 +0100[diff] [blame]1099 struct is_conn_group *grp;
1100 unsigned int num_grps = 0, i = 0;
1101 struct om2k_is_conn_grp *cg;
1102
1103 /* count number of groups in linked list */
1104 llist_for_each_entry(grp, &bts->rbs2000.is.conn_groups, list)
1105 num_grps++;
1106
1107 if (!num_grps)
1108 return -EINVAL;
1109
1110 /* allocate buffer for oml group array */
1111 cg = talloc_zero_array(bts, struct om2k_is_conn_grp, num_grps);
1112
1113 /* fill array with data from linked list */
1114 llist_for_each_entry(grp, &bts->rbs2000.is.conn_groups, list)
1115 om2k_fill_is_conn_grp(&cg[i++], grp->icp1, grp->icp2, grp->ci);
Harald Welte8bcb1a02011-02-12 20:23:40 +0100[diff] [blame]1116
1117 o2k = (struct abis_om2k_hdr *) msgb_put(msg, sizeof(*o2k));
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]1118 fill_om2k_hdr(o2k, &bts->rbs2000.is.om2k_mo.addr,
1119 OM2K_MSGT_IS_CONF_REQ);
Harald Welte8bcb1a02011-02-12 20:23:40 +0100[diff] [blame]1120
1121 msgb_tv_put(msg, OM2K_DEI_LIST_NR, 1);
1122 msgb_tv_put(msg, OM2K_DEI_END_LIST_NR, 1);
1123
1124 msgb_tlv_put(msg, OM2K_DEI_IS_CONN_LIST,
Harald Welted529db62011-03-06 21:49:21 +0100[diff] [blame]1125 num_grps * sizeof(*cg), (uint8_t *)cg);
1126
1127 talloc_free(cg);
Harald Welte8bcb1a02011-02-12 20:23:40 +0100[diff] [blame]1128
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]1129 DEBUGP(DNM, "Tx MO=%s %s\n",
1130 om2k_mo_name(&bts->rbs2000.is.om2k_mo.addr),
Harald Welte79c34ff2012-09-07 20:15:50 +0200[diff] [blame]1131 get_value_string(om2k_msgcode_vals, OM2K_MSGT_IS_CONF_REQ));
1132
Harald Welte8bcb1a02011-02-12 20:23:40 +0100[diff] [blame]1133 return abis_om2k_sendmsg(bts, msg);
1134}
1135
Harald Welteeae68292016-11-11 19:41:59 +0100[diff] [blame]1136int abis_om2k_tx_con_conf_req(struct gsm_bts *bts)
Harald Weltefdb71942011-02-14 15:31:43 +0100[diff] [blame]1137{
1138 struct msgb *msg = om2k_msgb_alloc();
1139 struct abis_om2k_hdr *o2k;
Harald Welteeae68292016-11-11 19:41:59 +0100[diff] [blame]1140 struct con_group *grp;
1141 unsigned int num_grps = 0;
Harald Weltefdb71942011-02-14 15:31:43 +0100[diff] [blame]1142
Harald Welteeae68292016-11-11 19:41:59 +0100[diff] [blame]1143 /* count number of groups in linked list */
1144 llist_for_each_entry(grp, &bts->rbs2000.con.conn_groups, list)
1145 num_grps++;
1146
1147 if (!num_grps)
1148 return -EINVAL;
1149
1150 /* first build the value part of the OM2K_DEI_CON_CONN_LIST DEI */
1151 msgb_put_u8(msg, num_grps);
1152 llist_for_each_entry(grp, &bts->rbs2000.con.conn_groups, list) {
1153 struct con_path *cp;
1154 unsigned int num_paths = 0;
1155 llist_for_each_entry(cp, &grp->paths, list)
1156 num_paths++;
1157 msgb_put_u8(msg, num_paths);
1158 llist_for_each_entry(cp, &grp->paths, list) {
1159 struct om2k_con_path *om2k_cp;
1160 om2k_cp = (struct om2k_con_path *) msgb_put(msg, sizeof(*om2k_cp));
1161 om2k_cp->ccp = htons(cp->ccp);
1162 om2k_cp->ci = cp->ci;
1163 om2k_cp->tag = cp->tag;
1164 om2k_cp->tei = cp->tei;
1165 }
1166 }
1167 msgb_push_u8(msg, msgb_length(msg));
1168 msgb_push_u8(msg, OM2K_DEI_CON_CONN_LIST);
1169
1170 /* pre-pend the list number DEIs */
1171 msgb_tv_push(msg, OM2K_DEI_END_LIST_NR, 1);
1172 msgb_tv_push(msg, OM2K_DEI_LIST_NR, 1);
1173
1174 /* pre-pend the OM2K header */
1175 o2k = (struct abis_om2k_hdr *) msgb_push(msg, sizeof(*o2k));
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]1176 fill_om2k_hdr(o2k, &bts->rbs2000.con.om2k_mo.addr,
1177 OM2K_MSGT_CON_CONF_REQ);
Harald Weltefdb71942011-02-14 15:31:43 +0100[diff] [blame]1178
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]1179 DEBUGP(DNM, "Tx MO=%s %s\n",
1180 om2k_mo_name(&bts->rbs2000.con.om2k_mo.addr),
Harald Welte79c34ff2012-09-07 20:15:50 +0200[diff] [blame]1181 get_value_string(om2k_msgcode_vals, OM2K_MSGT_CON_CONF_REQ));
1182
Harald Weltefdb71942011-02-14 15:31:43 +0100[diff] [blame]1183 return abis_om2k_sendmsg(bts, msg);
1184}
1185
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]1186static void om2k_trx_to_mo(struct abis_om2k_mo *mo,
1187 const struct gsm_bts_trx *trx,
1188 enum abis_om2k_mo_cls cls)
1189{
1190 mo->class = cls;
1191 mo->bts = 0;
1192 mo->inst = trx->nr;
Harald Welte53492c82011-03-05 16:21:01 +0100[diff] [blame]1193 mo->assoc_so = 255;
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]1194}
1195
1196static void om2k_ts_to_mo(struct abis_om2k_mo *mo,
1197 const struct gsm_bts_trx_ts *ts)
1198{
1199 mo->class = OM2K_MO_CLS_TS;
1200 mo->bts = 0;
1201 mo->inst = ts->nr;
1202 mo->assoc_so = ts->trx->nr;
1203}
1204
1205/* Configure a Receiver MO */
1206int abis_om2k_tx_rx_conf_req(struct gsm_bts_trx *trx)
1207{
1208 struct msgb *msg = om2k_msgb_alloc();
1209 struct abis_om2k_hdr *o2k;
1210 struct abis_om2k_mo mo;
1211
1212 om2k_trx_to_mo(&mo, trx, OM2K_MO_CLS_RX);
1213
1214 o2k = (struct abis_om2k_hdr *) msgb_put(msg, sizeof(*o2k));
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]1215 fill_om2k_hdr(o2k, &mo, OM2K_MSGT_RX_CONF_REQ);
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]1216
1217 msgb_tv16_put(msg, OM2K_DEI_FREQ_SPEC_RX, trx->arfcn);
Harald Welte1edc2b42011-03-06 19:01:54 +0100[diff] [blame]1218 msgb_tv_put(msg, OM2K_DEI_RX_DIVERSITY, 0x02); /* A */
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]1219
1220 return abis_om2k_sendmsg(trx->bts, msg);
1221}
1222
1223/* Configure a Transmitter MO */
1224int abis_om2k_tx_tx_conf_req(struct gsm_bts_trx *trx)
1225{
1226 struct msgb *msg = om2k_msgb_alloc();
1227 struct abis_om2k_hdr *o2k;
1228 struct abis_om2k_mo mo;
1229
1230 om2k_trx_to_mo(&mo, trx, OM2K_MO_CLS_TX);
1231
1232 o2k = (struct abis_om2k_hdr *) msgb_put(msg, sizeof(*o2k));
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]1233 fill_om2k_hdr(o2k, &mo, OM2K_MSGT_TX_CONF_REQ);
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]1234
1235 msgb_tv16_put(msg, OM2K_DEI_FREQ_SPEC_TX, trx->arfcn);
1236 msgb_tv_put(msg, OM2K_DEI_POWER, trx->nominal_power-trx->max_power_red);
1237 msgb_tv_put(msg, OM2K_DEI_FILLING_MARKER, 0); /* Filling enabled */
1238 msgb_tv_put(msg, OM2K_DEI_BCC, trx->bts->bsic & 0x7);
1239 /* Dedication Information is optional */
1240
1241 return abis_om2k_sendmsg(trx->bts, msg);
1242}
1243
Harald Weltef9cf9612011-03-05 14:36:47 +0100[diff] [blame]1244enum abis_om2k_tf_mode {
1245 OM2K_TF_MODE_MASTER = 0x00,
1246 OM2K_TF_MODE_STANDALONE = 0x01,
1247 OM2K_TF_MODE_SLAVE = 0x02,
1248 OM2K_TF_MODE_UNDEFINED = 0xff,
1249};
1250
1251static const uint8_t fs_offset_undef[5] = { 0xff, 0xff, 0xff, 0xff, 0xff };
1252
1253int abis_om2k_tx_tf_conf_req(struct gsm_bts *bts)
1254{
1255 struct msgb *msg = om2k_msgb_alloc();
1256 struct abis_om2k_hdr *o2k;
1257
1258 o2k = (struct abis_om2k_hdr *) msgb_put(msg, sizeof(*o2k));
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]1259 fill_om2k_hdr(o2k, &bts->rbs2000.tf.om2k_mo.addr,
1260 OM2K_MSGT_TF_CONF_REQ);
Harald Weltef9cf9612011-03-05 14:36:47 +0100[diff] [blame]1261
1262 msgb_tv_put(msg, OM2K_DEI_TF_MODE, OM2K_TF_MODE_STANDALONE);
Harald Welteba9adbb2011-03-06 19:01:16 +0100[diff] [blame]1263 msgb_tv_put(msg, OM2K_DEI_TF_SYNC_SRC, 0x00);
Harald Weltef9cf9612011-03-05 14:36:47 +0100[diff] [blame]1264 msgb_tv_fixed_put(msg, OM2K_DEI_FS_OFFSET,
1265 sizeof(fs_offset_undef), fs_offset_undef);
1266
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]1267 DEBUGP(DNM, "Tx MO=%s %s\n",
1268 om2k_mo_name(&bts->rbs2000.tf.om2k_mo.addr),
Harald Welte79c34ff2012-09-07 20:15:50 +0200[diff] [blame]1269 get_value_string(om2k_msgcode_vals, OM2K_MSGT_TF_CONF_REQ));
1270
Harald Weltef9cf9612011-03-05 14:36:47 +0100[diff] [blame]1271 return abis_om2k_sendmsg(bts, msg);
1272}
1273
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]1274static uint8_t pchan2comb(enum gsm_phys_chan_config pchan)
1275{
1276 switch (pchan) {
1277 case GSM_PCHAN_CCCH:
1278 return 4;
1279 case GSM_PCHAN_CCCH_SDCCH4:
1280 return 5;
1281 case GSM_PCHAN_SDCCH8_SACCH8C:
1282 return 3;
1283 case GSM_PCHAN_TCH_F:
1284 case GSM_PCHAN_TCH_H:
1285 case GSM_PCHAN_PDCH:
Harald Welte80ccb952016-11-15 23:23:42 +0100[diff] [blame]1286 case GSM_PCHAN_TCH_F_PDCH:
1287 case GSM_PCHAN_TCH_F_TCH_H_PDCH:
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]1288 return 8;
1289 default:
1290 return 0;
1291 }
1292}
1293
Neels Hofmeyr23c3aa32016-09-25 15:15:59 +0200[diff] [blame]1294static uint8_t ts2comb(struct gsm_bts_trx_ts *ts)
1295{
1296 switch (ts->pchan) {
1297 case GSM_PCHAN_TCH_F_PDCH:
Neels Hofmeyr87ef68e2016-11-10 02:18:00 +0100[diff] [blame]1298 LOGP(DNM, LOGL_ERROR, "%s pchan %s not intended for use"
1299 " with OM2000, use %s instead\n",
1300 gsm_ts_and_pchan_name(ts),
1301 gsm_pchan_name(GSM_PCHAN_TCH_F_PDCH),
1302 gsm_pchan_name(GSM_PCHAN_TCH_F_TCH_H_PDCH));
1303 /* If we allowed initialization of TCH/F_PDCH, it would fail
1304 * when we try to send the ip.access specific RSL PDCH Act
1305 * message for it. Rather fail completely right now: */
1306 return 0;
Neels Hofmeyr23c3aa32016-09-25 15:15:59 +0200[diff] [blame]1307 case GSM_PCHAN_TCH_F_TCH_H_PDCH:
Neels Hofmeyrf926f452016-10-31 18:16:34 +0100[diff] [blame]1308 return pchan2comb(GSM_PCHAN_TCH_F);
Neels Hofmeyr23c3aa32016-09-25 15:15:59 +0200[diff] [blame]1309 default:
1310 return pchan2comb(ts->pchan);
1311 }
1312}
1313
Harald Welte5748c202011-03-05 17:30:07 +0100[diff] [blame]1314static int put_freq_list(uint8_t *buf, uint16_t arfcn)
1315{
1316 buf[0] = 0x00; /* TX/RX address */
1317 buf[1] = (arfcn >> 8);
1318 buf[2] = (arfcn & 0xff);
1319
1320 return 3;
1321}
1322
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]1323/* Compute a frequency list in OM2000 fomrmat */
1324static int om2k_gen_freq_list(uint8_t *list, struct gsm_bts_trx_ts *ts)
1325{
1326 uint8_t *cur = list;
Harald Weltee6e83832011-03-05 17:52:09 +0100[diff] [blame]1327 int len;
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]1328
1329 if (ts->hopping.enabled) {
1330 unsigned int i;
1331 for (i = 0; i < ts->hopping.arfcns.data_len*8; i++) {
Harald Welte5748c202011-03-05 17:30:07 +0100[diff] [blame]1332 if (bitvec_get_bit_pos(&ts->hopping.arfcns, i))
1333 cur += put_freq_list(cur, i);
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]1334 }
Harald Welte5748c202011-03-05 17:30:07 +0100[diff] [blame]1335 } else
1336 cur += put_freq_list(cur, ts->trx->arfcn);
1337
Harald Weltee6e83832011-03-05 17:52:09 +0100[diff] [blame]1338 len = cur - list;
1339
1340 return len;
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]1341}
1342
Harald Welte75755c52011-03-05 20:38:35 +0100[diff] [blame]1343const uint8_t icm_bound_params[] = { 0x02, 0x06, 0x0c, 0x16, 0x06 };
1344
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]1345int abis_om2k_tx_ts_conf_req(struct gsm_bts_trx_ts *ts)
1346{
1347 struct msgb *msg = om2k_msgb_alloc();
1348 struct abis_om2k_hdr *o2k;
1349 struct abis_om2k_mo mo;
1350 uint8_t freq_list[64*3]; /* BA max size: 64 ARFCN */
1351 int freq_list_len;
1352
1353 om2k_ts_to_mo(&mo, ts);
1354
Harald Welte5748c202011-03-05 17:30:07 +0100[diff] [blame]1355 memset(freq_list, 0, sizeof(freq_list));
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]1356 freq_list_len = om2k_gen_freq_list(freq_list, ts);
1357 if (freq_list_len < 0)
1358 return freq_list_len;
1359
1360 o2k = (struct abis_om2k_hdr *) msgb_put(msg, sizeof(*o2k));
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]1361 fill_om2k_hdr(o2k, &mo, OM2K_MSGT_TS_CONF_REQ);
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]1362
Neels Hofmeyr23c3aa32016-09-25 15:15:59 +0200[diff] [blame]1363 msgb_tv_put(msg, OM2K_DEI_COMBINATION, ts2comb(ts));
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]1364 msgb_tv_put(msg, OM2K_DEI_TS_NR, ts->nr);
1365 msgb_tlv_put(msg, OM2K_DEI_FREQ_LIST, freq_list_len, freq_list);
1366 msgb_tv_put(msg, OM2K_DEI_HSN, ts->hopping.hsn);
1367 msgb_tv_put(msg, OM2K_DEI_MAIO, ts->hopping.maio);
1368 msgb_tv_put(msg, OM2K_DEI_BSIC, ts->trx->bts->bsic);
Harald Welte1edc2b42011-03-06 19:01:54 +0100[diff] [blame]1369 msgb_tv_put(msg, OM2K_DEI_RX_DIVERSITY, 0x02); /* A */
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]1370 msgb_tv16_put(msg, OM2K_DEI_FN_OFFSET, 0);
1371 msgb_tv_put(msg, OM2K_DEI_EXT_RANGE, 0); /* Off */
1372 /* Optional: Interference Rejection Combining */
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]1373 msgb_tv_put(msg, OM2K_DEI_INTERF_REJ_COMB, 0x00);
1374 switch (ts->pchan) {
1375 case GSM_PCHAN_CCCH:
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]1376 msgb_tv_put(msg, OM2K_DEI_BA_PA_MFRMS, 0x06);
1377 msgb_tv_put(msg, OM2K_DEI_BS_AG_BKS_RES, 0x01);
1378 msgb_tv_put(msg, OM2K_DEI_DRX_DEV_MAX, 0x05);
1379 /* Repeat Paging/IMM.ASS: True, Allow Paging Type 3: Yes, Page for 5 seconds (default) */
1380 msgb_tv_put(msg, OM2K_DEI_CCCH_OPTIONS, 0x01);
1381 break;
Harald Welte75755c52011-03-05 20:38:35 +0100[diff] [blame]1382 case GSM_PCHAN_CCCH_SDCCH4:
Harald Welte67161f22012-06-03 13:01:47 +0200[diff] [blame]1383 msgb_tv_put(msg, OM2K_DEI_T3105, ts->trx->bts->network->T3105 / 10);
Harald Welte75755c52011-03-05 20:38:35 +0100[diff] [blame]1384 msgb_tv_put(msg, OM2K_DEI_NY1, 35);
1385 msgb_tv_put(msg, OM2K_DEI_BA_PA_MFRMS, 0x06);
1386 msgb_tv_put(msg, OM2K_DEI_CBCH_INDICATOR, 0);
Harald Welte94bc1e02014-01-19 17:19:10 +0100[diff] [blame]1387 msgb_tv_put(msg, OM2K_DEI_TSC, gsm_ts_tsc(ts));
Harald Welte75755c52011-03-05 20:38:35 +0100[diff] [blame]1388 msgb_tv_put(msg, OM2K_DEI_BS_AG_BKS_RES, 0x01);
1389 msgb_tv_put(msg, OM2K_DEI_ICM_INDICATOR, 0);
1390 msgb_tv_put(msg, OM2K_DEI_DRX_DEV_MAX, 0x05);
1391 /* Repeat Paging/IMM.ASS: True, Allow Paging Type 3: Yes, Page for 5 seconds (default) */
1392 msgb_tv_put(msg, OM2K_DEI_CCCH_OPTIONS, 0x01);
1393 msgb_tv_fixed_put(msg, OM2K_DEI_ICM_BOUND_PARAMS,
1394 sizeof(icm_bound_params), icm_bound_params);
1395 break;
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]1396 case GSM_PCHAN_SDCCH8_SACCH8C:
Harald Welte67161f22012-06-03 13:01:47 +0200[diff] [blame]1397 msgb_tv_put(msg, OM2K_DEI_T3105, ts->trx->bts->network->T3105 / 10);
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]1398 msgb_tv_put(msg, OM2K_DEI_NY1, 35);
1399 msgb_tv_put(msg, OM2K_DEI_CBCH_INDICATOR, 0);
Harald Welte94bc1e02014-01-19 17:19:10 +0100[diff] [blame]1400 msgb_tv_put(msg, OM2K_DEI_TSC, gsm_ts_tsc(ts));
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]1401 /* Disable RF RESOURCE INDICATION on idle channels */
1402 msgb_tv_put(msg, OM2K_DEI_ICM_INDICATOR, 0);
Harald Welte75755c52011-03-05 20:38:35 +0100[diff] [blame]1403 msgb_tv_fixed_put(msg, OM2K_DEI_ICM_BOUND_PARAMS,
1404 sizeof(icm_bound_params), icm_bound_params);
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]1405 break;
1406 default:
Harald Welte67161f22012-06-03 13:01:47 +0200[diff] [blame]1407 msgb_tv_put(msg, OM2K_DEI_T3105, ts->trx->bts->network->T3105 / 10);
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]1408 msgb_tv_put(msg, OM2K_DEI_NY1, 35);
Harald Welte94bc1e02014-01-19 17:19:10 +0100[diff] [blame]1409 msgb_tv_put(msg, OM2K_DEI_TSC, gsm_ts_tsc(ts));
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]1410 /* Disable RF RESOURCE INDICATION on idle channels */
1411 msgb_tv_put(msg, OM2K_DEI_ICM_INDICATOR, 0);
Harald Welte75755c52011-03-05 20:38:35 +0100[diff] [blame]1412 msgb_tv_fixed_put(msg, OM2K_DEI_ICM_BOUND_PARAMS,
1413 sizeof(icm_bound_params), icm_bound_params);
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]1414 msgb_tv_put(msg, OM2K_DEI_TTA, 10); /* Timer for Time Alignment */
Harald Welte75755c52011-03-05 20:38:35 +0100[diff] [blame]1415 if (ts->pchan == GSM_PCHAN_TCH_H)
1416 msgb_tv_put(msg, OM2K_DEI_ICM_CHAN_RATE, 1); /* TCH/H */
1417 else
1418 msgb_tv_put(msg, OM2K_DEI_ICM_CHAN_RATE, 0); /* TCH/F */
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]1419 msgb_tv_put(msg, OM2K_DEI_LSC, 1); /* enabled */
Harald Welte1edc2b42011-03-06 19:01:54 +0100[diff] [blame]1420 msgb_tv_put(msg, OM2K_DEI_LSC_FILT_TIME, 10); /* units of 100ms */
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]1421 msgb_tv_put(msg, OM2K_DEI_CALL_SUPV_TIME, 8);
1422 msgb_tv_put(msg, OM2K_DEI_ENCR_ALG, 0x00);
Harald Welte96638d12016-11-15 23:23:56 +0100[diff] [blame]1423 /* Not sure what those below mean */
1424 msgb_tv_put(msg, 0x9e, 0x00);
1425 msgb_tv_put(msg, 0x9f, 0x37);
1426 msgb_tv_put(msg, 0xa0, 0x01);
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]1427 break;
1428 }
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]1429
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]1430 DEBUGP(DNM, "Tx MO=%s %s\n",
1431 om2k_mo_name(&mo),
1432 get_value_string(om2k_msgcode_vals, OM2K_MSGT_TS_CONF_REQ));
1433
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]1434 return abis_om2k_sendmsg(ts->trx->bts, msg);
1435}
Harald Weltefdb71942011-02-14 15:31:43 +0100[diff] [blame]1436
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]1437
1438/***********************************************************************
1439 * OM2000 Managed Object (MO) FSM
1440 ***********************************************************************/
1441
1442#define S(x) (1 << (x))
1443
1444enum om2k_event_name {
1445 OM2K_MO_EVT_START,
1446 OM2K_MO_EVT_RX_CONN_COMPL,
1447 OM2K_MO_EVT_RX_RESET_COMPL,
1448 OM2K_MO_EVT_RX_START_REQ_ACCEPT,
1449 OM2K_MO_EVT_RX_START_RES,
1450 OM2K_MO_EVT_RX_CFG_REQ_ACCEPT,
1451 OM2K_MO_EVT_RX_CFG_RES,
1452 OM2K_MO_EVT_RX_ENA_REQ_ACCEPT,
1453 OM2K_MO_EVT_RX_ENA_RES,
1454 OM2K_MO_EVT_RX_OPINFO_ACC,
1455};
1456
1457static const struct value_string om2k_event_names[] = {
1458 { OM2K_MO_EVT_START, "START" },
1459 { OM2K_MO_EVT_RX_CONN_COMPL, "RX-CONN-COMPL" },
1460 { OM2K_MO_EVT_RX_RESET_COMPL, "RX-RESET-COMPL" },
1461 { OM2K_MO_EVT_RX_START_REQ_ACCEPT, "RX-RESET-REQ-ACCEPT" },
1462 { OM2K_MO_EVT_RX_START_RES, "RX-START-RESULT" },
1463 { OM2K_MO_EVT_RX_CFG_REQ_ACCEPT, "RX-CFG-REQ-ACCEPT" },
1464 { OM2K_MO_EVT_RX_CFG_RES, "RX-CFG-RESULT" },
1465 { OM2K_MO_EVT_RX_ENA_REQ_ACCEPT, "RX-ENABLE-REQ-ACCEPT" },
1466 { OM2K_MO_EVT_RX_ENA_RES, "RX-ENABLE-RESULT" },
1467 { OM2K_MO_EVT_RX_OPINFO_ACC, "RX-OPINFO-ACCEPT" },
1468 { 0, NULL }
1469};
1470
1471enum om2k_mo_fsm_state {
1472 OM2K_ST_INIT,
1473 OM2K_ST_WAIT_CONN_COMPL,
1474 OM2K_ST_WAIT_RES_COMPL,
1475 OM2K_ST_WAIT_START_ACCEPT,
1476 OM2K_ST_WAIT_START_RES,
1477 OM2K_ST_WAIT_CFG_ACCEPT,
1478 OM2K_ST_WAIT_CFG_RES,
1479 OM2K_ST_WAIT_ENABLE_ACCEPT,
1480 OM2K_ST_WAIT_ENABLE_RES,
1481 OM2K_ST_WAIT_OPINFO_ACCEPT,
1482 OM2K_ST_DONE,
1483 OM2K_ST_ERROR,
1484};
1485
1486struct om2k_mo_fsm_priv {
1487 struct gsm_bts_trx *trx;
1488 struct om2k_mo *mo;
1489 uint8_t ts_nr;
1490};
1491
1492static void om2k_mo_st_init(struct osmo_fsm_inst *fi, uint32_t event, void *data)
1493{
1494 struct om2k_mo_fsm_priv *omfp = fi->priv;
1495
1496 OSMO_ASSERT(event == OM2K_MO_EVT_START);
1497
1498 switch (omfp->mo->addr.class) {
1499 case OM2K_MO_CLS_CF:
1500 /* no Connect required, is always connected */
1501 osmo_fsm_inst_state_chg(fi, OM2K_ST_WAIT_START_ACCEPT,
1502 OM2K_TIMEOUT, 0);
1503 abis_om2k_tx_start_req(omfp->trx->bts, &omfp->mo->addr);
1504 break;
1505 case OM2K_MO_CLS_TRXC:
1506 /* no Connect required, start with Reset */
1507 osmo_fsm_inst_state_chg(fi, OM2K_ST_WAIT_RES_COMPL,
1508 OM2K_TIMEOUT, 0);
1509 abis_om2k_tx_reset_cmd(omfp->trx->bts, &omfp->mo->addr);
1510 break;
1511 default:
1512 /* start with Connect */
1513 osmo_fsm_inst_state_chg(fi, OM2K_ST_WAIT_CONN_COMPL,
1514 OM2K_TIMEOUT, 0);
1515 abis_om2k_tx_connect_cmd(omfp->trx->bts, &omfp->mo->addr);
1516 break;
1517 }
1518}
1519
1520static void om2k_mo_st_wait_conn_compl(struct osmo_fsm_inst *fi, uint32_t event, void *data)
1521{
1522 struct om2k_mo_fsm_priv *omfp = fi->priv;
1523
1524 switch (omfp->mo->addr.class) {
1525#if 0
1526 case OM2K_MO_CLS_TF:
1527 /* skip the reset, hope that helps */
1528 osmo_fsm_inst_state_chg(fi, OM2K_ST_WAIT_START_ACCEPT,
1529 OM2K_TIMEOUT, 0);
1530 abis_om2k_tx_start_req(omfp->trx->bts, &omfp->mo->addr);
1531 break;
1532#endif
1533 default:
1534 osmo_fsm_inst_state_chg(fi, OM2K_ST_WAIT_RES_COMPL,
1535 OM2K_TIMEOUT, 0);
1536 abis_om2k_tx_reset_cmd(omfp->trx->bts, &omfp->mo->addr);
1537 break;
1538 }
1539}
1540
1541static void om2k_mo_st_wait_res_compl(struct osmo_fsm_inst *fi, uint32_t event, void *data)
1542{
1543 struct om2k_mo_fsm_priv *omfp = fi->priv;
1544
1545 osmo_fsm_inst_state_chg(fi, OM2K_ST_WAIT_START_ACCEPT,
1546 OM2K_TIMEOUT, 0);
1547 abis_om2k_tx_start_req(omfp->trx->bts, &omfp->mo->addr);
1548}
1549
1550static void om2k_mo_st_wait_start_accept(struct osmo_fsm_inst *fi, uint32_t event, void *data)
1551{
1552 struct om2k_decoded_msg *omd = data;
1553
1554 switch (omd->msg_type) {
1555 case OM2K_MSGT_START_REQ_ACK:
1556 osmo_fsm_inst_state_chg(fi, OM2K_ST_WAIT_START_RES,
1557 OM2K_TIMEOUT, 0);
1558 break;
1559 case OM2K_MSGT_START_REQ_REJ:
1560 osmo_fsm_inst_state_chg(fi, OM2K_ST_ERROR, 0, 0);
1561 break;
1562 }
1563}
1564
1565static void om2k_mo_st_wait_start_res(struct osmo_fsm_inst *fi, uint32_t event, void *data)
1566{
1567 struct om2k_mo_fsm_priv *omfp = fi->priv;
1568 struct gsm_bts_trx_ts *ts;
1569
1570 switch (omfp->mo->addr.class) {
1571 case OM2K_MO_CLS_CF:
1572 case OM2K_MO_CLS_TRXC:
1573 /* Transition directly to Operational Info */
1574 osmo_fsm_inst_state_chg(fi, OM2K_ST_WAIT_OPINFO_ACCEPT,
1575 OM2K_TIMEOUT, 0);
1576 abis_om2k_tx_op_info(omfp->trx->bts, &omfp->mo->addr, 1);
Harald Welte424656e2016-10-15 16:30:35 +0200[diff] [blame]1577 return;
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]1578 case OM2K_MO_CLS_DP:
1579 /* Transition directoy to WAIT_ENABLE_ACCEPT */
1580 osmo_fsm_inst_state_chg(fi, OM2K_ST_WAIT_ENABLE_ACCEPT,
1581 OM2K_TIMEOUT, 0);
1582 abis_om2k_tx_enable_req(omfp->trx->bts, &omfp->mo->addr);
1583 return;
1584#if 0
1585 case OM2K_MO_CLS_TF:
1586 /* skip the config, hope that helps speeding things up */
1587 osmo_fsm_inst_state_chg(fi, OM2K_ST_WAIT_ENABLE_ACCEPT,
1588 OM2K_TIMEOUT, 0);
1589 abis_om2k_tx_enable_req(omfp->trx->bts, &omfp->mo->addr);
1590 return;
1591#endif
1592 }
1593
1594 osmo_fsm_inst_state_chg(fi, OM2K_ST_WAIT_CFG_ACCEPT,
1595 OM2K_TIMEOUT, 0);
1596 switch (omfp->mo->addr.class) {
1597 case OM2K_MO_CLS_TF:
1598 abis_om2k_tx_tf_conf_req(omfp->trx->bts);
1599 break;
1600 case OM2K_MO_CLS_IS:
1601 abis_om2k_tx_is_conf_req(omfp->trx->bts);
1602 break;
1603 case OM2K_MO_CLS_CON:
Harald Welteeae68292016-11-11 19:41:59 +0100[diff] [blame]1604 abis_om2k_tx_con_conf_req(omfp->trx->bts);
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]1605 break;
1606 case OM2K_MO_CLS_TX:
1607 abis_om2k_tx_tx_conf_req(omfp->trx);
1608 break;
1609 case OM2K_MO_CLS_RX:
1610 abis_om2k_tx_rx_conf_req(omfp->trx);
1611 break;
1612 case OM2K_MO_CLS_TS:
1613 ts = mo2obj(omfp->trx->bts, &omfp->mo->addr);
1614 abis_om2k_tx_ts_conf_req(ts);
1615 break;
1616 }
1617}
1618
1619static void om2k_mo_st_wait_cfg_accept(struct osmo_fsm_inst *fi, uint32_t event, void *data)
1620{
1621 struct om2k_mo_fsm_priv *omfp = fi->priv;
1622 uint32_t timeout = OM2K_TIMEOUT;
1623
1624 if (omfp->mo->addr.class == OM2K_MO_CLS_TF)
1625 timeout = 600;
1626
1627 osmo_fsm_inst_state_chg(fi, OM2K_ST_WAIT_CFG_RES, timeout, 0);
1628}
1629
1630static void om2k_mo_st_wait_cfg_res(struct osmo_fsm_inst *fi, uint32_t event, void *data)
1631{
1632 struct om2k_mo_fsm_priv *omfp = fi->priv;
1633 struct om2k_decoded_msg *omd = data;
1634 uint8_t accordance;
1635
1636 if (!TLVP_PRESENT(&omd->tp, OM2K_DEI_ACCORDANCE_IND)) {
1637 osmo_fsm_inst_state_chg(fi, OM2K_ST_ERROR, 0, 0);
1638 return;
1639 }
1640 accordance = *TLVP_VAL(&omd->tp, OM2K_DEI_ACCORDANCE_IND);
1641
1642 if (accordance != 0) {
1643 /* accordance not OK */
1644 osmo_fsm_inst_state_chg(fi, OM2K_ST_ERROR, 0, 0);
1645 return;
1646 }
1647
1648 osmo_fsm_inst_state_chg(fi, OM2K_ST_WAIT_ENABLE_ACCEPT,
1649 OM2K_TIMEOUT, 0);
1650 abis_om2k_tx_enable_req(omfp->trx->bts, &omfp->mo->addr);
1651}
1652
1653static void om2k_mo_st_wait_enable_accept(struct osmo_fsm_inst *fi, uint32_t event, void *data)
1654{
1655 struct om2k_decoded_msg *omd = data;
1656
1657 switch (omd->msg_type) {
1658 case OM2K_MSGT_ENABLE_REQ_REJ:
1659 osmo_fsm_inst_state_chg(fi, OM2K_ST_ERROR, 0, 0);
1660 break;
1661 case OM2K_MSGT_ENABLE_REQ_ACK:
1662 osmo_fsm_inst_state_chg(fi, OM2K_ST_WAIT_ENABLE_RES,
1663 OM2K_TIMEOUT, 0);
1664 }
1665}
1666
1667static void om2k_mo_st_wait_enable_res(struct osmo_fsm_inst *fi, uint32_t event, void *data)
1668{
1669 struct om2k_mo_fsm_priv *omfp = fi->priv;
1670 //struct om2k_decoded_msg *omd = data;
1671 /* TODO: check if state is actually enabled now? */
1672
1673 osmo_fsm_inst_state_chg(fi, OM2K_ST_WAIT_OPINFO_ACCEPT,
1674 OM2K_TIMEOUT, 0);
1675 abis_om2k_tx_op_info(omfp->trx->bts, &omfp->mo->addr, 1);
1676}
1677
1678static void om2k_mo_st_wait_opinfo_accept(struct osmo_fsm_inst *fi, uint32_t event, void *data)
1679{
Harald Welte80ccb952016-11-15 23:23:42 +0100[diff] [blame]1680 struct om2k_mo_fsm_priv *omfp = fi->priv;
1681
1682 /* if we have just received opinfo accept for the timeslot,
1683 * start dynamic TCH switching procedures */
1684 if (omfp->mo->addr.class == OM2K_MO_CLS_TS) {
Neels Hofmeyr2b9c5342016-12-02 01:58:08 +0100[diff] [blame]1685 struct gsm_bts_trx_ts *ts;
Harald Welte80ccb952016-11-15 23:23:42 +0100[diff] [blame]1686 ts = mo2obj(omfp->trx->bts, &omfp->mo->addr);
1687 dyn_ts_init(ts);
1688 }
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]1689 osmo_fsm_inst_state_chg(fi, OM2K_ST_DONE, 0, 0);
1690}
1691
1692static void om2k_mo_s_done_onenter(struct osmo_fsm_inst *fi, uint32_t prev_state)
1693{
1694 osmo_fsm_inst_term(fi, OSMO_FSM_TERM_REGULAR, NULL);
1695}
1696
1697static const struct osmo_fsm_state om2k_is_states[] = {
1698 [OM2K_ST_INIT] = {
1699 .name = "INIT",
1700 .in_event_mask = S(OM2K_MO_EVT_START),
1701 .out_state_mask = S(OM2K_ST_DONE) |
1702 S(OM2K_ST_ERROR) |
1703 S(OM2K_ST_WAIT_CONN_COMPL) |
1704 S(OM2K_ST_WAIT_START_ACCEPT) |
1705 S(OM2K_ST_WAIT_RES_COMPL),
1706 .action = om2k_mo_st_init,
1707 },
1708 [OM2K_ST_WAIT_CONN_COMPL] = {
1709 .name = "WAIT-CONN-COMPL",
1710 .in_event_mask = S(OM2K_MO_EVT_RX_CONN_COMPL),
1711 .out_state_mask = S(OM2K_ST_DONE) |
1712 S(OM2K_ST_ERROR) |
1713 S(OM2K_ST_WAIT_START_ACCEPT) |
1714 S(OM2K_ST_WAIT_RES_COMPL),
1715 .action = om2k_mo_st_wait_conn_compl,
1716 },
1717 [OM2K_ST_WAIT_RES_COMPL] = {
1718 .name = "WAIT-RES-COMPL",
1719 .in_event_mask = S(OM2K_MO_EVT_RX_RESET_COMPL),
1720 .out_state_mask = S(OM2K_ST_DONE) |
1721 S(OM2K_ST_ERROR) |
1722 S(OM2K_ST_WAIT_START_ACCEPT),
1723 .action = om2k_mo_st_wait_res_compl,
1724 },
1725 [OM2K_ST_WAIT_START_ACCEPT] = {
1726 .name = "WAIT-START-ACCEPT",
1727 .in_event_mask = S(OM2K_MO_EVT_RX_START_REQ_ACCEPT),
1728 .out_state_mask = S(OM2K_ST_DONE) |
1729 S(OM2K_ST_ERROR) |
1730 S(OM2K_ST_WAIT_START_RES),
1731 .action =om2k_mo_st_wait_start_accept,
1732 },
1733 [OM2K_ST_WAIT_START_RES] = {
1734 .name = "WAIT-START-RES",
1735 .in_event_mask = S(OM2K_MO_EVT_RX_START_RES),
1736 .out_state_mask = S(OM2K_ST_DONE) |
1737 S(OM2K_ST_ERROR) |
1738 S(OM2K_ST_WAIT_CFG_ACCEPT) |
1739 S(OM2K_ST_WAIT_OPINFO_ACCEPT),
1740 .action = om2k_mo_st_wait_start_res,
1741 },
1742 [OM2K_ST_WAIT_CFG_ACCEPT] = {
1743 .name = "WAIT-CFG-ACCEPT",
1744 .in_event_mask = S(OM2K_MO_EVT_RX_CFG_REQ_ACCEPT),
1745 .out_state_mask = S(OM2K_ST_DONE) |
1746 S(OM2K_ST_ERROR) |
1747 S(OM2K_ST_WAIT_CFG_RES),
1748 .action = om2k_mo_st_wait_cfg_accept,
1749 },
1750 [OM2K_ST_WAIT_CFG_RES] = {
1751 .name = "WAIT-CFG-RES",
1752 .in_event_mask = S(OM2K_MO_EVT_RX_CFG_RES),
1753 .out_state_mask = S(OM2K_ST_DONE) |
1754 S(OM2K_ST_ERROR) |
1755 S(OM2K_ST_WAIT_ENABLE_ACCEPT),
1756 .action = om2k_mo_st_wait_cfg_res,
1757 },
1758 [OM2K_ST_WAIT_ENABLE_ACCEPT] = {
1759 .name = "WAIT-ENABLE-ACCEPT",
1760 .in_event_mask = S(OM2K_MO_EVT_RX_ENA_REQ_ACCEPT),
1761 .out_state_mask = S(OM2K_ST_DONE) |
1762 S(OM2K_ST_ERROR) |
1763 S(OM2K_ST_WAIT_ENABLE_RES),
1764 .action = om2k_mo_st_wait_enable_accept,
1765 },
1766 [OM2K_ST_WAIT_ENABLE_RES] = {
1767 .name = "WAIT-ENABLE-RES",
1768 .in_event_mask = S(OM2K_MO_EVT_RX_ENA_RES),
1769 .out_state_mask = S(OM2K_ST_DONE) |
1770 S(OM2K_ST_ERROR) |
1771 S(OM2K_ST_WAIT_OPINFO_ACCEPT),
1772 .action = om2k_mo_st_wait_enable_res,
1773 },
1774 [OM2K_ST_WAIT_OPINFO_ACCEPT] = {
1775 .name = "WAIT-OPINFO-ACCEPT",
1776 .in_event_mask = S(OM2K_MO_EVT_RX_OPINFO_ACC),
1777 .out_state_mask = S(OM2K_ST_DONE) |
1778 S(OM2K_ST_ERROR),
1779 .action = om2k_mo_st_wait_opinfo_accept,
1780 },
1781 [OM2K_ST_DONE] = {
1782 .name = "DONE",
1783 .in_event_mask = 0,
1784 .out_state_mask = 0,
1785 .onenter = om2k_mo_s_done_onenter,
1786 },
1787 [OM2K_ST_ERROR] = {
1788 .name = "ERROR",
1789 .in_event_mask = 0,
1790 .out_state_mask = 0,
1791 .onenter = om2k_mo_s_done_onenter,
1792 },
1793
1794};
1795
1796static int om2k_mo_timer_cb(struct osmo_fsm_inst *fi)
1797{
1798 osmo_fsm_inst_state_chg(fi, OM2K_ST_ERROR, 0, 0);
1799 return 0;
1800}
1801
1802static struct osmo_fsm om2k_mo_fsm = {
1803 .name = "OM2000-MO",
1804 .states = om2k_is_states,
1805 .num_states = ARRAY_SIZE(om2k_is_states),
1806 .log_subsys = DNM,
1807 .event_names = om2k_event_names,
1808 .timer_cb = om2k_mo_timer_cb,
1809};
1810
1811struct osmo_fsm_inst *om2k_mo_fsm_start(struct osmo_fsm_inst *parent,
1812 uint32_t term_event,
1813 struct gsm_bts_trx *trx, struct om2k_mo *mo)
1814{
1815 struct osmo_fsm_inst *fi;
1816 struct om2k_mo_fsm_priv *omfp;
1817 char idbuf[64];
1818
1819 snprintf(idbuf, sizeof(idbuf), "%s-%s", parent->id,
1820 om2k_mo_name(&mo->addr));
1821
1822 fi = osmo_fsm_inst_alloc_child_id(&om2k_mo_fsm, parent,
1823 term_event, idbuf);
1824 if (!fi)
1825 return NULL;
1826
1827 mo->fsm = fi;
1828 omfp = talloc_zero(fi, struct om2k_mo_fsm_priv);
1829 omfp->mo = mo;
1830 omfp->trx = trx;
1831 fi->priv = omfp;
1832
1833 osmo_fsm_inst_dispatch(fi, OM2K_MO_EVT_START, NULL);
1834
1835 return fi;
1836}
1837
1838int om2k_mo_fsm_recvmsg(struct gsm_bts *bts, struct om2k_mo *mo,
1839 struct om2k_decoded_msg *odm)
1840{
1841 switch (odm->msg_type) {
1842 case OM2K_MSGT_CONNECT_COMPL:
1843 case OM2K_MSGT_CONNECT_REJ:
1844 osmo_fsm_inst_dispatch(mo->fsm,
1845 OM2K_MO_EVT_RX_CONN_COMPL, odm);
1846 break;
1847
1848 case OM2K_MSGT_RESET_COMPL:
1849 case OM2K_MSGT_RESET_REJ:
1850 osmo_fsm_inst_dispatch(mo->fsm,
1851 OM2K_MO_EVT_RX_RESET_COMPL, odm);
1852 break;
1853
1854 case OM2K_MSGT_START_REQ_ACK:
1855 case OM2K_MSGT_START_REQ_REJ:
1856 osmo_fsm_inst_dispatch(mo->fsm,
1857 OM2K_MO_EVT_RX_START_REQ_ACCEPT, odm);
1858 break;
1859
1860 case OM2K_MSGT_START_RES:
1861 osmo_fsm_inst_dispatch(mo->fsm,
1862 OM2K_MO_EVT_RX_START_RES, odm);
1863 break;
1864
1865 case OM2K_MSGT_CON_CONF_REQ_ACK:
1866 case OM2K_MSGT_IS_CONF_REQ_ACK:
1867 case OM2K_MSGT_RX_CONF_REQ_ACK:
1868 case OM2K_MSGT_TF_CONF_REQ_ACK:
1869 case OM2K_MSGT_TS_CONF_REQ_ACK:
1870 case OM2K_MSGT_TX_CONF_REQ_ACK:
1871 osmo_fsm_inst_dispatch(mo->fsm,
1872 OM2K_MO_EVT_RX_CFG_REQ_ACCEPT, odm);
1873 break;
1874
1875 case OM2K_MSGT_CON_CONF_RES:
1876 case OM2K_MSGT_IS_CONF_RES:
1877 case OM2K_MSGT_RX_CONF_RES:
1878 case OM2K_MSGT_TF_CONF_RES:
1879 case OM2K_MSGT_TS_CONF_RES:
1880 case OM2K_MSGT_TX_CONF_RES:
1881 osmo_fsm_inst_dispatch(mo->fsm,
1882 OM2K_MO_EVT_RX_CFG_RES, odm);
1883 break;
1884
1885 case OM2K_MSGT_ENABLE_REQ_ACK:
1886 case OM2K_MSGT_ENABLE_REQ_REJ:
1887 osmo_fsm_inst_dispatch(mo->fsm,
1888 OM2K_MO_EVT_RX_ENA_REQ_ACCEPT, odm);
1889 break;
1890 case OM2K_MSGT_ENABLE_RES:
1891 osmo_fsm_inst_dispatch(mo->fsm,
1892 OM2K_MO_EVT_RX_ENA_RES, odm);
1893 break;
1894
1895 case OM2K_MSGT_OP_INFO_ACK:
1896 case OM2K_MSGT_OP_INFO_REJ:
1897 osmo_fsm_inst_dispatch(mo->fsm,
1898 OM2K_MO_EVT_RX_OPINFO_ACC, odm);
1899 break;
1900 default:
1901 return -1;
1902 }
1903
1904 return 0;
1905}
1906
1907/***********************************************************************
1908 * OM2000 TRX Finite State Machine, initializes TRXC and all siblings
1909 ***********************************************************************/
1910
1911enum om2k_trx_event {
1912 OM2K_TRX_EVT_START,
1913 OM2K_TRX_EVT_TRXC_DONE,
1914 OM2K_TRX_EVT_TX_DONE,
1915 OM2K_TRX_EVT_RX_DONE,
1916 OM2K_TRX_EVT_TS_DONE,
1917 OM2K_TRX_EVT_STOP,
1918};
1919
1920static struct value_string om2k_trx_events[] = {
1921 { OM2K_TRX_EVT_START, "START" },
1922 { OM2K_TRX_EVT_TRXC_DONE, "TRXC-DONE" },
1923 { OM2K_TRX_EVT_TX_DONE, "TX-DONE" },
1924 { OM2K_TRX_EVT_RX_DONE, "RX-DONE" },
1925 { OM2K_TRX_EVT_TS_DONE, "TS-DONE" },
1926 { OM2K_TRX_EVT_STOP, "STOP" },
1927 { 0, NULL }
1928};
1929
1930enum om2k_trx_state {
1931 OM2K_TRX_S_INIT,
1932 OM2K_TRX_S_WAIT_TRXC,
1933 OM2K_TRX_S_WAIT_TX,
1934 OM2K_TRX_S_WAIT_RX,
1935 OM2K_TRX_S_WAIT_TS,
1936 OM2K_TRX_S_DONE,
1937 OM2K_TRX_S_ERROR
1938};
1939
1940struct om2k_trx_fsm_priv {
1941 struct gsm_bts_trx *trx;
1942 uint8_t next_ts_nr;
1943};
1944
1945static void om2k_trx_s_init(struct osmo_fsm_inst *fi, uint32_t event, void *data)
1946{
1947 struct om2k_trx_fsm_priv *otfp = fi->priv;
1948
1949 /* First initialize TRXC */
1950 osmo_fsm_inst_state_chg(fi, OM2K_TRX_S_WAIT_TRXC,
1951 TRX_FSM_TIMEOUT, 0);
1952 om2k_mo_fsm_start(fi, OM2K_TRX_EVT_TRXC_DONE, otfp->trx,
1953 &otfp->trx->rbs2000.trxc.om2k_mo);
1954}
1955
1956static void om2k_trx_s_wait_trxc(struct osmo_fsm_inst *fi, uint32_t event, void *data)
1957{
1958 struct om2k_trx_fsm_priv *otfp = fi->priv;
1959
1960 /* Initialize TX after TRXC */
1961 osmo_fsm_inst_state_chg(fi, OM2K_TRX_S_WAIT_TX,
1962 TRX_FSM_TIMEOUT, 0);
1963 om2k_mo_fsm_start(fi, OM2K_TRX_EVT_TX_DONE, otfp->trx,
1964 &otfp->trx->rbs2000.tx.om2k_mo);
1965}
1966
1967static void om2k_trx_s_wait_tx(struct osmo_fsm_inst *fi, uint32_t event, void *data)
1968{
1969 struct om2k_trx_fsm_priv *otfp = fi->priv;
1970
1971 /* Initialize RX after TX */
1972 osmo_fsm_inst_state_chg(fi, OM2K_TRX_S_WAIT_RX,
1973 TRX_FSM_TIMEOUT, 0);
1974 om2k_mo_fsm_start(fi, OM2K_TRX_EVT_RX_DONE, otfp->trx,
1975 &otfp->trx->rbs2000.rx.om2k_mo);
1976}
1977
1978static void om2k_trx_s_wait_rx(struct osmo_fsm_inst *fi, uint32_t event, void *data)
1979{
1980 struct om2k_trx_fsm_priv *otfp = fi->priv;
1981 struct gsm_bts_trx_ts *ts;
1982
1983 /* Initialize Timeslots after TX */
1984 osmo_fsm_inst_state_chg(fi, OM2K_TRX_S_WAIT_TS,
1985 TRX_FSM_TIMEOUT, 0);
1986 otfp->next_ts_nr = 0;
1987 ts = &otfp->trx->ts[otfp->next_ts_nr++];
1988 om2k_mo_fsm_start(fi, OM2K_TRX_EVT_TS_DONE, otfp->trx,
1989 &ts->rbs2000.om2k_mo);
1990}
1991
1992static void om2k_trx_s_wait_ts(struct osmo_fsm_inst *fi, uint32_t event, void *data)
1993{
1994 struct om2k_trx_fsm_priv *otfp = fi->priv;
1995 struct gsm_bts_trx_ts *ts;
1996
1997 if (otfp->next_ts_nr < 8) {
1998 /* iterate to the next timeslot */
1999 ts = &otfp->trx->ts[otfp->next_ts_nr++];
2000 om2k_mo_fsm_start(fi, OM2K_TRX_EVT_TS_DONE, otfp->trx,
2001 &ts->rbs2000.om2k_mo);
2002 } else {
2003 /* only after all 8 TS */
2004 osmo_fsm_inst_state_chg(fi, OM2K_TRX_S_DONE, 0, 0);
2005 }
2006}
2007
2008static void om2k_trx_s_done_onenter(struct osmo_fsm_inst *fi, uint32_t prev_state)
2009{
2010 struct om2k_trx_fsm_priv *otfp = fi->priv;
2011 gsm_bts_trx_set_system_infos(otfp->trx);
2012 osmo_fsm_inst_term(fi, OSMO_FSM_TERM_REGULAR, NULL);
2013}
2014
2015static const struct osmo_fsm_state om2k_trx_states[] = {
2016 [OM2K_TRX_S_INIT] = {
2017 .in_event_mask = S(OM2K_TRX_EVT_START),
2018 .out_state_mask = S(OM2K_TRX_S_WAIT_TRXC),
2019 .name = "INIT",
2020 .action = om2k_trx_s_init,
2021 },
2022 [OM2K_TRX_S_WAIT_TRXC] = {
2023 .in_event_mask = S(OM2K_TRX_EVT_TRXC_DONE),
2024 .out_state_mask = S(OM2K_TRX_S_ERROR) |
2025 S(OM2K_TRX_S_WAIT_TX),
2026 .name = "WAIT-TRXC",
2027 .action = om2k_trx_s_wait_trxc,
2028 },
2029 [OM2K_TRX_S_WAIT_TX] = {
2030 .in_event_mask = S(OM2K_TRX_EVT_TX_DONE),
2031 .out_state_mask = S(OM2K_TRX_S_ERROR) |
2032 S(OM2K_TRX_S_WAIT_RX),
2033 .name = "WAIT-TX",
2034 .action = om2k_trx_s_wait_tx,
2035 },
2036 [OM2K_TRX_S_WAIT_RX] = {
2037 .in_event_mask = S(OM2K_TRX_EVT_RX_DONE),
2038 .out_state_mask = S(OM2K_TRX_S_ERROR) |
2039 S(OM2K_TRX_S_WAIT_TS),
2040 .name = "WAIT-RX",
2041 .action = om2k_trx_s_wait_rx,
2042 },
2043 [OM2K_TRX_S_WAIT_TS] = {
2044 .in_event_mask = S(OM2K_TRX_EVT_TS_DONE),
2045 .out_state_mask = S(OM2K_TRX_S_ERROR) |
2046 S(OM2K_TRX_S_DONE),
2047 .name = "WAIT-TS",
2048 .action = om2k_trx_s_wait_ts,
2049 },
2050 [OM2K_TRX_S_DONE] = {
2051 .name = "DONE",
2052 .onenter = om2k_trx_s_done_onenter,
2053 },
2054 [OM2K_TRX_S_ERROR] = {
2055 .name = "ERROR",
2056 },
2057};
2058
2059static int om2k_trx_timer_cb(struct osmo_fsm_inst *fi)
2060{
2061 osmo_fsm_inst_state_chg(fi, OM2K_TRX_S_ERROR, 0, 0);
2062 return 0;
2063}
2064
2065static struct osmo_fsm om2k_trx_fsm = {
2066 .name = "OM2000-TRX",
2067 .states = om2k_trx_states,
2068 .num_states = ARRAY_SIZE(om2k_trx_states),
2069 .log_subsys = DNM,
2070 .event_names = om2k_trx_events,
2071 .timer_cb = om2k_trx_timer_cb,
2072};
2073
2074struct osmo_fsm_inst *om2k_trx_fsm_start(struct osmo_fsm_inst *parent,
2075 struct gsm_bts_trx *trx,
2076 uint32_t term_event)
2077{
2078 struct osmo_fsm_inst *fi;
2079 struct om2k_trx_fsm_priv *otfp;
2080 char idbuf[32];
2081
2082 snprintf(idbuf, sizeof(idbuf), "%u/%u", trx->bts->nr, trx->nr);
2083
2084 fi = osmo_fsm_inst_alloc_child_id(&om2k_trx_fsm, parent, term_event,
2085 idbuf);
2086 if (!fi)
2087 return NULL;
2088
2089 otfp = talloc_zero(fi, struct om2k_trx_fsm_priv);
2090 otfp->trx = trx;
2091 fi->priv = otfp;
2092
2093 osmo_fsm_inst_dispatch(fi, OM2K_TRX_EVT_START, NULL);
2094
2095 return fi;
2096}
2097
2098
2099/***********************************************************************
2100 * OM2000 BTS Finite State Machine, initializes CF and all siblings
2101 ***********************************************************************/
2102
2103enum om2k_bts_event {
2104 OM2K_BTS_EVT_START,
2105 OM2K_BTS_EVT_CF_DONE,
2106 OM2K_BTS_EVT_IS_DONE,
Harald Welteeae68292016-11-11 19:41:59 +0100[diff] [blame]2107 OM2K_BTS_EVT_CON_DONE,
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]2108 OM2K_BTS_EVT_TF_DONE,
2109 OM2K_BTS_EVT_TRX_DONE,
2110 OM2K_BTS_EVT_STOP,
2111};
2112
2113static const struct value_string om2k_bts_events[] = {
2114 { OM2K_BTS_EVT_START, "START" },
2115 { OM2K_BTS_EVT_CF_DONE, "CF-DONE" },
2116 { OM2K_BTS_EVT_IS_DONE, "IS-DONE" },
Harald Welteeae68292016-11-11 19:41:59 +0100[diff] [blame]2117 { OM2K_BTS_EVT_CON_DONE, "CON-DONE" },
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]2118 { OM2K_BTS_EVT_TF_DONE, "TF-DONE" },
2119 { OM2K_BTS_EVT_TRX_DONE, "TRX-DONE" },
2120 { OM2K_BTS_EVT_STOP, "STOP" },
2121 { 0, NULL }
2122};
2123
2124enum om2k_bts_state {
2125 OM2K_BTS_S_INIT,
2126 OM2K_BTS_S_WAIT_CF,
2127 OM2K_BTS_S_WAIT_IS,
Harald Welteeae68292016-11-11 19:41:59 +0100[diff] [blame]2128 OM2K_BTS_S_WAIT_CON,
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]2129 OM2K_BTS_S_WAIT_TF,
2130 OM2K_BTS_S_WAIT_TRX,
2131 OM2K_BTS_S_DONE,
2132 OM2K_BTS_S_ERROR,
2133};
2134
2135struct om2k_bts_fsm_priv {
2136 struct gsm_bts *bts;
2137 uint8_t next_trx_nr;
2138};
2139
2140static void om2k_bts_s_init(struct osmo_fsm_inst *fi, uint32_t event, void *data)
2141{
2142 struct om2k_bts_fsm_priv *obfp = fi->priv;
2143 struct gsm_bts *bts = obfp->bts;
2144
2145 OSMO_ASSERT(event == OM2K_BTS_EVT_START);
2146 osmo_fsm_inst_state_chg(fi, OM2K_BTS_S_WAIT_CF,
2147 BTS_FSM_TIMEOUT, 0);
2148 om2k_mo_fsm_start(fi, OM2K_BTS_EVT_CF_DONE, bts->c0,
2149 &bts->rbs2000.cf.om2k_mo);
2150}
2151
2152static void om2k_bts_s_wait_cf(struct osmo_fsm_inst *fi, uint32_t event, void *data)
2153{
2154 struct om2k_bts_fsm_priv *obfp = fi->priv;
2155 struct gsm_bts *bts = obfp->bts;
2156
2157 OSMO_ASSERT(event == OM2K_BTS_EVT_CF_DONE);
2158 osmo_fsm_inst_state_chg(fi, OM2K_BTS_S_WAIT_IS,
2159 BTS_FSM_TIMEOUT, 0);
2160 om2k_mo_fsm_start(fi, OM2K_BTS_EVT_IS_DONE, bts->c0,
2161 &bts->rbs2000.is.om2k_mo);
2162}
2163
2164static void om2k_bts_s_wait_is(struct osmo_fsm_inst *fi, uint32_t event, void *data)
2165{
2166 struct om2k_bts_fsm_priv *obfp = fi->priv;
2167 struct gsm_bts *bts = obfp->bts;
2168
2169 OSMO_ASSERT(event == OM2K_BTS_EVT_IS_DONE);
Harald Welteeae68292016-11-11 19:41:59 +0100[diff] [blame]2170 osmo_fsm_inst_state_chg(fi, OM2K_BTS_S_WAIT_CON,
2171 BTS_FSM_TIMEOUT, 0);
2172 om2k_mo_fsm_start(fi, OM2K_BTS_EVT_CON_DONE, bts->c0,
2173 &bts->rbs2000.con.om2k_mo);
2174}
2175
2176static void om2k_bts_s_wait_con(struct osmo_fsm_inst *fi, uint32_t event, void *data)
2177{
2178 struct om2k_bts_fsm_priv *obfp = fi->priv;
2179 struct gsm_bts *bts = obfp->bts;
2180
2181 OSMO_ASSERT(event == OM2K_BTS_EVT_CON_DONE);
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]2182 /* TF can take a long time to initialize, wait for 10min */
2183 osmo_fsm_inst_state_chg(fi, OM2K_BTS_S_WAIT_TF, 600, 0);
2184 om2k_mo_fsm_start(fi, OM2K_BTS_EVT_TF_DONE, bts->c0,
2185 &bts->rbs2000.tf.om2k_mo);
2186}
2187
2188static void om2k_bts_s_wait_tf(struct osmo_fsm_inst *fi, uint32_t event, void *data)
2189{
2190 struct om2k_bts_fsm_priv *obfp = fi->priv;
2191 struct gsm_bts_trx *trx;
2192
2193 OSMO_ASSERT(event == OM2K_BTS_EVT_TF_DONE);
2194
2195 osmo_fsm_inst_state_chg(fi, OM2K_BTS_S_WAIT_TRX,
2196 BTS_FSM_TIMEOUT, 0);
2197 obfp->next_trx_nr = 0;
2198 trx = gsm_bts_trx_num(obfp->bts, obfp->next_trx_nr++);
2199 om2k_trx_fsm_start(fi, trx, OM2K_BTS_EVT_TRX_DONE);
2200}
2201
2202static void om2k_bts_s_wait_trx(struct osmo_fsm_inst *fi, uint32_t event, void *data)
2203{
2204 struct om2k_bts_fsm_priv *obfp = fi->priv;
2205
2206 OSMO_ASSERT(event == OM2K_BTS_EVT_TRX_DONE);
2207
2208 if (obfp->next_trx_nr < obfp->bts->num_trx) {
2209 struct gsm_bts_trx *trx;
2210 trx = gsm_bts_trx_num(obfp->bts, obfp->next_trx_nr++);
2211 om2k_trx_fsm_start(fi, trx, OM2K_BTS_EVT_TRX_DONE);
2212 } else {
2213 osmo_fsm_inst_state_chg(fi, OM2K_BTS_S_DONE, 0, 0);
2214 }
2215}
2216
2217static void om2k_bts_s_done_onenter(struct osmo_fsm_inst *fi, uint32_t prev_state)
2218{
2219 osmo_fsm_inst_term(fi, OSMO_FSM_TERM_REGULAR, NULL);
2220}
2221
2222static const struct osmo_fsm_state om2k_bts_states[] = {
2223 [OM2K_BTS_S_INIT] = {
2224 .in_event_mask = S(OM2K_BTS_EVT_START),
2225 .out_state_mask = S(OM2K_BTS_S_WAIT_CF),
2226 .name = "INIT",
2227 .action = om2k_bts_s_init,
2228 },
2229 [OM2K_BTS_S_WAIT_CF] = {
2230 .in_event_mask = S(OM2K_BTS_EVT_CF_DONE),
2231 .out_state_mask = S(OM2K_BTS_S_ERROR) |
2232 S(OM2K_BTS_S_WAIT_IS),
2233 .name = "WAIT-CF",
2234 .action = om2k_bts_s_wait_cf,
2235 },
2236 [OM2K_BTS_S_WAIT_IS] = {
2237 .in_event_mask = S(OM2K_BTS_EVT_IS_DONE),
2238 .out_state_mask = S(OM2K_BTS_S_ERROR) |
Harald Welteeae68292016-11-11 19:41:59 +0100[diff] [blame]2239 S(OM2K_BTS_S_WAIT_CON),
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]2240 .name = "WAIT-IS",
2241 .action = om2k_bts_s_wait_is,
2242 },
Harald Welteeae68292016-11-11 19:41:59 +0100[diff] [blame]2243 [OM2K_BTS_S_WAIT_CON] = {
2244 .in_event_mask = S(OM2K_BTS_EVT_CON_DONE),
2245 .out_state_mask = S(OM2K_BTS_S_ERROR) |
2246 S(OM2K_BTS_S_WAIT_TF),
2247 .name = "WAIT-CON",
2248 .action = om2k_bts_s_wait_con,
2249 },
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]2250 [OM2K_BTS_S_WAIT_TF] = {
2251 .in_event_mask = S(OM2K_BTS_EVT_TF_DONE),
2252 .out_state_mask = S(OM2K_BTS_S_ERROR) |
2253 S(OM2K_BTS_S_WAIT_TRX),
2254 .name = "WAIT-TF",
2255 .action = om2k_bts_s_wait_tf,
2256 },
2257 [OM2K_BTS_S_WAIT_TRX] = {
2258 .in_event_mask = S(OM2K_BTS_EVT_TRX_DONE),
2259 .out_state_mask = S(OM2K_BTS_S_ERROR) |
2260 S(OM2K_BTS_S_DONE),
2261 .name = "WAIT-TRX",
2262 .action = om2k_bts_s_wait_trx,
2263 },
2264 [OM2K_BTS_S_DONE] = {
2265 .name = "DONE",
2266 .onenter = om2k_bts_s_done_onenter,
2267 },
2268 [OM2K_BTS_S_ERROR] = {
2269 .name = "ERROR",
2270 },
2271};
2272
2273static int om2k_bts_timer_cb(struct osmo_fsm_inst *fi)
2274{
2275 osmo_fsm_inst_state_chg(fi, OM2K_BTS_S_ERROR, 0, 0);
2276 return 0;
2277}
2278
2279static struct osmo_fsm om2k_bts_fsm = {
2280 .name = "OM2000-BTS",
2281 .states = om2k_bts_states,
2282 .num_states = ARRAY_SIZE(om2k_bts_states),
2283 .log_subsys = DNM,
2284 .event_names = om2k_bts_events,
2285 .timer_cb = om2k_bts_timer_cb,
2286};
2287
2288struct osmo_fsm_inst *
2289om2k_bts_fsm_start(struct gsm_bts *bts)
2290{
2291 struct osmo_fsm_inst *fi;
2292 struct om2k_bts_fsm_priv *obfp;
2293 char idbuf[16];
2294
2295 snprintf(idbuf, sizeof(idbuf), "%u", bts->nr);
2296
2297 fi = osmo_fsm_inst_alloc(&om2k_bts_fsm, bts, NULL,
2298 LOGL_DEBUG, idbuf);
2299 if (!fi)
2300 return NULL;
2301 fi->priv = obfp = talloc_zero(fi, struct om2k_bts_fsm_priv);
2302 obfp->bts = bts;
2303
2304 osmo_fsm_inst_dispatch(fi, OM2K_BTS_EVT_START, NULL);
2305
2306 return fi;
2307}
2308
2309
2310/***********************************************************************
2311 * OM2000 Negotiation
2312 ***********************************************************************/
2313
Harald Welte6fec79d2011-02-12 14:57:17 +0100[diff] [blame]2314static int abis_om2k_tx_negot_req_ack(struct gsm_bts *bts, const struct abis_om2k_mo *mo,
Harald Welte73541072011-02-12 13:44:14 +0100[diff] [blame]2315 uint8_t *data, unsigned int len)
2316{
2317 struct msgb *msg = om2k_msgb_alloc();
2318 struct abis_om2k_hdr *o2k;
2319
2320 o2k = (struct abis_om2k_hdr *) msgb_put(msg, sizeof(*o2k));
Harald Welte1164dce2011-03-05 19:21:26 +0100[diff] [blame]2321 fill_om2k_hdr(o2k, mo, OM2K_MSGT_NEGOT_REQ_ACK);
Harald Welte73541072011-02-12 13:44:14 +0100[diff] [blame]2322
2323 msgb_tlv_put(msg, OM2K_DEI_NEGOT_REC2, len, data);
2324
2325 DEBUGP(DNM, "Tx MO=%s %s\n", om2k_mo_name(mo),
2326 get_value_string(om2k_msgcode_vals, OM2K_MSGT_NEGOT_REQ_ACK));
2327
2328 return abis_om2k_sendmsg(bts, msg);
2329}
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]2330
Harald Welte563d3162011-02-12 18:11:16 +0100[diff] [blame]2331struct iwd_version {
2332 uint8_t gen_char[3+1];
2333 uint8_t rev_char[3+1];
2334};
2335
2336struct iwd_type {
2337 uint8_t num_vers;
2338 struct iwd_version v[8];
2339};
2340
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]2341static int om2k_rx_negot_req(struct msgb *msg)
2342{
Pablo Neira Ayuso7abecfc2011-08-17 22:43:54 +0200[diff] [blame]2343 struct e1inp_sign_link *sign_link = (struct e1inp_sign_link *)msg->dst;
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]2344 struct abis_om2k_hdr *o2h = msgb_l2(msg);
Harald Welte563d3162011-02-12 18:11:16 +0100[diff] [blame]2345 struct iwd_type iwd_types[16];
2346 uint8_t num_iwd_types = o2h->data[2];
2347 uint8_t *cur = o2h->data+3;
2348 unsigned int i, v;
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]2349
Harald Welte563d3162011-02-12 18:11:16 +0100[diff] [blame]2350 uint8_t out_buf[1024];
2351 uint8_t *out_cur = out_buf+1;
2352 uint8_t out_num_types = 0;
2353
2354 memset(iwd_types, 0, sizeof(iwd_types));
2355
2356 /* Parse the RBS-supported IWD versions into iwd_types array */
2357 for (i = 0; i < num_iwd_types; i++) {
2358 uint8_t num_versions = *cur++;
2359 uint8_t iwd_type = *cur++;
2360
2361 iwd_types[iwd_type].num_vers = num_versions;
2362
2363 for (v = 0; v < num_versions; v++) {
2364 struct iwd_version *iwd_v = &iwd_types[iwd_type].v[v];
2365
2366 memcpy(iwd_v->gen_char, cur, 3);
Harald Welte56ee6b82011-02-12 18:13:37 +0100[diff] [blame]2367 cur += 3;
2368 memcpy(iwd_v->rev_char, cur, 3);
2369 cur += 3;
2370
Harald Welte563d3162011-02-12 18:11:16 +0100[diff] [blame]2371 DEBUGP(DNM, "\tIWD Type %u Gen %s Rev %s\n", iwd_type,
2372 iwd_v->gen_char, iwd_v->rev_char);
2373 }
2374 }
2375
2376 /* Select the last version for each IWD type */
2377 for (i = 0; i < ARRAY_SIZE(iwd_types); i++) {
2378 struct iwd_type *type = &iwd_types[i];
2379 struct iwd_version *last_v;
2380
2381 if (type->num_vers == 0)
2382 continue;
2383
2384 out_num_types++;
2385
2386 last_v = &type->v[type->num_vers-1];
2387
2388 *out_cur++ = i;
2389 memcpy(out_cur, last_v->gen_char, 3);
2390 out_cur += 3;
2391 memcpy(out_cur, last_v->rev_char, 3);
2392 out_cur += 3;
2393 }
2394
2395 out_buf[0] = out_num_types;
2396
Pablo Neira Ayuso7abecfc2011-08-17 22:43:54 +0200[diff] [blame]2397 return abis_om2k_tx_negot_req_ack(sign_link->trx->bts, &o2h->mo, out_buf, out_cur - out_buf);
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]2398}
2399
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]2400
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]2401/***********************************************************************
2402 * OM2000 Receive Message Handler
2403 ***********************************************************************/
Harald Weltee898ecc2011-03-06 19:26:11 +0100[diff] [blame]2404
Harald Weltee6e83832011-03-05 17:52:09 +0100[diff] [blame]2405static int om2k_rx_nack(struct msgb *msg)
2406{
2407 struct abis_om2k_hdr *o2h = msgb_l2(msg);
2408 uint16_t msg_type = ntohs(o2h->msg_type);
2409 struct tlv_parsed tp;
2410
2411 LOGP(DNM, LOGL_ERROR, "Rx MO=%s %s", om2k_mo_name(&o2h->mo),
2412 get_value_string(om2k_msgcode_vals, msg_type));
2413
Harald Weltee898ecc2011-03-06 19:26:11 +0100[diff] [blame]2414 abis_om2k_msg_tlv_parse(&tp, o2h);
Harald Weltee6e83832011-03-05 17:52:09 +0100[diff] [blame]2415 if (TLVP_PRESENT(&tp, OM2K_DEI_REASON_CODE))
2416 LOGPC(DNM, LOGL_ERROR, ", Reason 0x%02x",
2417 *TLVP_VAL(&tp, OM2K_DEI_REASON_CODE));
2418
2419 if (TLVP_PRESENT(&tp, OM2K_DEI_RESULT_CODE))
2420 LOGPC(DNM, LOGL_ERROR, ", Result %s",
2421 get_value_string(om2k_result_strings,
2422 *TLVP_VAL(&tp, OM2K_DEI_RESULT_CODE)));
2423 LOGPC(DNM, LOGL_ERROR, "\n");
2424
2425 return 0;
2426}
2427
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]2428static int process_mo_state(struct gsm_bts *bts, struct om2k_decoded_msg *odm)
Harald Weltee898ecc2011-03-06 19:26:11 +0100[diff] [blame]2429{
Harald Weltee898ecc2011-03-06 19:26:11 +0100[diff] [blame]2430 uint8_t mo_state;
2431
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]2432 if (!TLVP_PRESENT(&odm->tp, OM2K_DEI_MO_STATE))
Harald Weltee898ecc2011-03-06 19:26:11 +0100[diff] [blame]2433 return -EIO;
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]2434 mo_state = *TLVP_VAL(&odm->tp, OM2K_DEI_MO_STATE);
Harald Weltee898ecc2011-03-06 19:26:11 +0100[diff] [blame]2435
2436 LOGP(DNM, LOGL_DEBUG, "Rx MO=%s %s, MO State: %s\n",
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]2437 om2k_mo_name(&odm->o2h.mo),
2438 get_value_string(om2k_msgcode_vals, odm->msg_type),
Harald Weltee898ecc2011-03-06 19:26:11 +0100[diff] [blame]2439 get_value_string(om2k_mostate_vals, mo_state));
2440
Philippb4ecc1d2016-10-20 13:55:21 +0200[diff] [blame]2441 /* Throw error message in case we see an enable rsponse that does
2442 * not yield an enabled mo-state */
2443 if (odm->msg_type == OM2K_MSGT_ENABLE_RES
2444 && mo_state != OM2K_MO_S_ENABLED) {
2445 LOGP(DNM, LOGL_ERROR,
2446 "Rx MO=%s %s Failed to enable MO State!\n",
2447 om2k_mo_name(&odm->o2h.mo),
2448 get_value_string(om2k_msgcode_vals, odm->msg_type));
2449 }
2450
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]2451 update_mo_state(bts, &odm->o2h.mo, mo_state);
Harald Welteaf9b8102011-03-06 21:20:38 +0100[diff] [blame]2452
Harald Weltee898ecc2011-03-06 19:26:11 +0100[diff] [blame]2453 return 0;
2454}
2455
Philipp8136e4b2016-10-19 10:14:35 +0200[diff] [blame]2456/* Display fault report bits (helper function of display_fault_maps()) */
Philipp38cba5a2016-11-15 19:27:20 +0100[diff] [blame]2457static bool display_fault_bits(const uint8_t *vect, uint16_t len,
Philipp8136e4b2016-10-19 10:14:35 +0200[diff] [blame]2458 uint8_t dei, const struct abis_om2k_mo *mo)
2459{
Philipp38cba5a2016-11-15 19:27:20 +0100[diff] [blame]2460 uint16_t i;
Philipp8136e4b2016-10-19 10:14:35 +0200[diff] [blame]2461 int k;
2462 bool faults_present = false;
2463 int first = 1;
2464 char string[255];
2465
2466 /* Check if errors are present at all */
2467 for (i = 0; i < len; i++)
2468 if (vect[i])
2469 faults_present = true;
2470 if (!faults_present)
2471 return false;
2472
2473 sprintf(string, "Fault Report: %s (",
2474 get_value_string(om2k_attr_vals, dei));
2475
2476 for (i = 0; i < len; i++) {
2477 for (k = 0; k < 8; k++) {
2478 if ((vect[i] >> k) & 1) {
2479 if (!first)
2480 sprintf(string + strlen(string), ",");
2481 sprintf(string + strlen(string), "%d", k + i*8);
2482 first = 0;
2483 }
2484 }
2485 }
2486
2487 sprintf(string + strlen(string), ")\n");
2488 DEBUGP(DNM, "Rx MO=%s %s", om2k_mo_name(mo), string);
2489
2490 return true;
2491}
2492
2493/* Display fault report maps */
2494static void display_fault_maps(const uint8_t *src, unsigned int src_len,
2495 const struct abis_om2k_mo *mo)
2496{
2497 uint8_t tag;
2498 uint16_t tag_len;
2499 const uint8_t *val;
2500 int src_pos = 0;
2501 int rc;
2502 int tlv_count = 0;
2503 uint16_t msg_code;
2504 bool faults_present = false;
2505
2506 /* Chop off header */
2507 src+=4;
2508 src_len-=4;
2509
2510 /* Check message type */
2511 msg_code = (*src & 0xff) << 8;
2512 src++;
2513 src_len--;
2514 msg_code |= (*src & 0xff);
2515 src++;
2516 src_len--;
2517 if (msg_code != OM2K_MSGT_FAULT_REP) {
2518 LOGP(DNM, LOGL_ERROR, "Rx MO=%s Fault report: invalid message code!\n",
2519 om2k_mo_name(mo));
2520 return;
2521 }
2522
2523 /* Chop off mo-interface */
2524 src += 4;
2525 src_len -= 4;
2526
2527 /* Iterate over each TLV element */
2528 while (1) {
2529
2530 /* Bail if an the maximum number of TLV fields
2531 * have been parsed */
2532 if (tlv_count >= 11) {
2533 LOGP(DNM, LOGL_ERROR,
2534 "Rx MO=%s Fault Report: too many tlv elements!\n",
2535 om2k_mo_name(mo));
2536 return;
2537 }
2538
2539 /* Parse TLV field */
2540 rc = tlv_parse_one(&tag, &tag_len, &val, &om2k_att_tlvdef,
2541 src + src_pos, src_len - src_pos);
2542 if (rc > 0)
2543 src_pos += rc;
2544 else {
2545 LOGP(DNM, LOGL_ERROR,
2546 "Rx MO=%s Fault Report: invalid tlv element!\n",
2547 om2k_mo_name(mo));
2548 return;
2549 }
2550
2551 switch (tag) {
2552 case OM2K_DEI_INT_FAULT_MAP_1A:
2553 case OM2K_DEI_INT_FAULT_MAP_1B:
2554 case OM2K_DEI_INT_FAULT_MAP_2A:
2555 case OM2K_DEI_EXT_COND_MAP_1:
2556 case OM2K_DEI_EXT_COND_MAP_2:
2557 case OM2K_DEI_REPL_UNIT_MAP:
2558 case OM2K_DEI_INT_FAULT_MAP_2A_EXT:
2559 case OM2K_DEI_EXT_COND_MAP_2_EXT:
2560 case OM2K_DEI_REPL_UNIT_MAP_EXT:
2561 faults_present |= display_fault_bits(val, tag_len,
2562 tag, mo);
2563 break;
2564 }
2565
2566 /* Stop when no further TLV elements can be expected */
2567 if (src_len - src_pos < 2)
2568 break;
2569
2570 tlv_count++;
2571 }
2572
2573 if (!faults_present) {
2574 DEBUGP(DNM, "Rx MO=%s Fault Report: All faults ceased!\n",
2575 om2k_mo_name(mo));
2576 }
2577}
2578
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]2579int abis_om2k_rcvmsg(struct msgb *msg)
2580{
Pablo Neira Ayuso7abecfc2011-08-17 22:43:54 +0200[diff] [blame]2581 struct e1inp_sign_link *sign_link = (struct e1inp_sign_link *)msg->dst;
2582 struct gsm_bts *bts = sign_link->trx->bts;
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]2583 struct abis_om2k_hdr *o2h = msgb_l2(msg);
2584 struct abis_om_hdr *oh = &o2h->om;
Harald Weltebc867d92011-02-12 13:09:38 +0100[diff] [blame]2585 uint16_t msg_type = ntohs(o2h->msg_type);
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]2586 struct om2k_decoded_msg odm;
2587 struct om2k_mo *mo;
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]2588 int rc = 0;
2589
2590 /* Various consistency checks */
2591 if (oh->placement != ABIS_OM_PLACEMENT_ONLY) {
2592 LOGP(DNM, LOGL_ERROR, "ABIS OML placement 0x%x not supported\n",
2593 oh->placement);
2594 if (oh->placement != ABIS_OM_PLACEMENT_FIRST)
2595 return -EINVAL;
2596 }
2597 if (oh->sequence != 0) {
2598 LOGP(DNM, LOGL_ERROR, "ABIS OML sequence 0x%x != 0x00\n",
2599 oh->sequence);
2600 return -EINVAL;
2601 }
2602
2603 msg->l3h = (unsigned char *)o2h + sizeof(*o2h);
2604
2605 if (oh->mdisc != ABIS_OM_MDISC_FOM) {
2606 LOGP(DNM, LOGL_ERROR, "unknown ABIS OM2000 message discriminator 0x%x\n",
2607 oh->mdisc);
2608 return -EINVAL;
2609 }
2610
Harald Welte73541072011-02-12 13:44:14 +0100[diff] [blame]2611 DEBUGP(DNM, "Rx MO=%s %s (%s)\n", om2k_mo_name(&o2h->mo),
Harald Weltebc867d92011-02-12 13:09:38 +0100[diff] [blame]2612 get_value_string(om2k_msgcode_vals, msg_type),
Pablo Neira Ayusoc0d17f22011-05-07 12:12:48 +0200[diff] [blame]2613 osmo_hexdump(msg->l2h, msgb_l2len(msg)));
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]2614
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]2615 om2k_decode_msg(&odm, msg);
2616
2617 process_mo_state(bts, &odm);
2618
Harald Weltebc867d92011-02-12 13:09:38 +0100[diff] [blame]2619 switch (msg_type) {
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]2620 case OM2K_MSGT_CAL_TIME_REQ:
2621 rc = abis_om2k_cal_time_resp(bts);
2622 break;
2623 case OM2K_MSGT_FAULT_REP:
Philipp8136e4b2016-10-19 10:14:35 +0200[diff] [blame]2624 display_fault_maps(msg->l2h, msgb_l2len(msg), &o2h->mo);
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]2625 rc = abis_om2k_tx_simple(bts, &o2h->mo, OM2K_MSGT_FAULT_REP_ACK);
2626 break;
2627 case OM2K_MSGT_NEGOT_REQ:
2628 rc = om2k_rx_negot_req(msg);
2629 break;
2630 case OM2K_MSGT_START_RES:
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]2631 /* common processing here */
2632 rc = abis_om2k_tx_simple(bts, &o2h->mo, OM2K_MSGT_START_RES_ACK);
2633 /* below we dispatch into MO */
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]2634 break;
2635 case OM2K_MSGT_IS_CONF_RES:
2636 rc = abis_om2k_tx_simple(bts, &o2h->mo, OM2K_MSGT_IS_CONF_RES_ACK);
2637 break;
Harald Weltefdb71942011-02-14 15:31:43 +0100[diff] [blame]2638 case OM2K_MSGT_CON_CONF_RES:
2639 rc = abis_om2k_tx_simple(bts, &o2h->mo, OM2K_MSGT_CON_CONF_RES_ACK);
2640 break;
Harald Weltea0ce3492011-03-05 14:13:14 +0100[diff] [blame]2641 case OM2K_MSGT_TX_CONF_RES:
2642 rc = abis_om2k_tx_simple(bts, &o2h->mo, OM2K_MSGT_TX_CONF_RES_ACK);
2643 break;
2644 case OM2K_MSGT_RX_CONF_RES:
2645 rc = abis_om2k_tx_simple(bts, &o2h->mo, OM2K_MSGT_RX_CONF_RES_ACK);
2646 break;
2647 case OM2K_MSGT_TS_CONF_RES:
2648 rc = abis_om2k_tx_simple(bts, &o2h->mo, OM2K_MSGT_TS_CONF_RES_ACK);
2649 break;
Harald Weltef9cf9612011-03-05 14:36:47 +0100[diff] [blame]2650 case OM2K_MSGT_TF_CONF_RES:
2651 rc = abis_om2k_tx_simple(bts, &o2h->mo, OM2K_MSGT_TF_CONF_RES_ACK);
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]2652 break;
Harald Welteb3d70fd2011-02-13 12:43:44 +0100[diff] [blame]2653 case OM2K_MSGT_ENABLE_RES:
2654 rc = abis_om2k_tx_simple(bts, &o2h->mo, OM2K_MSGT_ENABLE_RES_ACK);
2655 break;
Harald Weltefdb71942011-02-14 15:31:43 +0100[diff] [blame]2656 case OM2K_MSGT_DISABLE_RES:
2657 rc = abis_om2k_tx_simple(bts, &o2h->mo, OM2K_MSGT_DISABLE_RES_ACK);
2658 break;
2659 case OM2K_MSGT_TEST_RES:
2660 rc = abis_om2k_tx_simple(bts, &o2h->mo, OM2K_MSGT_TEST_RES_ACK);
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]2661 break;
root45799782016-10-15 21:24:57 +0200[diff] [blame]2662 case OM2K_MSGT_CAPA_RES:
2663 rc = abis_om2k_tx_simple(bts, &o2h->mo, OM2K_MSGT_CAPA_RES_ACK);
2664 break;
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]2665 /* ERrors */
Harald Weltee6e83832011-03-05 17:52:09 +0100[diff] [blame]2666 case OM2K_MSGT_START_REQ_REJ:
Harald Welte3ede7232011-03-05 17:58:13 +0100[diff] [blame]2667 case OM2K_MSGT_CONNECT_REJ:
Harald Welteaff63bc2011-03-05 19:42:16 +0100[diff] [blame]2668 case OM2K_MSGT_OP_INFO_REJ:
Harald Welte3ede7232011-03-05 17:58:13 +0100[diff] [blame]2669 case OM2K_MSGT_DISCONNECT_REJ:
Harald Welteaff63bc2011-03-05 19:42:16 +0100[diff] [blame]2670 case OM2K_MSGT_TEST_REQ_REJ:
Harald Weltee6e83832011-03-05 17:52:09 +0100[diff] [blame]2671 case OM2K_MSGT_CON_CONF_REQ_REJ:
2672 case OM2K_MSGT_IS_CONF_REQ_REJ:
2673 case OM2K_MSGT_TX_CONF_REQ_REJ:
2674 case OM2K_MSGT_RX_CONF_REQ_REJ:
2675 case OM2K_MSGT_TS_CONF_REQ_REJ:
2676 case OM2K_MSGT_TF_CONF_REQ_REJ:
2677 case OM2K_MSGT_ENABLE_REQ_REJ:
2678 case OM2K_MSGT_ALARM_STATUS_REQ_REJ:
2679 case OM2K_MSGT_DISABLE_REQ_REJ:
2680 rc = om2k_rx_nack(msg);
2681 break;
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]2682 }
2683
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]2684 /* Resolve the MO for this message */
2685 mo = get_om2k_mo(bts, &o2h->mo);
2686 if (!mo) {
2687 LOGP(DNM, LOGL_ERROR, "Couldn't resolve MO for OM2K msg "
2688 "%s: %s\n", get_value_string(om2k_msgcode_vals, msg_type),
2689 msgb_hexdump(msg));
2690 return 0;
2691 }
2692
2693 /* Dispatch message to that MO */
2694 om2k_mo_fsm_recvmsg(bts, mo, &odm);
2695
Harald Welte9a311ec2011-02-12 12:33:06 +0100[diff] [blame]2696 msgb_free(msg);
2697 return rc;
2698}
Harald Welte591e1d72016-07-09 22:20:57 +0200[diff] [blame]2699
2700static void om2k_mo_init(struct om2k_mo *mo, uint8_t class,
2701 uint8_t bts_nr, uint8_t assoc_so, uint8_t inst)
2702{
2703 mo->addr.class = class;
2704 mo->addr.bts = bts_nr;
2705 mo->addr.assoc_so = assoc_so;
2706 mo->addr.inst = inst;
2707}
2708
2709/* initialize the OM2K_MO members of gsm_bts_trx and its timeslots */
2710void abis_om2k_trx_init(struct gsm_bts_trx *trx)
2711{
2712 struct gsm_bts *bts = trx->bts;
2713 unsigned int i;
2714
2715 OSMO_ASSERT(bts->type == GSM_BTS_TYPE_RBS2000);
2716
2717 om2k_mo_init(&trx->rbs2000.trxc.om2k_mo, OM2K_MO_CLS_TRXC,
2718 bts->nr, 255, trx->nr);
2719 om2k_mo_init(&trx->rbs2000.tx.om2k_mo, OM2K_MO_CLS_TX,
2720 bts->nr, 255, trx->nr);
2721 om2k_mo_init(&trx->rbs2000.rx.om2k_mo, OM2K_MO_CLS_RX,
2722 bts->nr, 255, trx->nr);
2723
2724 for (i = 0; i < ARRAY_SIZE(trx->ts); i++) {
2725 om2k_mo_init(&trx->ts[i].rbs2000.om2k_mo, OM2K_MO_CLS_TS,
2726 bts->nr, trx->nr, i);
2727 }
2728}
2729
2730/* initialize the OM2K_MO members of gsm_bts */
2731void abis_om2k_bts_init(struct gsm_bts *bts)
2732{
2733 OSMO_ASSERT(bts->type == GSM_BTS_TYPE_RBS2000);
2734
2735 om2k_mo_init(&bts->rbs2000.cf.om2k_mo, OM2K_MO_CLS_CF,
2736 bts->nr, 0xFF, 0);
2737 om2k_mo_init(&bts->rbs2000.is.om2k_mo, OM2K_MO_CLS_IS,
2738 bts->nr, 0xFF, 0);
2739 om2k_mo_init(&bts->rbs2000.con.om2k_mo, OM2K_MO_CLS_CON,
2740 bts->nr, 0xFF, 0);
2741 om2k_mo_init(&bts->rbs2000.dp.om2k_mo, OM2K_MO_CLS_DP,
2742 bts->nr, 0xFF, 0);
2743 om2k_mo_init(&bts->rbs2000.tf.om2k_mo, OM2K_MO_CLS_TF,
2744 bts->nr, 0xFF, 0);
2745}
2746
2747static __attribute__((constructor)) void abis_om2k_init(void)
2748{
2749 osmo_fsm_register(&om2k_mo_fsm);
2750 osmo_fsm_register(&om2k_bts_fsm);
2751 osmo_fsm_register(&om2k_trx_fsm);
2752}