| Harald Welte | da02f55 | 2012-01-14 18:18:31 +0100 | [diff] [blame] | 1 | #ifndef _IDT82_REGS_H |
| 2 | #define _IDT82_REGS_H |
| 3 | |
| 4 | /* Section 4.1 of Data Sheet */ |
| 5 | enum idt82v2081_reg { |
| 6 | IDT_REG_ID, /* control */ |
| 7 | IDT_REG_RST, |
| 8 | IDT_REG_GCF, |
| 9 | IDT_REG_TERM, |
| 10 | IDT_REG_JACF, |
| 11 | IDT_REG_TCF0, /* Tx path control */ |
| 12 | IDT_REG_TCF1, |
| 13 | IDT_REG_TCF2, |
| 14 | IDT_REG_TCF3, |
| 15 | IDT_REG_TCF4, |
| 16 | IDT_REG_RCF0, /* Rx path control */ |
| 17 | IDT_REG_RCF1, |
| 18 | IDT_REG_RCF2, |
| 19 | IDT_REG_MAINT0, /* Net Diag Ctrl */ |
| 20 | IDT_REG_MAINT1, |
| 21 | IDT_REG_MAINT2, |
| 22 | IDT_REG_MAINT3, |
| 23 | IDT_REG_MAINT4, |
| 24 | IDT_REG_MAINT5, |
| 25 | IDT_REG_MAINT6, |
| 26 | IDT_REG_INTM0, /* Interrupt Control */ |
| 27 | IDT_REG_INTM1, |
| 28 | IDT_REG_INTES, |
| 29 | IDT_REG_STAT0, /* Line Status */ |
| 30 | IDT_REG_STAT1, |
| 31 | IDT_REG_INTS0, /* Interrupt Status */ |
| 32 | IDT_REG_INTS1, |
| 33 | IDT_REG_CNT0, /* Counter */ |
| 34 | IDT_REG_CNT1, |
| 35 | }; |
| 36 | |
| 37 | #define IDT_GCF_T1E1_E1 (0 << 2) |
| 38 | #define IDT_GCF_T1E1_T1 (1 << 2) |
| 39 | #define IDT_GCF_T1E1_MASK (1 << 2) |
| 40 | |
| 41 | #define IDT_TERM_T_SHIFT 3 |
| 42 | #define IDT_TERM_T_MASK (7 << IDT_TERM_T_SHIFT) |
| 43 | #define IDT_TERM_R_SHIFT 0 |
| 44 | #define IDT_TERM_R_MASK (7 << IDT_TERM_R_SHIFT) |
| 45 | |
| 46 | #define IDT_TCF1_PULS_MASK 0xF |
| 47 | |
| 48 | #define IDT_TCF2_SCAL_MASK 0x3F |
| 49 | |
| 50 | #define IDT_RCF2_MG_MASK 3 |
| 51 | #define IDT_RCF2_UPDW_SHIFT 2 |
| 52 | #define IDT_RCF2_UPDW_MASK (3 << IDT_TERM_INT_75) |
| 53 | #define IDT_RCF2_SLICE_SHIFT 4 |
| 54 | #define IDT_RCF2_SLICE_MASK (3 << IDT_RCF2_SLICE_SHIFT) |
| 55 | |
| 56 | #define IDT_INTM0_EQ (1 << 7) /* equalizer out of range */ |
| 57 | #define IDT_INTM0_IBLBA (1 << 6) /* in-band LB act detect */ |
| 58 | #define IDT_INTM0_IBLBD (1 << 5) /* in-band LB deact detect */ |
| 59 | #define IDT_INTM0_PRBS (1 << 4) /* prbs sync signal detect */ |
| 60 | #define IDT_INTM0_TCLK (1 << 3) /* tclk loss */ |
| 61 | #define IDT_INTM0_DF (1 << 2) /* driver failure */ |
| 62 | #define IDT_INTM0_AIS (1 << 1) /* Alarm Indication Signal */ |
| 63 | #define IDT_INTM0_LOS (1 << 0) /* Loss Of Signal */ |
| 64 | |
| 65 | #define IDT_INTM1_DAC_OV (1 << 7) /* DAC arithmetic overflow */ |
| 66 | #define IDT_INTM1_JA_OV (1 << 6) /* JA overflow */ |
| 67 | #define IDT_INTM1_JA_UD (1 << 5) /* JA underflow */ |
| 68 | #define IDT_INTM1_ERR (1 << 4) /* PRBS/QRBS logic error detect */ |
| 69 | #define IDT_INTM1_EXZ (1 << 3) /* Receive excess zeros */ |
| 70 | #define IDT_INTM1_CV (1 << 2) /* Receive error */ |
| 71 | #define IDT_INTM1_TIMER (1 << 1) /* One second timer expiration */ |
| 72 | #define IDT_INTM1_CNT (1 << 0) /* Counter overflow */ |
| 73 | |
| 74 | /* STAT0 == INTES == INTS0 == INTM0 */ |
| 75 | |
| 76 | /* INTS1 == INTM1 */ |
| 77 | |
| 78 | #define IDT_STAT1_RLP (1 << 5) |
| 79 | #define IDT_STAT1_ATT_MASK 0x1F |
| 80 | |
| 81 | #endif /* _IDT82_REGS_H */ |