| Harald Welte | 2f4c472 | 2011-12-24 00:36:06 +0100 | [diff] [blame] | 1 | osmo-e1-xcvr -- (C) 2011 by Harald Welte <laforge@gnumonks.org> |
| 2 | ====================================================================== |
| 3 | |
| 4 | This is a simple hardware project that aims to generate a reusable module |
| 5 | for interfacing E1/T1/J1 lines from various custom FPGA/CPLD/microcontroller |
| 6 | projects. |
| 7 | |
| 8 | The board contains tranformers, the analog circuitry, the LIU (line interface |
| 9 | unit), an oscillator as well as an integrated transceiver chip. |
| 10 | |
| 11 | It exposes the control interface (SPI) as well as the decoded synchronous |
| 12 | Rx/Tx bitstreams each on a 2x5pin header. |
| 13 | |
| 14 | Framer, Multiplexe,r HDLC decoder or anything like that is out-of-scope for |
| 15 | now. The idea relaly is to provide an interface as low-level as possible. |
| 16 | |
| 17 | One of the ideas is to create a "soft E1" interface, where the Rx/Tx bitstreams |
| 18 | are interfaced with the SSC of an AT91SAM3S and subsequently passed into a PC |
| 19 | via USB. The 2Mbps signal is very low-bandwidth, so that a pure software |
| 20 | implementation should be absolutely no problem for todays computing power. |
| 21 | |
| 22 | == Status == |
| 23 | |
| 24 | The project is in design phase. Initial design has finished, but needs to be |
| 25 | reviewed. First prototype PCBs will be expected in January 2012 |
| 26 | |
| 27 | == Hardware Documentation == |
| 28 | |
| 29 | === JP2: TDM interface === |
| 30 | |
| 31 | JP2 contains the serial TDM bitstream + clock for Rx and Tx direction. The signals are |
| 32 | ||Pin||Name||Description|| |
| 33 | ||1||GND||Ground|| |
| 34 | ||2||nRST||low-active reset line, uC can reset the transceiver by pulling this low|| |
| 35 | ||3||NC|||| |
| 36 | ||4||LOS||Loss of Signal|| |
| 37 | ||5||TDN||Transmit Data Negative|| |
| 38 | ||6||RCLK||Receive Clock|| |
| 39 | ||7||TD/TDP||Transmit Data / Transmit Data Positive|| |
| 40 | ||8||RD/RDP||Receive Data / Receive Data Positive|| |
| 41 | ||9||TCLK||Transmitter Clock. Depending on JP9, this is an input into the board, or an output |
| 42 | ||10||RDN/CV||Receive Data Negative / Code Violation|| |
| 43 | |
| 44 | === JP1: SPI control === |
| 45 | |
| 46 | This is how the external microcontroller can control the transceiver chip. |
| 47 | |
| 48 | ||Pin||Name||Description|| |
| 49 | ||1||GND||Ground|| |
| 50 | ||2||NC||Not connected|| |
| 51 | ||3||NC||Not connected|| |
| 52 | ||4||nINT||low-active interrupt output, when transceiver wants to interrupt uC"" |
| 53 | ||5||NC||Not connected|| |
| 54 | ||6||nCS||low-active chip-select of the SPI|| |
| 55 | ||7||NC||Not connected|| |
| 56 | ||8||SDO||Serial Data Out (MISO)|| |
| 57 | ||9||SDI||Serial Data In (MOSI)|| |
| 58 | ||10||SCLK||Serial Clock|| |
| 59 | |
| 60 | === JP9 === |
| 61 | |
| 62 | JP10 switches the master clock (MCLK) of the transceiver between two on-board oscillators |
| 63 | of 2.048 MHz and 1.544 MHz. This is required for selecting between E1 or T1/J1 mode. |
| 64 | |
| 65 | ||1-2||2.048 MHz (E1) mode|| |
| 66 | ||2-3||1.544 MHz (T1/J1) mode|| |
| 67 | |
| 68 | === JP10 === |
| 69 | |
| 70 | This jumper decides if the 2.048/1.544 MHz MCLK should also be used as TDM Transmit Clock. |
| 71 | |
| 72 | ||closed||use MCLK as TCLK source, TCLK pin on JP2 is output|| |
| 73 | ||open||external circuit provides TCLK on JP2|| |
| 74 | |
| 75 | === JP3 + JP4 === |
| 76 | |
| 77 | JP3+JP4 can be used to select which of the pins on the RJ45 connector should be used: |
| 78 | |
| 79 | They should either all be in setting 1-2, or all be in 2-3, but never mixed. |
| 80 | |
| 81 | ||1-2||Use pins 3+6 as one pair|| |
| 82 | ||2-3||Use pins 1+2 as one pair|| |
| 83 | |
| 84 | === JP5, JP6, JP7, JP8 == |
| 85 | |
| 86 | Those select between TE mode and NT mode. |
| 87 | |
| 88 | They should either all be in setting 1-2, or all be in 2-3, but never mixed. |
| 89 | |