| Sylvain Munaut | 21b03ba | 2020-09-14 10:01:45 +0200 | [diff] [blame] | 1 | /* |
| 2 | * boot.S |
| 3 | * |
| 4 | * SPI boot code |
| 5 | * |
| 6 | * Copyright (C) 2020 Sylvain Munaut <tnt@246tNt.com> |
| 7 | * SPDX-License-Identifier: MIT |
| 8 | */ |
| 9 | |
| 10 | #ifndef APP_FLASH_ADDR |
| 11 | #define APP_FLASH_ADDR 0x00100000 |
| 12 | #endif |
| 13 | |
| 14 | #ifndef APP_SRAM_ADDR |
| 15 | #define APP_SRAM_ADDR 0x00020000 |
| 16 | #endif |
| 17 | |
| 18 | #ifndef APP_SIZE |
| 19 | #define APP_SIZE 0x00010000 |
| 20 | #endif |
| 21 | |
| 22 | .section .text.start |
| 23 | .global _start |
| 24 | _start: |
| 25 | // SPI init |
| 26 | jal spi_init |
| 27 | |
| 28 | // Read from flash to SRAM |
| 29 | li a0, APP_SRAM_ADDR |
| 30 | li a1, APP_SIZE |
| 31 | li a2, APP_FLASH_ADDR |
| 32 | jal spi_flash_read |
| 33 | |
| 34 | // Setup reboot code |
| 35 | li t0, 0x0002006f |
| 36 | sw t0, 0(zero) |
| 37 | |
| 38 | // Jump to main code |
| 39 | j APP_SRAM_ADDR |
| 40 | |
| 41 | |
| 42 | .equ SPI_BASE, 0x80000000 |
| 43 | .equ SPICR0, 4 * 0x08 |
| 44 | .equ SPICR1, 4 * 0x09 |
| 45 | .equ SPICR2, 4 * 0x0a |
| 46 | .equ SPIBR, 4 * 0x0b |
| 47 | .equ SPISR, 4 * 0x0c |
| 48 | .equ SPITXDR, 4 * 0x0d |
| 49 | .equ SPIRXDR, 4 * 0x0e |
| 50 | .equ SPICSR, 4 * 0x0f |
| 51 | |
| 52 | |
| 53 | spi_init: |
| 54 | li a0, SPI_BASE |
| 55 | |
| 56 | li a1, 0xff |
| 57 | sw a1, SPICR0(a0) |
| 58 | |
| 59 | li a1, 0x80 |
| 60 | sw a1, SPICR1(a0) |
| 61 | |
| 62 | li a1, 0xc0 |
| 63 | sw a1, SPICR2(a0) |
| 64 | |
| 65 | li a1, 0x03 |
| 66 | sw a1, SPIBR(a0) |
| 67 | |
| 68 | li a1, 0x0f |
| 69 | sw a1, SPICSR(a0) |
| 70 | |
| 71 | ret |
| 72 | |
| 73 | |
| 74 | // Params: |
| 75 | // a0 - destination pointer |
| 76 | // a1 - length (bytes) |
| 77 | // a2 - flash offset |
| 78 | // |
| 79 | |
| 80 | spi_flash_read: |
| 81 | // Save params |
| 82 | mv s0, a0 |
| 83 | mv s1, a1 |
| 84 | mv s2, ra |
| 85 | |
| 86 | // Setup CS |
| 87 | li t0, SPI_BASE |
| 88 | li t1, 0x0e |
| 89 | sw t1, SPICSR(t0) |
| 90 | |
| 91 | // Send command |
| 92 | li a0, 0x03 |
| 93 | jal _spi_do_one |
| 94 | |
| 95 | srli a0, a2, 16 |
| 96 | and a0, a0, 0xff |
| 97 | jal _spi_do_one |
| 98 | |
| 99 | srli a0, a2, 8 |
| 100 | and a0, a0, 0xff |
| 101 | jal _spi_do_one |
| 102 | |
| 103 | and a0, a2, 0xff |
| 104 | jal _spi_do_one |
| 105 | |
| 106 | // Read loop |
| 107 | _spi_loop: |
| 108 | li a0, 0x00 |
| 109 | jal _spi_do_one |
| 110 | sb a0, 0(s0) |
| 111 | addi s0, s0, 1 |
| 112 | addi s1, s1, -1 |
| 113 | bne s1, zero, _spi_loop |
| 114 | |
| 115 | // Release CS |
| 116 | li t0, SPI_BASE |
| 117 | li t1, 0x0f |
| 118 | sw t1, SPICSR(t0) |
| 119 | |
| 120 | // Done |
| 121 | jr s2 |
| 122 | |
| 123 | |
| 124 | // Params: a0 - Data to TX |
| 125 | // Returns: a0 - RX data |
| 126 | // Clobbers t0, t1 |
| 127 | _spi_do_one: |
| 128 | li t0, SPI_BASE |
| 129 | li t1, 0x08 |
| 130 | |
| 131 | // Write TX data |
| 132 | sw a0, SPITXDR(t0) |
| 133 | |
| 134 | // Wait for RXRDY |
| 135 | 1: |
| 136 | lw a0, SPISR(t0) |
| 137 | and a0, a0, t1 |
| 138 | bne a0, t1, 1b |
| 139 | |
| 140 | // Read RX data |
| 141 | lw a0, SPIRXDR(t0) |
| 142 | |
| 143 | // Done |
| 144 | ret |