Sylvain Munaut | 26bc465 | 2020-09-14 10:19:49 +0200 | [diff] [blame] | 1 | /* |
| 2 | * spi.c |
| 3 | * |
| 4 | * Copyright (C) 2019-2020 Sylvain Munaut <tnt@246tNt.com> |
| 5 | * SPDX-License-Identifier: LGPL-3.0-or-later |
| 6 | */ |
| 7 | |
| 8 | #include <stdbool.h> |
| 9 | #include <stdint.h> |
| 10 | |
| 11 | #include "config.h" |
| 12 | #include "spi.h" |
| 13 | |
| 14 | |
| 15 | struct spi { |
| 16 | uint32_t _rsvd0[6]; |
| 17 | uint32_t irq; /* 0110 - SPIIRQ - Interrupt Status Register */ |
| 18 | uint32_t irqen; /* 0111 - SPIIRQEN - Interrupt Control Register */ |
| 19 | uint32_t cr0; /* 1000 - CR0 - Control Register 0 */ |
| 20 | uint32_t cr1; /* 1001 - CR1 - Control Register 1 */ |
| 21 | uint32_t cr2; /* 1010 - CR2 - Control Register 2 */ |
| 22 | uint32_t br; /* 1011 - BR - Baud Rate Register */ |
| 23 | uint32_t sr; /* 1100 - SR - Status Register */ |
| 24 | uint32_t txdr; /* 1101 - TXDR - Transmit Data Register */ |
| 25 | uint32_t rxdr; /* 1110 - RXDR - Receive Data Register */ |
| 26 | uint32_t csr; /* 1111 - CSR - Chip Select Register */ |
| 27 | } __attribute__((packed,aligned(4))); |
| 28 | |
| 29 | #define SPI_CR0_TIDLE(xcnt) (((xcnt) & 3) << 6) |
| 30 | #define SPI_CR0_TTRAIL(xcnt) (((xcnt) & 7) << 3) |
| 31 | #define SPI_CR0_TLEAD(xcnt) (((xcnt) & 7) << 0) |
| 32 | |
| 33 | #define SPI_CR1_ENABLE (1 << 7) |
| 34 | #define SPI_CR1_WKUPEN_USER (1 << 6) |
| 35 | #define SPI_CR1_TXEDGE (1 << 4) |
| 36 | |
| 37 | #define SPI_CR2_MASTER (1 << 7) |
| 38 | #define SPI_CR2_MCSH (1 << 6) |
| 39 | #define SPI_CR2_SDBRE (1 << 5) |
| 40 | #define SPI_CR2_CPOL (1 << 2) |
| 41 | #define SPI_CR2_CPHA (1 << 1) |
| 42 | #define SPI_CR2_LSBF (1 << 0) |
| 43 | |
| 44 | #define SPI_SR_TIP (1 << 7) |
| 45 | #define SPI_SR_BUSY (1 << 6) |
| 46 | #define SPI_SR_TRDY (1 << 4) |
| 47 | #define SPI_SR_RRDY (1 << 3) |
| 48 | #define SPI_SR_TOE (1 << 2) |
| 49 | #define SPI_SR_ROE (1 << 1) |
| 50 | #define SPI_SR_MDF (1 << 0) |
| 51 | |
| 52 | |
| 53 | static volatile struct spi * const spi_regs[] = { |
| 54 | (void*)(SPI_FLASH_BASE), |
| 55 | #ifdef BOARD_E1_TRACER |
| 56 | (void*)(SPI_LIU_BASE), |
| 57 | #endif |
| 58 | }; |
| 59 | |
| 60 | |
| 61 | void |
| 62 | spi_init(void) |
| 63 | { |
| 64 | /* Channel 0: Flash */ |
| 65 | spi_regs[0]->cr0 = SPI_CR0_TIDLE(3) | |
| 66 | SPI_CR0_TTRAIL(7) | |
| 67 | SPI_CR0_TLEAD(7); |
| 68 | |
| 69 | spi_regs[0]->cr1 = SPI_CR1_ENABLE; |
| 70 | spi_regs[0]->cr2 = SPI_CR2_MASTER | SPI_CR2_MCSH; |
| 71 | spi_regs[0]->br = 3; |
| 72 | spi_regs[0]->csr = 0xf; |
| 73 | |
| 74 | #ifdef BOARD_E1_TRACER |
| 75 | /* Channel 1: LIU */ |
| 76 | spi_regs[1]->cr0 = SPI_CR0_TIDLE(3) | |
| 77 | SPI_CR0_TTRAIL(7) | |
| 78 | SPI_CR0_TLEAD(7); |
| 79 | spi_regs[1]->cr1 = SPI_CR1_ENABLE | SPI_CR1_TXEDGE; |
| 80 | spi_regs[1]->cr2 = SPI_CR2_MASTER | SPI_CR2_LSBF | SPI_CR2_MCSH | SPI_CR2_CPHA; |
| 81 | spi_regs[1]->br = 3; |
| 82 | spi_regs[1]->csr = 0xf; |
| 83 | #endif |
| 84 | } |
| 85 | |
| 86 | void |
| 87 | spi_xfer(unsigned cs, const struct spi_xfer_chunk *xfer, unsigned n) |
| 88 | { |
Sylvain Munaut | bc59615 | 2020-10-28 21:59:29 +0100 | [diff] [blame] | 89 | uint8_t rxd; |
Sylvain Munaut | 26bc465 | 2020-09-14 10:19:49 +0200 | [diff] [blame] | 90 | unsigned chan = (cs >> 2); |
| 91 | cs &= 3; |
| 92 | |
| 93 | /* Setup CS */ |
Sylvain Munaut | 26bc465 | 2020-09-14 10:19:49 +0200 | [diff] [blame] | 94 | spi_regs[chan]->csr = 0xf ^ (1 << cs); |
| 95 | |
| 96 | /* Run the chunks */ |
| 97 | while (n--) { |
Sylvain Munaut | de20fb7 | 2020-10-29 13:24:50 +0100 | [diff] [blame] | 98 | for (unsigned int i=0; i<xfer->len; i++) |
Sylvain Munaut | 26bc465 | 2020-09-14 10:19:49 +0200 | [diff] [blame] | 99 | { |
| 100 | spi_regs[chan]->txdr = xfer->write ? xfer->data[i] : 0x00; |
| 101 | while (!(spi_regs[chan]->sr & SPI_SR_RRDY)); |
Sylvain Munaut | bc59615 | 2020-10-28 21:59:29 +0100 | [diff] [blame] | 102 | rxd = spi_regs[chan]->rxdr; |
Sylvain Munaut | 26bc465 | 2020-09-14 10:19:49 +0200 | [diff] [blame] | 103 | if (xfer->read) |
Sylvain Munaut | bc59615 | 2020-10-28 21:59:29 +0100 | [diff] [blame] | 104 | xfer->data[i] = rxd; |
Sylvain Munaut | 26bc465 | 2020-09-14 10:19:49 +0200 | [diff] [blame] | 105 | } |
| 106 | xfer++; |
| 107 | } |
| 108 | |
| 109 | /* Clear CS */ |
Sylvain Munaut | 26bc465 | 2020-09-14 10:19:49 +0200 | [diff] [blame] | 110 | spi_regs[chan]->csr = 0xf; |
| 111 | } |
| 112 | |
| 113 | |
| 114 | #define FLASH_CMD_DEEP_POWER_DOWN 0xb9 |
| 115 | #define FLASH_CMD_WAKE_UP 0xab |
| 116 | #define FLASH_CMD_WRITE_ENABLE 0x06 |
| 117 | #define FLASH_CMD_WRITE_ENABLE_VOLATILE 0x50 |
| 118 | #define FLASH_CMD_WRITE_DISABLE 0x04 |
| 119 | |
| 120 | #define FLASH_CMD_READ_MANUF_ID 0x9f |
| 121 | #define FLASH_CMD_READ_UNIQUE_ID 0x4b |
| 122 | |
| 123 | #define FLASH_CMD_READ_SR1 0x05 |
| 124 | #define FLASH_CMD_WRITE_SR1 0x01 |
| 125 | |
| 126 | #define FLASH_CMD_READ_DATA 0x03 |
| 127 | #define FLASH_CMD_PAGE_PROGRAM 0x02 |
| 128 | #define FLASH_CMD_CHIP_ERASE 0x60 |
| 129 | #define FLASH_CMD_SECTOR_ERASE 0x20 |
| 130 | |
| 131 | void |
| 132 | flash_cmd(uint8_t cmd) |
| 133 | { |
| 134 | struct spi_xfer_chunk xfer[1] = { |
| 135 | { .data = (void*)&cmd, .len = 1, .read = false, .write = true, }, |
| 136 | }; |
| 137 | spi_xfer(SPI_CS_FLASH, xfer, 1); |
| 138 | } |
| 139 | |
| 140 | void |
| 141 | flash_deep_power_down(void) |
| 142 | { |
| 143 | flash_cmd(FLASH_CMD_DEEP_POWER_DOWN); |
| 144 | } |
| 145 | |
| 146 | void |
| 147 | flash_wake_up(void) |
| 148 | { |
| 149 | flash_cmd(FLASH_CMD_WAKE_UP); |
| 150 | } |
| 151 | |
| 152 | void |
| 153 | flash_write_enable(void) |
| 154 | { |
| 155 | flash_cmd(FLASH_CMD_WRITE_ENABLE); |
| 156 | } |
| 157 | |
| 158 | void |
| 159 | flash_write_enable_volatile(void) |
| 160 | { |
| 161 | flash_cmd(FLASH_CMD_WRITE_ENABLE_VOLATILE); |
| 162 | } |
| 163 | |
| 164 | void |
| 165 | flash_write_disable(void) |
| 166 | { |
| 167 | flash_cmd(FLASH_CMD_WRITE_DISABLE); |
| 168 | } |
| 169 | |
| 170 | void |
| 171 | flash_manuf_id(void *manuf) |
| 172 | { |
| 173 | uint8_t cmd = FLASH_CMD_READ_MANUF_ID; |
| 174 | struct spi_xfer_chunk xfer[2] = { |
| 175 | { .data = (void*)&cmd, .len = 1, .read = false, .write = true, }, |
| 176 | { .data = (void*)manuf, .len = 3, .read = true, .write = false, }, |
| 177 | }; |
| 178 | spi_xfer(SPI_CS_FLASH, xfer, 2); |
| 179 | } |
| 180 | |
| 181 | void |
| 182 | flash_unique_id(void *id) |
| 183 | { |
| 184 | uint8_t cmd = FLASH_CMD_READ_UNIQUE_ID; |
| 185 | struct spi_xfer_chunk xfer[3] = { |
| 186 | { .data = (void*)&cmd, .len = 1, .read = false, .write = true, }, |
| 187 | { .data = (void*)0, .len = 4, .read = false, .write = false, }, |
| 188 | { .data = (void*)id, .len = 8, .read = true, .write = false, }, |
| 189 | }; |
| 190 | spi_xfer(SPI_CS_FLASH, xfer, 3); |
| 191 | } |
| 192 | |
| 193 | uint8_t |
| 194 | flash_read_sr(void) |
| 195 | { |
| 196 | uint8_t cmd = FLASH_CMD_READ_SR1; |
| 197 | uint8_t rv; |
| 198 | struct spi_xfer_chunk xfer[2] = { |
| 199 | { .data = (void*)&cmd, .len = 1, .read = false, .write = true, }, |
| 200 | { .data = (void*)&rv, .len = 1, .read = true, .write = false, }, |
| 201 | }; |
| 202 | spi_xfer(SPI_CS_FLASH, xfer, 2); |
| 203 | return rv; |
| 204 | } |
| 205 | |
| 206 | void |
| 207 | flash_write_sr(uint8_t sr) |
| 208 | { |
| 209 | uint8_t cmd[2] = { FLASH_CMD_WRITE_SR1, sr }; |
| 210 | struct spi_xfer_chunk xfer[1] = { |
| 211 | { .data = (void*)cmd, .len = 2, .read = false, .write = true, }, |
| 212 | }; |
| 213 | spi_xfer(SPI_CS_FLASH, xfer, 1); |
| 214 | } |
| 215 | |
| 216 | void |
| 217 | flash_read(void *dst, uint32_t addr, unsigned len) |
| 218 | { |
| 219 | uint8_t cmd[4] = { FLASH_CMD_READ_DATA, ((addr >> 16) & 0xff), ((addr >> 8) & 0xff), (addr & 0xff) }; |
| 220 | struct spi_xfer_chunk xfer[2] = { |
| 221 | { .data = (void*)cmd, .len = 4, .read = false, .write = true, }, |
| 222 | { .data = (void*)dst, .len = len, .read = true, .write = false, }, |
| 223 | }; |
| 224 | spi_xfer(SPI_CS_FLASH, xfer, 2); |
| 225 | } |
| 226 | |
| 227 | void |
Sylvain Munaut | c5f3f77 | 2020-10-28 21:58:57 +0100 | [diff] [blame] | 228 | flash_page_program(const void *src, uint32_t addr, unsigned len) |
Sylvain Munaut | 26bc465 | 2020-09-14 10:19:49 +0200 | [diff] [blame] | 229 | { |
| 230 | uint8_t cmd[4] = { FLASH_CMD_PAGE_PROGRAM, ((addr >> 16) & 0xff), ((addr >> 8) & 0xff), (addr & 0xff) }; |
| 231 | struct spi_xfer_chunk xfer[2] = { |
| 232 | { .data = (void*)cmd, .len = 4, .read = false, .write = true, }, |
| 233 | { .data = (void*)src, .len = len, .read = false, .write = true, }, |
| 234 | }; |
| 235 | spi_xfer(SPI_CS_FLASH, xfer, 2); |
| 236 | } |
| 237 | |
| 238 | void |
| 239 | flash_sector_erase(uint32_t addr) |
| 240 | { |
| 241 | uint8_t cmd[4] = { FLASH_CMD_SECTOR_ERASE, ((addr >> 16) & 0xff), ((addr >> 8) & 0xff), (addr & 0xff) }; |
| 242 | struct spi_xfer_chunk xfer[1] = { |
| 243 | { .data = (void*)cmd, .len = 4, .read = false, .write = true, }, |
| 244 | }; |
| 245 | spi_xfer(SPI_CS_FLASH, xfer, 1); |
| 246 | } |